ata_wdc.c revision 1.101
1 /* $NetBSD: ata_wdc.c,v 1.101 2012/07/31 15:50:34 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: ata_wdc.c,v 1.101 2012/07/31 15:50:34 bouyer Exp $"); 58 59 #include "opt_ata.h" 60 #include "opt_wdc.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/file.h> 66 #include <sys/stat.h> 67 #include <sys/buf.h> 68 #include <sys/bufq.h> 69 #include <sys/malloc.h> 70 #include <sys/device.h> 71 #include <sys/disklabel.h> 72 #include <sys/syslog.h> 73 #include <sys/proc.h> 74 75 #include <sys/intr.h> 76 #include <sys/bus.h> 77 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 78 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 79 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 80 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 81 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 82 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 83 84 #include <dev/ata/ataconf.h> 85 #include <dev/ata/atareg.h> 86 #include <dev/ata/atavar.h> 87 #include <dev/ic/wdcreg.h> 88 #include <dev/ic/wdcvar.h> 89 90 #define DEBUG_INTR 0x01 91 #define DEBUG_XFERS 0x02 92 #define DEBUG_STATUS 0x04 93 #define DEBUG_FUNCS 0x08 94 #define DEBUG_PROBE 0x10 95 #ifdef ATADEBUG 96 extern int wdcdebug_wd_mask; /* inited in wd.c */ 97 #define ATADEBUG_PRINT(args, level) \ 98 if (wdcdebug_wd_mask & (level)) \ 99 printf args 100 #else 101 #define ATADEBUG_PRINT(args, level) 102 #endif 103 104 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 105 106 static int wdc_ata_bio(struct ata_drive_datas*, struct ata_bio*); 107 static void wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 108 static void _wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 109 static int wdc_ata_bio_intr(struct ata_channel *, struct ata_xfer *, 110 int); 111 static void wdc_ata_bio_kill_xfer(struct ata_channel *, 112 struct ata_xfer *, int); 113 static void wdc_ata_bio_done(struct ata_channel *, struct ata_xfer *); 114 static int wdc_ata_err(struct ata_drive_datas *, struct ata_bio *); 115 #define WDC_ATA_NOERR 0x00 /* Drive doesn't report an error */ 116 #define WDC_ATA_RECOV 0x01 /* There was a recovered error */ 117 #define WDC_ATA_ERR 0x02 /* Drive reports an error */ 118 static int wdc_ata_addref(struct ata_drive_datas *); 119 static void wdc_ata_delref(struct ata_drive_datas *); 120 121 const struct ata_bustype wdc_ata_bustype = { 122 SCSIPI_BUSTYPE_ATA, 123 wdc_ata_bio, 124 wdc_reset_drive, 125 wdc_reset_channel, 126 wdc_exec_command, 127 ata_get_params, 128 wdc_ata_addref, 129 wdc_ata_delref, 130 ata_kill_pending, 131 }; 132 133 /* 134 * Handle block I/O operation. Return ATACMD_COMPLETE, ATACMD_QUEUED, or 135 * ATACMD_TRY_AGAIN. Must be called at splbio(). 136 */ 137 static int 138 wdc_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 139 { 140 struct ata_xfer *xfer; 141 struct ata_channel *chp = drvp->chnl_softc; 142 struct atac_softc *atac = chp->ch_atac; 143 144 xfer = ata_get_xfer(ATAXF_NOSLEEP); 145 if (xfer == NULL) 146 return ATACMD_TRY_AGAIN; 147 if (atac->atac_cap & ATAC_CAP_NOIRQ) 148 ata_bio->flags |= ATA_POLL; 149 if (ata_bio->flags & ATA_POLL) 150 xfer->c_flags |= C_POLL; 151 #if NATA_DMA 152 if ((drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) && 153 (ata_bio->flags & ATA_SINGLE) == 0) 154 xfer->c_flags |= C_DMA; 155 #endif 156 #if NATA_DMA && NATA_PIOBM 157 else 158 #endif 159 #if NATA_PIOBM 160 if (atac->atac_cap & ATAC_CAP_PIOBM) 161 xfer->c_flags |= C_PIOBM; 162 #endif 163 xfer->c_drive = drvp->drive; 164 xfer->c_cmd = ata_bio; 165 xfer->c_databuf = ata_bio->databuf; 166 xfer->c_bcount = ata_bio->bcount; 167 xfer->c_start = wdc_ata_bio_start; 168 xfer->c_intr = wdc_ata_bio_intr; 169 xfer->c_kill_xfer = wdc_ata_bio_kill_xfer; 170 ata_exec_xfer(chp, xfer); 171 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 172 } 173 174 static void 175 wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 176 { 177 struct atac_softc *atac = chp->ch_atac; 178 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 179 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 180 struct ata_bio *ata_bio = xfer->c_cmd; 181 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 182 int wait_flags; 183 const char *errstring; 184 #ifdef WDC_NO_IDS 185 wait_flags = AT_POLL; 186 #else 187 wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 188 #endif 189 190 ATADEBUG_PRINT(("wdc_ata_bio_start %s:%d:%d state %d drive_flags 0x%x " 191 "c_flags 0x%x ch_flags 0x%x\n", 192 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 193 drvp->state, drvp->drive_flags, xfer->c_flags, chp->ch_flags), 194 DEBUG_XFERS); 195 196 /* Do control operations specially. */ 197 if (__predict_false(drvp->state < READY)) { 198 /* 199 * Actually, we want to be careful not to mess with the control 200 * state if the device is currently busy, but we can assume 201 * that we never get to this point if that's the case. 202 */ 203 /* If it's not a polled command, we need the kernel thread */ 204 if ((xfer->c_flags & C_POLL) == 0 && 205 (chp->ch_flags & ATACH_TH_RUN) == 0) { 206 chp->ch_queue->queue_freeze++; 207 wakeup(&chp->ch_thread); 208 return; 209 } 210 /* 211 * disable interrupts, all commands here should be quick 212 * enough to be able to poll, and we don't go here that often 213 */ 214 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 215 WDCTL_4BIT | WDCTL_IDS); 216 if (wdc->select) 217 wdc->select(chp, xfer->c_drive); 218 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 219 WDSD_IBM | (xfer->c_drive << 4)); 220 DELAY(10); 221 errstring = "wait"; 222 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 223 goto ctrltimeout; 224 wdccommandshort(chp, xfer->c_drive, WDCC_RECAL); 225 /* Wait for at last 400ns for status bit to be valid */ 226 DELAY(1); 227 errstring = "recal"; 228 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 229 goto ctrltimeout; 230 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 231 goto ctrlerror; 232 /* Don't try to set modes if controller can't be adjusted */ 233 if (atac->atac_set_modes == NULL) 234 goto geometry; 235 /* Also don't try if the drive didn't report its mode */ 236 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 237 goto geometry; 238 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 239 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 240 errstring = "piomode"; 241 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 242 goto ctrltimeout; 243 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 244 goto ctrlerror; 245 #if NATA_DMA 246 #if NATA_UDMA 247 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 248 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 249 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 250 } else 251 #endif 252 if (drvp->drive_flags & ATA_DRIVE_DMA) { 253 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 254 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 255 } else { 256 goto geometry; 257 } 258 errstring = "dmamode"; 259 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 260 goto ctrltimeout; 261 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 262 goto ctrlerror; 263 #endif /* NATA_DMA */ 264 geometry: 265 if (ata_bio->flags & ATA_LBA) 266 goto multimode; 267 wdccommand(chp, xfer->c_drive, WDCC_IDP, 268 ata_bio->lp->d_ncylinders, 269 ata_bio->lp->d_ntracks - 1, 0, ata_bio->lp->d_nsectors, 270 (ata_bio->lp->d_type == DTYPE_ST506) ? 271 ata_bio->lp->d_precompcyl / 4 : 0); 272 errstring = "geometry"; 273 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 274 goto ctrltimeout; 275 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 276 goto ctrlerror; 277 multimode: 278 if (ata_bio->multi == 1) 279 goto ready; 280 wdccommand(chp, xfer->c_drive, WDCC_SETMULTI, 0, 0, 0, 281 ata_bio->multi, 0); 282 errstring = "setmulti"; 283 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 284 goto ctrltimeout; 285 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 286 goto ctrlerror; 287 ready: 288 drvp->state = READY; 289 /* 290 * The drive is usable now 291 */ 292 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 293 WDCTL_4BIT); 294 delay(10); /* some drives need a little delay here */ 295 } 296 297 _wdc_ata_bio_start(chp, xfer); 298 return; 299 ctrltimeout: 300 printf("%s:%d:%d: %s timed out\n", 301 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 302 errstring); 303 ata_bio->error = TIMEOUT; 304 goto ctrldone; 305 ctrlerror: 306 printf("%s:%d:%d: %s ", 307 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 308 errstring); 309 if (chp->ch_status & WDCS_DWF) { 310 printf("drive fault\n"); 311 ata_bio->error = ERR_DF; 312 } else { 313 printf("error (%x)\n", chp->ch_error); 314 ata_bio->r_error = chp->ch_error; 315 ata_bio->error = ERROR; 316 } 317 ctrldone: 318 drvp->state = 0; 319 wdc_ata_bio_done(chp, xfer); 320 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 321 return; 322 } 323 324 static void 325 _wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 326 { 327 struct atac_softc *atac = chp->ch_atac; 328 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 329 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 330 struct ata_bio *ata_bio = xfer->c_cmd; 331 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 332 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 333 u_int16_t cyl; 334 u_int8_t head, sect, cmd = 0; 335 int nblks; 336 #if NATA_DMA || NATA_PIOBM 337 int error, dma_flags = 0; 338 #endif 339 340 ATADEBUG_PRINT(("_wdc_ata_bio_start %s:%d:%d\n", 341 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 342 DEBUG_INTR | DEBUG_XFERS); 343 344 #if NATA_DMA || NATA_PIOBM 345 if (xfer->c_flags & (C_DMA | C_PIOBM)) { 346 #if NATA_DMA 347 if (drvp->n_xfers <= NXFER) 348 drvp->n_xfers++; 349 #endif 350 dma_flags = (ata_bio->flags & ATA_READ) ? WDC_DMA_READ : 0; 351 if (ata_bio->flags & ATA_LBA48) 352 dma_flags |= WDC_DMA_LBA48; 353 } 354 #endif 355 again: 356 /* 357 * 358 * When starting a multi-sector transfer, or doing single-sector 359 * transfers... 360 */ 361 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 362 if (ata_bio->flags & ATA_SINGLE) 363 nblks = 1; 364 else 365 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 366 /* Check for bad sectors and adjust transfer, if necessary. */ 367 if ((ata_bio->lp->d_flags & D_BADSECT) != 0) { 368 long blkdiff; 369 int i; 370 for (i = 0; (blkdiff = ata_bio->badsect[i]) != -1; 371 i++) { 372 blkdiff -= ata_bio->blkno; 373 if (blkdiff < 0) 374 continue; 375 if (blkdiff == 0) { 376 /* Replace current block of transfer. */ 377 ata_bio->blkno = 378 ata_bio->lp->d_secperunit - 379 ata_bio->lp->d_nsectors - i - 1; 380 } 381 if (blkdiff < nblks) { 382 /* Bad block inside transfer. */ 383 ata_bio->flags |= ATA_SINGLE; 384 nblks = 1; 385 } 386 break; 387 } 388 /* Transfer is okay now. */ 389 } 390 if (ata_bio->flags & ATA_LBA48) { 391 sect = 0; 392 cyl = 0; 393 head = 0; 394 } else if (ata_bio->flags & ATA_LBA) { 395 sect = (ata_bio->blkno >> 0) & 0xff; 396 cyl = (ata_bio->blkno >> 8) & 0xffff; 397 head = (ata_bio->blkno >> 24) & 0x0f; 398 head |= WDSD_LBA; 399 } else { 400 int blkno = ata_bio->blkno; 401 sect = blkno % ata_bio->lp->d_nsectors; 402 sect++; /* Sectors begin with 1, not 0. */ 403 blkno /= ata_bio->lp->d_nsectors; 404 head = blkno % ata_bio->lp->d_ntracks; 405 blkno /= ata_bio->lp->d_ntracks; 406 cyl = blkno; 407 head |= WDSD_CHS; 408 } 409 #if NATA_DMA 410 if (xfer->c_flags & C_DMA) { 411 ata_bio->nblks = nblks; 412 ata_bio->nbytes = xfer->c_bcount; 413 cmd = (ata_bio->flags & ATA_READ) ? 414 WDCC_READDMA : WDCC_WRITEDMA; 415 /* Init the DMA channel. */ 416 error = (*wdc->dma_init)(wdc->dma_arg, 417 chp->ch_channel, xfer->c_drive, 418 (char *)xfer->c_databuf + xfer->c_skip, 419 ata_bio->nbytes, dma_flags); 420 if (error) { 421 if (error == EINVAL) { 422 /* 423 * We can't do DMA on this transfer 424 * for some reason. Fall back to 425 * PIO. 426 */ 427 xfer->c_flags &= ~C_DMA; 428 error = 0; 429 goto do_pio; 430 } 431 ata_bio->error = ERR_DMA; 432 ata_bio->r_error = 0; 433 wdc_ata_bio_done(chp, xfer); 434 return; 435 } 436 /* Initiate command */ 437 if (wdc->select) 438 wdc->select(chp, xfer->c_drive); 439 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 440 0, WDSD_IBM | (xfer->c_drive << 4)); 441 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags)) { 442 case WDCWAIT_OK: 443 break; 444 case WDCWAIT_TOUT: 445 goto timeout; 446 case WDCWAIT_THR: 447 return; 448 } 449 if (ata_bio->flags & ATA_LBA48) { 450 wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd), 451 (u_int64_t)ata_bio->blkno, nblks, 0); 452 } else { 453 wdccommand(chp, xfer->c_drive, cmd, cyl, 454 head, sect, nblks, 0); 455 } 456 /* start the DMA channel */ 457 (*wdc->dma_start)(wdc->dma_arg, 458 chp->ch_channel, xfer->c_drive); 459 chp->ch_flags |= ATACH_DMA_WAIT; 460 /* start timeout machinery */ 461 if ((xfer->c_flags & C_POLL) == 0) 462 callout_reset(&chp->ch_callout, 463 ATA_DELAY / 1000 * hz, wdctimeout, chp); 464 /* wait for irq */ 465 goto intr; 466 } /* else not DMA */ 467 do_pio: 468 #endif /* NATA_DMA */ 469 #if NATA_PIOBM 470 if ((xfer->c_flags & C_PIOBM) && xfer->c_skip == 0) { 471 if (ata_bio->flags & ATA_POLL) { 472 /* XXX not supported yet --- fall back to PIO */ 473 xfer->c_flags &= ~C_PIOBM; 474 } else { 475 /* Init the DMA channel. */ 476 error = (*wdc->dma_init)(wdc->dma_arg, 477 chp->ch_channel, xfer->c_drive, 478 (char *)xfer->c_databuf + xfer->c_skip, 479 xfer->c_bcount, 480 dma_flags | WDC_DMA_PIOBM_ATA); 481 if (error) { 482 if (error == EINVAL) { 483 /* 484 * We can't do DMA on this 485 * transfer for some reason. 486 * Fall back to PIO. 487 */ 488 xfer->c_flags &= ~C_PIOBM; 489 error = 0; 490 } else { 491 ata_bio->error = ERR_DMA; 492 ata_bio->r_error = 0; 493 wdc_ata_bio_done(chp, xfer); 494 return; 495 } 496 } 497 } 498 } 499 #endif 500 ata_bio->nblks = min(nblks, ata_bio->multi); 501 ata_bio->nbytes = ata_bio->nblks * ata_bio->lp->d_secsize; 502 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 503 if (ata_bio->nblks > 1) { 504 cmd = (ata_bio->flags & ATA_READ) ? 505 WDCC_READMULTI : WDCC_WRITEMULTI; 506 } else { 507 cmd = (ata_bio->flags & ATA_READ) ? 508 WDCC_READ : WDCC_WRITE; 509 } 510 /* Initiate command! */ 511 if (wdc->select) 512 wdc->select(chp, xfer->c_drive); 513 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 514 WDSD_IBM | (xfer->c_drive << 4)); 515 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags)) { 516 case WDCWAIT_OK: 517 break; 518 case WDCWAIT_TOUT: 519 goto timeout; 520 case WDCWAIT_THR: 521 return; 522 } 523 if (ata_bio->flags & ATA_LBA48) { 524 wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd), 525 (u_int64_t)ata_bio->blkno, nblks, 0); 526 } else { 527 wdccommand(chp, xfer->c_drive, cmd, cyl, 528 head, sect, nblks, 529 (ata_bio->lp->d_type == DTYPE_ST506) ? 530 ata_bio->lp->d_precompcyl / 4 : 0); 531 } 532 /* start timeout machinery */ 533 if ((xfer->c_flags & C_POLL) == 0) 534 callout_reset(&chp->ch_callout, 535 ATA_DELAY / 1000 * hz, wdctimeout, chp); 536 } else if (ata_bio->nblks > 1) { 537 /* The number of blocks in the last stretch may be smaller. */ 538 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 539 if (ata_bio->nblks > nblks) { 540 ata_bio->nblks = nblks; 541 ata_bio->nbytes = xfer->c_bcount; 542 } 543 } 544 /* If this was a write and not using DMA, push the data. */ 545 if ((ata_bio->flags & ATA_READ) == 0) { 546 /* 547 * we have to busy-wait here, we can't rely on running in 548 * thread context. 549 */ 550 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL) != 0) { 551 printf("%s:%d:%d: timeout waiting for DRQ, " 552 "st=0x%02x, err=0x%02x\n", 553 device_xname(atac->atac_dev), chp->ch_channel, 554 xfer->c_drive, chp->ch_status, chp->ch_error); 555 if (wdc_ata_err(drvp, ata_bio) != WDC_ATA_ERR) 556 ata_bio->error = TIMEOUT; 557 wdc_ata_bio_done(chp, xfer); 558 return; 559 } 560 if (wdc_ata_err(drvp, ata_bio) == WDC_ATA_ERR) { 561 wdc_ata_bio_done(chp, xfer); 562 return; 563 } 564 #if NATA_PIOBM 565 if (xfer->c_flags & C_PIOBM) { 566 /* start the busmastering PIO */ 567 (*wdc->piobm_start)(wdc->dma_arg, 568 chp->ch_channel, xfer->c_drive, 569 xfer->c_skip, ata_bio->nbytes, 0); 570 chp->ch_flags |= ATACH_DMA_WAIT; 571 } else 572 #endif 573 574 wdc->dataout_pio(chp, drvp->drive_flags, 575 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 576 } 577 578 #if NATA_DMA 579 intr: 580 #endif 581 /* Wait for IRQ (either real or polled) */ 582 if ((ata_bio->flags & ATA_POLL) == 0) { 583 chp->ch_flags |= ATACH_IRQ_WAIT; 584 } else { 585 /* Wait for at last 400ns for status bit to be valid */ 586 delay(1); 587 #if NATA_DMA 588 if (chp->ch_flags & ATACH_DMA_WAIT) { 589 wdc_dmawait(chp, xfer, ATA_DELAY); 590 chp->ch_flags &= ~ATACH_DMA_WAIT; 591 } 592 #endif 593 wdc_ata_bio_intr(chp, xfer, 0); 594 if ((ata_bio->flags & ATA_ITSDONE) == 0) 595 goto again; 596 } 597 return; 598 timeout: 599 printf("%s:%d:%d: not ready, st=0x%02x, err=0x%02x\n", 600 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 601 chp->ch_status, chp->ch_error); 602 if (wdc_ata_err(drvp, ata_bio) != WDC_ATA_ERR) 603 ata_bio->error = TIMEOUT; 604 wdc_ata_bio_done(chp, xfer); 605 return; 606 } 607 608 static int 609 wdc_ata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 610 { 611 struct atac_softc *atac = chp->ch_atac; 612 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 613 struct ata_bio *ata_bio = xfer->c_cmd; 614 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 615 int drv_err; 616 617 ATADEBUG_PRINT(("wdc_ata_bio_intr %s:%d:%d\n", 618 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 619 DEBUG_INTR | DEBUG_XFERS); 620 621 622 /* Is it not a transfer, but a control operation? */ 623 if (drvp->state < READY) { 624 printf("%s:%d:%d: bad state %d in wdc_ata_bio_intr\n", 625 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 626 drvp->state); 627 panic("wdc_ata_bio_intr: bad state"); 628 } 629 630 /* 631 * if we missed an interrupt in a PIO transfer, reset and restart. 632 * Don't try to continue transfer, we may have missed cycles. 633 */ 634 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 635 ata_bio->error = TIMEOUT; 636 wdc_ata_bio_done(chp, xfer); 637 return 1; 638 } 639 640 #if NATA_PIOBM 641 /* Transfer-done interrupt for busmastering PIO read */ 642 if ((xfer->c_flags & C_PIOBM) && (chp->ch_flags & ATACH_PIOBM_WAIT)) { 643 chp->ch_flags &= ~ATACH_PIOBM_WAIT; 644 goto end; 645 } 646 #endif 647 648 /* Ack interrupt done by wdc_wait_for_unbusy */ 649 if (wdc_wait_for_unbusy(chp, (irq == 0) ? ATA_DELAY : 0, AT_POLL) < 0) { 650 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 651 return 0; /* IRQ was not for us */ 652 printf("%s:%d:%d: device timeout, c_bcount=%d, c_skip%d\n", 653 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 654 xfer->c_bcount, xfer->c_skip); 655 ata_bio->error = TIMEOUT; 656 wdc_ata_bio_done(chp, xfer); 657 return 1; 658 } 659 if (wdc->irqack) 660 wdc->irqack(chp); 661 662 drv_err = wdc_ata_err(drvp, ata_bio); 663 664 #if NATA_DMA 665 /* If we were using DMA, Turn off the DMA channel and check for error */ 666 if (xfer->c_flags & C_DMA) { 667 if (ata_bio->flags & ATA_POLL) { 668 /* 669 * IDE drives deassert WDCS_BSY before transfer is 670 * complete when using DMA. Polling for DRQ to deassert 671 * is not enough DRQ is not required to be 672 * asserted for DMA transfers, so poll for DRDY. 673 */ 674 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 675 ATA_DELAY, ATA_POLL) == WDCWAIT_TOUT) { 676 printf("%s:%d:%d: polled transfer timed out " 677 "(st=0x%x)\n", 678 device_xname(atac->atac_dev), 679 chp->ch_channel, xfer->c_drive, 680 chp->ch_status); 681 ata_bio->error = TIMEOUT; 682 drv_err = WDC_ATA_ERR; 683 } 684 } 685 if (wdc->dma_status != 0) { 686 if (drv_err != WDC_ATA_ERR) { 687 ata_bio->error = ERR_DMA; 688 drv_err = WDC_ATA_ERR; 689 } 690 } 691 if (chp->ch_status & WDCS_DRQ) { 692 if (drv_err != WDC_ATA_ERR) { 693 printf("%s:%d:%d: intr with DRQ (st=0x%x)\n", 694 device_xname(atac->atac_dev), 695 chp->ch_channel, 696 xfer->c_drive, chp->ch_status); 697 ata_bio->error = TIMEOUT; 698 drv_err = WDC_ATA_ERR; 699 } 700 } 701 if (drv_err != WDC_ATA_ERR) 702 goto end; 703 if (ata_bio->r_error & WDCE_CRC || ata_bio->error == ERR_DMA) 704 ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0); 705 } 706 #endif /* NATA_DMA */ 707 708 /* if we had an error, end */ 709 if (drv_err == WDC_ATA_ERR) { 710 wdc_ata_bio_done(chp, xfer); 711 return 1; 712 } 713 714 /* If this was a read and not using DMA, fetch the data. */ 715 if ((ata_bio->flags & ATA_READ) != 0) { 716 if ((chp->ch_status & WDCS_DRQ) != WDCS_DRQ) { 717 printf("%s:%d:%d: read intr before drq\n", 718 device_xname(atac->atac_dev), chp->ch_channel, 719 xfer->c_drive); 720 ata_bio->error = TIMEOUT; 721 wdc_ata_bio_done(chp, xfer); 722 return 1; 723 } 724 #if NATA_PIOBM 725 if (xfer->c_flags & C_PIOBM) { 726 /* start the busmastering PIO */ 727 (*wdc->piobm_start)(wdc->dma_arg, 728 chp->ch_channel, xfer->c_drive, 729 xfer->c_skip, ata_bio->nbytes, 730 WDC_PIOBM_XFER_IRQ); 731 chp->ch_flags |= ATACH_DMA_WAIT | ATACH_PIOBM_WAIT | ATACH_IRQ_WAIT; 732 return 1; 733 } else 734 #endif 735 wdc->datain_pio(chp, drvp->drive_flags, 736 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 737 } 738 739 #if NATA_DMA || NATA_PIOBM 740 end: 741 #endif 742 ata_bio->blkno += ata_bio->nblks; 743 ata_bio->blkdone += ata_bio->nblks; 744 xfer->c_skip += ata_bio->nbytes; 745 xfer->c_bcount -= ata_bio->nbytes; 746 /* See if this transfer is complete. */ 747 if (xfer->c_bcount > 0) { 748 if ((ata_bio->flags & ATA_POLL) == 0) { 749 /* Start the next operation */ 750 _wdc_ata_bio_start(chp, xfer); 751 } else { 752 /* Let _wdc_ata_bio_start do the loop */ 753 return 1; 754 } 755 } else { /* Done with this transfer */ 756 ata_bio->error = NOERROR; 757 wdc_ata_bio_done(chp, xfer); 758 } 759 return 1; 760 } 761 762 static void 763 wdc_ata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 764 int reason) 765 { 766 struct ata_bio *ata_bio = xfer->c_cmd; 767 int drive = xfer->c_drive; 768 769 ata_free_xfer(chp, xfer); 770 771 ata_bio->flags |= ATA_ITSDONE; 772 switch (reason) { 773 case KILL_GONE: 774 ata_bio->error = ERR_NODEV; 775 break; 776 case KILL_RESET: 777 ata_bio->error = ERR_RESET; 778 break; 779 default: 780 printf("wdc_ata_bio_kill_xfer: unknown reason %d\n", 781 reason); 782 panic("wdc_ata_bio_kill_xfer"); 783 } 784 ata_bio->r_error = WDCE_ABRT; 785 ATADEBUG_PRINT(("wdc_ata_bio_kill_xfer: drv_done\n"), DEBUG_XFERS); 786 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 787 } 788 789 static void 790 wdc_ata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 791 { 792 struct ata_bio *ata_bio = xfer->c_cmd; 793 int drive = xfer->c_drive; 794 795 ATADEBUG_PRINT(("wdc_ata_bio_done %s:%d:%d: flags 0x%x\n", 796 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 797 xfer->c_drive, (u_int)xfer->c_flags), 798 DEBUG_XFERS); 799 800 callout_stop(&chp->ch_callout); 801 802 /* feed back residual bcount to our caller */ 803 ata_bio->bcount = xfer->c_bcount; 804 805 /* mark controller inactive and free xfer */ 806 chp->ch_queue->active_xfer = NULL; 807 ata_free_xfer(chp, xfer); 808 809 if (chp->ch_drive[drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 810 ata_bio->error = ERR_NODEV; 811 chp->ch_drive[drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 812 wakeup(&chp->ch_queue->active_xfer); 813 } 814 ata_bio->flags |= ATA_ITSDONE; 815 ATADEBUG_PRINT(("wdc_ata_done: drv_done\n"), DEBUG_XFERS); 816 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 817 ATADEBUG_PRINT(("atastart from wdc_ata_done, flags 0x%x\n", 818 chp->ch_flags), DEBUG_XFERS); 819 atastart(chp); 820 } 821 822 static int 823 wdc_ata_err(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 824 { 825 struct ata_channel *chp = drvp->chnl_softc; 826 ata_bio->error = 0; 827 if (chp->ch_status & WDCS_BSY) { 828 ata_bio->error = TIMEOUT; 829 return WDC_ATA_ERR; 830 } 831 832 if (chp->ch_status & WDCS_DWF) { 833 ata_bio->error = ERR_DF; 834 return WDC_ATA_ERR; 835 } 836 837 if (chp->ch_status & WDCS_ERR) { 838 ata_bio->error = ERROR; 839 ata_bio->r_error = chp->ch_error; 840 if (ata_bio->r_error & (WDCE_BBK | WDCE_UNC | WDCE_IDNF | 841 WDCE_ABRT | WDCE_TK0NF | WDCE_AMNF)) 842 return WDC_ATA_ERR; 843 return WDC_ATA_NOERR; 844 } 845 846 if (chp->ch_status & WDCS_CORR) 847 ata_bio->flags |= ATA_CORR; 848 return WDC_ATA_NOERR; 849 } 850 851 static int 852 wdc_ata_addref(struct ata_drive_datas *drvp) 853 { 854 struct ata_channel *chp = drvp->chnl_softc; 855 856 return (ata_addref(chp)); 857 } 858 859 static void 860 wdc_ata_delref(struct ata_drive_datas *drvp) 861 { 862 struct ata_channel *chp = drvp->chnl_softc; 863 864 ata_delref(chp); 865 } 866
Indexes created Mon Sep 29 21:09:56 GMT 2025