ata_wdc.c revision 1.105.6.4
1 /* $NetBSD: ata_wdc.c,v 1.105.6.4 2017/06/16 20:40:49 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: ata_wdc.c,v 1.105.6.4 2017/06/16 20:40:49 jdolecek Exp $"); 58 59 #include "opt_ata.h" 60 #include "opt_wdc.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/file.h> 66 #include <sys/stat.h> 67 #include <sys/buf.h> 68 #include <sys/bufq.h> 69 #include <sys/malloc.h> 70 #include <sys/device.h> 71 #include <sys/disklabel.h> 72 #include <sys/syslog.h> 73 #include <sys/proc.h> 74 75 #include <sys/intr.h> 76 #include <sys/bus.h> 77 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 78 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 79 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 80 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 81 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 82 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 83 84 #include <dev/ata/ataconf.h> 85 #include <dev/ata/atareg.h> 86 #include <dev/ata/atavar.h> 87 #include <dev/ic/wdcreg.h> 88 #include <dev/ic/wdcvar.h> 89 90 #define DEBUG_INTR 0x01 91 #define DEBUG_XFERS 0x02 92 #define DEBUG_STATUS 0x04 93 #define DEBUG_FUNCS 0x08 94 #define DEBUG_PROBE 0x10 95 #ifdef ATADEBUG 96 extern int wdcdebug_wd_mask; /* inited in wd.c */ 97 #define ATADEBUG_PRINT(args, level) \ 98 if (wdcdebug_wd_mask & (level)) \ 99 printf args 100 #else 101 #define ATADEBUG_PRINT(args, level) 102 #endif 103 104 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 105 106 static int wdc_ata_bio(struct ata_drive_datas*, struct ata_xfer *); 107 static void wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 108 static void _wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 109 static int wdc_ata_bio_intr(struct ata_channel *, struct ata_xfer *, 110 int); 111 static void wdc_ata_bio_kill_xfer(struct ata_channel *, 112 struct ata_xfer *, int); 113 static void wdc_ata_bio_done(struct ata_channel *, struct ata_xfer *); 114 static int wdc_ata_err(struct ata_drive_datas *, struct ata_bio *); 115 #define WDC_ATA_NOERR 0x00 /* Drive doesn't report an error */ 116 #define WDC_ATA_RECOV 0x01 /* There was a recovered error */ 117 #define WDC_ATA_ERR 0x02 /* Drive reports an error */ 118 static int wdc_ata_addref(struct ata_drive_datas *); 119 static void wdc_ata_delref(struct ata_drive_datas *); 120 121 const struct ata_bustype wdc_ata_bustype = { 122 SCSIPI_BUSTYPE_ATA, 123 wdc_ata_bio, 124 wdc_reset_drive, 125 wdc_reset_channel, 126 wdc_exec_command, 127 ata_get_params, 128 wdc_ata_addref, 129 wdc_ata_delref, 130 ata_kill_pending, 131 }; 132 133 /* 134 * Handle block I/O operation. Return ATACMD_COMPLETE, ATACMD_QUEUED, or 135 * ATACMD_TRY_AGAIN. Must be called at splbio(). 136 */ 137 static int 138 wdc_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 139 { 140 struct ata_channel *chp = drvp->chnl_softc; 141 struct atac_softc *atac = chp->ch_atac; 142 struct ata_bio *ata_bio = &xfer->c_bio; 143 144 if (atac->atac_cap & ATAC_CAP_NOIRQ) 145 ata_bio->flags |= ATA_POLL; 146 if (ata_bio->flags & ATA_POLL) 147 xfer->c_flags |= C_POLL; 148 #if NATA_DMA 149 if ((drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) && 150 (ata_bio->flags & ATA_SINGLE) == 0) 151 xfer->c_flags |= C_DMA; 152 #endif 153 #if NATA_DMA && NATA_PIOBM 154 else 155 #endif 156 #if NATA_PIOBM 157 if (atac->atac_cap & ATAC_CAP_PIOBM) 158 xfer->c_flags |= C_PIOBM; 159 #endif 160 xfer->c_drive = drvp->drive; 161 xfer->c_databuf = ata_bio->databuf; 162 xfer->c_bcount = ata_bio->bcount; 163 xfer->c_start = wdc_ata_bio_start; 164 xfer->c_intr = wdc_ata_bio_intr; 165 xfer->c_kill_xfer = wdc_ata_bio_kill_xfer; 166 ata_exec_xfer(chp, xfer); 167 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 168 } 169 170 static void 171 wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 172 { 173 struct atac_softc *atac = chp->ch_atac; 174 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 175 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 176 struct ata_bio *ata_bio = &xfer->c_bio; 177 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 178 int wait_flags; 179 const char *errstring; 180 #ifdef WDC_NO_IDS 181 wait_flags = AT_POLL; 182 #else 183 wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 184 #endif 185 186 ATADEBUG_PRINT(("wdc_ata_bio_start %s:%d:%d state %d drive_flags 0x%x " 187 "c_flags 0x%x ch_flags 0x%x\n", 188 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 189 drvp->state, drvp->drive_flags, xfer->c_flags, chp->ch_flags), 190 DEBUG_XFERS); 191 192 /* Do control operations specially. */ 193 if (__predict_false(drvp->state < READY)) { 194 /* 195 * Actually, we want to be careful not to mess with the control 196 * state if the device is currently busy, but we can assume 197 * that we never get to this point if that's the case. 198 */ 199 /* If it's not a polled command, we need the kernel thread */ 200 if ((xfer->c_flags & C_POLL) == 0 && 201 (chp->ch_flags & ATACH_TH_RUN) == 0) { 202 chp->ch_queue->queue_freeze++; 203 wakeup(&chp->ch_thread); 204 return; 205 } 206 /* 207 * disable interrupts, all commands here should be quick 208 * enough to be able to poll, and we don't go here that often 209 */ 210 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 211 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 212 wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS); 213 if (wdc->select) 214 wdc->select(chp, xfer->c_drive); 215 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 216 WDSD_IBM | (xfer->c_drive << 4)); 217 DELAY(10); 218 errstring = "wait"; 219 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 220 goto ctrltimeout; 221 wdccommandshort(chp, xfer->c_drive, WDCC_RECAL); 222 /* Wait for at last 400ns for status bit to be valid */ 223 DELAY(1); 224 errstring = "recal"; 225 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 226 goto ctrltimeout; 227 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 228 goto ctrlerror; 229 /* Don't try to set modes if controller can't be adjusted */ 230 if (atac->atac_set_modes == NULL) 231 goto geometry; 232 /* Also don't try if the drive didn't report its mode */ 233 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 234 goto geometry; 235 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 236 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 237 errstring = "piomode"; 238 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 239 goto ctrltimeout; 240 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 241 goto ctrlerror; 242 #if NATA_DMA 243 #if NATA_UDMA 244 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 245 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 246 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 247 } else 248 #endif 249 if (drvp->drive_flags & ATA_DRIVE_DMA) { 250 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 251 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 252 } else { 253 goto geometry; 254 } 255 errstring = "dmamode"; 256 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 257 goto ctrltimeout; 258 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 259 goto ctrlerror; 260 #endif /* NATA_DMA */ 261 geometry: 262 if (ata_bio->flags & ATA_LBA) 263 goto multimode; 264 wdccommand(chp, xfer->c_drive, WDCC_IDP, 265 drvp->lp->d_ncylinders, 266 drvp->lp->d_ntracks - 1, 0, drvp->lp->d_nsectors, 267 (drvp->lp->d_type == DKTYPE_ST506) ? 268 drvp->lp->d_precompcyl / 4 : 0); 269 errstring = "geometry"; 270 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 271 goto ctrltimeout; 272 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 273 goto ctrlerror; 274 multimode: 275 if (drvp->multi == 1) 276 goto ready; 277 wdccommand(chp, xfer->c_drive, WDCC_SETMULTI, 0, 0, 0, 278 drvp->multi, 0); 279 errstring = "setmulti"; 280 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 281 goto ctrltimeout; 282 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 283 goto ctrlerror; 284 ready: 285 drvp->state = READY; 286 /* 287 * The drive is usable now 288 */ 289 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 290 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 291 wd_aux_ctlr, WDCTL_4BIT); 292 delay(10); /* some drives need a little delay here */ 293 } 294 295 _wdc_ata_bio_start(chp, xfer); 296 return; 297 ctrltimeout: 298 printf("%s:%d:%d: %s timed out\n", 299 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 300 errstring); 301 ata_bio->error = TIMEOUT; 302 goto ctrldone; 303 ctrlerror: 304 printf("%s:%d:%d: %s ", 305 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 306 errstring); 307 if (chp->ch_status & WDCS_DWF) { 308 printf("drive fault\n"); 309 ata_bio->error = ERR_DF; 310 } else { 311 printf("error (%x)\n", chp->ch_error); 312 ata_bio->r_error = chp->ch_error; 313 ata_bio->error = ERROR; 314 } 315 ctrldone: 316 drvp->state = 0; 317 wdc_ata_bio_done(chp, xfer); 318 319 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 320 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 321 WDCTL_4BIT); 322 return; 323 } 324 325 static void 326 _wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 327 { 328 struct atac_softc *atac = chp->ch_atac; 329 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 330 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 331 struct ata_bio *ata_bio = &xfer->c_bio; 332 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 333 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 334 uint16_t cyl; 335 uint8_t head, sect, cmd = 0; 336 int nblks; 337 #if NATA_DMA || NATA_PIOBM 338 int error, dma_flags = 0; 339 #endif 340 341 ATADEBUG_PRINT(("_wdc_ata_bio_start %s:%d:%d\n", 342 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 343 DEBUG_INTR | DEBUG_XFERS); 344 345 #if NATA_DMA || NATA_PIOBM 346 if (xfer->c_flags & (C_DMA | C_PIOBM)) { 347 #if NATA_DMA 348 if (drvp->n_xfers <= NXFER) 349 drvp->n_xfers++; 350 #endif 351 dma_flags = (ata_bio->flags & ATA_READ) ? WDC_DMA_READ : 0; 352 if (ata_bio->flags & ATA_LBA48) 353 dma_flags |= WDC_DMA_LBA48; 354 } 355 #endif 356 again: 357 /* 358 * 359 * When starting a multi-sector transfer, or doing single-sector 360 * transfers... 361 */ 362 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 363 if (ata_bio->flags & ATA_SINGLE) 364 nblks = 1; 365 else 366 nblks = xfer->c_bcount / drvp->lp->d_secsize; 367 /* Check for bad sectors and adjust transfer, if necessary. */ 368 if ((drvp->lp->d_flags & D_BADSECT) != 0) { 369 long blkdiff; 370 int i; 371 for (i = 0; (blkdiff = drvp->badsect[i]) != -1; 372 i++) { 373 blkdiff -= ata_bio->blkno; 374 if (blkdiff < 0) 375 continue; 376 if (blkdiff == 0) { 377 /* Replace current block of transfer. */ 378 ata_bio->blkno = 379 drvp->lp->d_secperunit - 380 drvp->lp->d_nsectors - i - 1; 381 } 382 if (blkdiff < nblks) { 383 /* Bad block inside transfer. */ 384 ata_bio->flags |= ATA_SINGLE; 385 nblks = 1; 386 } 387 break; 388 } 389 /* Transfer is okay now. */ 390 } 391 if (ata_bio->flags & ATA_LBA48) { 392 sect = 0; 393 cyl = 0; 394 head = 0; 395 } else if (ata_bio->flags & ATA_LBA) { 396 sect = (ata_bio->blkno >> 0) & 0xff; 397 cyl = (ata_bio->blkno >> 8) & 0xffff; 398 head = (ata_bio->blkno >> 24) & 0x0f; 399 head |= WDSD_LBA; 400 } else { 401 int blkno = ata_bio->blkno; 402 sect = blkno % drvp->lp->d_nsectors; 403 sect++; /* Sectors begin with 1, not 0. */ 404 blkno /= drvp->lp->d_nsectors; 405 head = blkno % drvp->lp->d_ntracks; 406 blkno /= drvp->lp->d_ntracks; 407 cyl = blkno; 408 head |= WDSD_CHS; 409 } 410 #if NATA_DMA 411 if (xfer->c_flags & C_DMA) { 412 uint16_t count = nblks, features = 0; 413 414 ata_bio->nblks = nblks; 415 ata_bio->nbytes = xfer->c_bcount; 416 cmd = (ata_bio->flags & ATA_READ) ? 417 WDCC_READDMA : WDCC_WRITEDMA; 418 /* Init the DMA channel. */ 419 error = (*wdc->dma_init)(wdc->dma_arg, 420 chp->ch_channel, xfer->c_drive, 421 (char *)xfer->c_databuf + xfer->c_skip, 422 ata_bio->nbytes, dma_flags); 423 if (error) { 424 if (error == EINVAL) { 425 /* 426 * We can't do DMA on this transfer 427 * for some reason. Fall back to 428 * PIO. 429 */ 430 xfer->c_flags &= ~C_DMA; 431 error = 0; 432 goto do_pio; 433 } 434 ata_bio->error = ERR_DMA; 435 ata_bio->r_error = 0; 436 wdc_ata_bio_done(chp, xfer); 437 return; 438 } 439 /* Initiate command */ 440 if (wdc->select) 441 wdc->select(chp, xfer->c_drive); 442 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 443 0, WDSD_IBM | (xfer->c_drive << 4)); 444 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags)) { 445 case WDCWAIT_OK: 446 break; 447 case WDCWAIT_TOUT: 448 goto timeout; 449 case WDCWAIT_THR: 450 return; 451 } 452 if (ata_bio->flags & ATA_LBA48) { 453 uint8_t device = WDSD_LBA; 454 cmd = atacmd_to48(cmd); 455 456 atacmd_toncq(xfer, &cmd, &count, &features, 457 &device); 458 459 wdccommandext(chp, xfer->c_drive, cmd, 460 ata_bio->blkno, count, features, device); 461 } else { 462 wdccommand(chp, xfer->c_drive, cmd, cyl, 463 head, sect, count, features); 464 } 465 /* start the DMA channel */ 466 (*wdc->dma_start)(wdc->dma_arg, 467 chp->ch_channel, xfer->c_drive); 468 chp->ch_flags |= ATACH_DMA_WAIT; 469 /* start timeout machinery */ 470 if ((xfer->c_flags & C_POLL) == 0) 471 callout_reset(&xfer->c_timo_callout, 472 ATA_DELAY / 1000 * hz, wdctimeout, xfer); 473 /* wait for irq */ 474 goto intr; 475 } /* else not DMA */ 476 do_pio: 477 #endif /* NATA_DMA */ 478 #if NATA_PIOBM 479 if ((xfer->c_flags & C_PIOBM) && xfer->c_skip == 0) { 480 if (ata_bio->flags & ATA_POLL) { 481 /* XXX not supported yet --- fall back to PIO */ 482 xfer->c_flags &= ~C_PIOBM; 483 } else { 484 /* Init the DMA channel. */ 485 error = (*wdc->dma_init)(wdc->dma_arg, 486 chp->ch_channel, xfer->c_drive, 487 (char *)xfer->c_databuf + xfer->c_skip, 488 xfer->c_bcount, 489 dma_flags | WDC_DMA_PIOBM_ATA); 490 if (error) { 491 if (error == EINVAL) { 492 /* 493 * We can't do DMA on this 494 * transfer for some reason. 495 * Fall back to PIO. 496 */ 497 xfer->c_flags &= ~C_PIOBM; 498 error = 0; 499 } else { 500 ata_bio->error = ERR_DMA; 501 ata_bio->r_error = 0; 502 wdc_ata_bio_done(chp, xfer); 503 return; 504 } 505 } 506 } 507 } 508 #endif 509 ata_bio->nblks = min(nblks, drvp->multi); 510 ata_bio->nbytes = ata_bio->nblks * drvp->lp->d_secsize; 511 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 512 if (ata_bio->nblks > 1) { 513 cmd = (ata_bio->flags & ATA_READ) ? 514 WDCC_READMULTI : WDCC_WRITEMULTI; 515 } else { 516 cmd = (ata_bio->flags & ATA_READ) ? 517 WDCC_READ : WDCC_WRITE; 518 } 519 /* Initiate command! */ 520 if (wdc->select) 521 wdc->select(chp, xfer->c_drive); 522 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 523 WDSD_IBM | (xfer->c_drive << 4)); 524 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags)) { 525 case WDCWAIT_OK: 526 break; 527 case WDCWAIT_TOUT: 528 goto timeout; 529 case WDCWAIT_THR: 530 return; 531 } 532 if (ata_bio->flags & ATA_LBA48) { 533 wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd), 534 ata_bio->blkno, nblks, 0, WDSD_LBA); 535 } else { 536 wdccommand(chp, xfer->c_drive, cmd, cyl, 537 head, sect, nblks, 538 (drvp->lp->d_type == DKTYPE_ST506) ? 539 drvp->lp->d_precompcyl / 4 : 0); 540 } 541 /* start timeout machinery */ 542 if ((xfer->c_flags & C_POLL) == 0) 543 callout_reset(&xfer->c_timo_callout, 544 ATA_DELAY / 1000 * hz, wdctimeout, xfer); 545 } else if (ata_bio->nblks > 1) { 546 /* The number of blocks in the last stretch may be smaller. */ 547 nblks = xfer->c_bcount / drvp->lp->d_secsize; 548 if (ata_bio->nblks > nblks) { 549 ata_bio->nblks = nblks; 550 ata_bio->nbytes = xfer->c_bcount; 551 } 552 } 553 /* If this was a write and not using DMA, push the data. */ 554 if ((ata_bio->flags & ATA_READ) == 0) { 555 /* 556 * we have to busy-wait here, we can't rely on running in 557 * thread context. 558 */ 559 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL) != 0) { 560 printf("%s:%d:%d: timeout waiting for DRQ, " 561 "st=0x%02x, err=0x%02x\n", 562 device_xname(atac->atac_dev), chp->ch_channel, 563 xfer->c_drive, chp->ch_status, chp->ch_error); 564 if (wdc_ata_err(drvp, ata_bio) != WDC_ATA_ERR) 565 ata_bio->error = TIMEOUT; 566 wdc_ata_bio_done(chp, xfer); 567 return; 568 } 569 if (wdc_ata_err(drvp, ata_bio) == WDC_ATA_ERR) { 570 wdc_ata_bio_done(chp, xfer); 571 return; 572 } 573 #if NATA_PIOBM 574 if (xfer->c_flags & C_PIOBM) { 575 /* start the busmastering PIO */ 576 (*wdc->piobm_start)(wdc->dma_arg, 577 chp->ch_channel, xfer->c_drive, 578 xfer->c_skip, ata_bio->nbytes, 0); 579 chp->ch_flags |= ATACH_DMA_WAIT; 580 } else 581 #endif 582 583 wdc->dataout_pio(chp, drvp->drive_flags, 584 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 585 } 586 587 #if NATA_DMA 588 intr: 589 #endif 590 /* Wait for IRQ (either real or polled) */ 591 if ((ata_bio->flags & ATA_POLL) == 0) { 592 chp->ch_flags |= ATACH_IRQ_WAIT; 593 } else { 594 /* Wait for at last 400ns for status bit to be valid */ 595 delay(1); 596 #if NATA_DMA 597 if (chp->ch_flags & ATACH_DMA_WAIT) { 598 wdc_dmawait(chp, xfer, ATA_DELAY); 599 chp->ch_flags &= ~ATACH_DMA_WAIT; 600 } 601 #endif 602 wdc_ata_bio_intr(chp, xfer, 0); 603 if ((ata_bio->flags & ATA_ITSDONE) == 0) 604 goto again; 605 } 606 return; 607 timeout: 608 printf("%s:%d:%d: not ready, st=0x%02x, err=0x%02x\n", 609 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 610 chp->ch_status, chp->ch_error); 611 if (wdc_ata_err(drvp, ata_bio) != WDC_ATA_ERR) 612 ata_bio->error = TIMEOUT; 613 wdc_ata_bio_done(chp, xfer); 614 return; 615 } 616 617 static int 618 wdc_ata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 619 { 620 struct atac_softc *atac = chp->ch_atac; 621 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 622 struct ata_bio *ata_bio = &xfer->c_bio; 623 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 624 int drv_err; 625 626 ATADEBUG_PRINT(("wdc_ata_bio_intr %s:%d:%d\n", 627 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 628 DEBUG_INTR | DEBUG_XFERS); 629 630 631 /* Is it not a transfer, but a control operation? */ 632 if (drvp->state < READY) { 633 printf("%s:%d:%d: bad state %d in wdc_ata_bio_intr\n", 634 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 635 drvp->state); 636 panic("wdc_ata_bio_intr: bad state"); 637 } 638 639 /* 640 * if we missed an interrupt in a PIO transfer, reset and restart. 641 * Don't try to continue transfer, we may have missed cycles. 642 */ 643 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 644 ata_bio->error = TIMEOUT; 645 wdc_ata_bio_done(chp, xfer); 646 return 1; 647 } 648 649 #if NATA_PIOBM 650 /* Transfer-done interrupt for busmastering PIO read */ 651 if ((xfer->c_flags & C_PIOBM) && (chp->ch_flags & ATACH_PIOBM_WAIT)) { 652 chp->ch_flags &= ~ATACH_PIOBM_WAIT; 653 goto end; 654 } 655 #endif 656 657 /* Ack interrupt done by wdc_wait_for_unbusy */ 658 if (wdc_wait_for_unbusy(chp, (irq == 0) ? ATA_DELAY : 0, AT_POLL) < 0) { 659 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 660 return 0; /* IRQ was not for us */ 661 printf("%s:%d:%d: device timeout, c_bcount=%d, c_skip%d\n", 662 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 663 xfer->c_bcount, xfer->c_skip); 664 ata_bio->error = TIMEOUT; 665 wdc_ata_bio_done(chp, xfer); 666 return 1; 667 } 668 if (wdc->irqack) 669 wdc->irqack(chp); 670 671 drv_err = wdc_ata_err(drvp, ata_bio); 672 673 #if NATA_DMA 674 /* If we were using DMA, Turn off the DMA channel and check for error */ 675 if (xfer->c_flags & C_DMA) { 676 if (ata_bio->flags & ATA_POLL) { 677 /* 678 * IDE drives deassert WDCS_BSY before transfer is 679 * complete when using DMA. Polling for DRQ to deassert 680 * is not enough DRQ is not required to be 681 * asserted for DMA transfers, so poll for DRDY. 682 */ 683 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 684 ATA_DELAY, ATA_POLL) == WDCWAIT_TOUT) { 685 printf("%s:%d:%d: polled transfer timed out " 686 "(st=0x%x)\n", 687 device_xname(atac->atac_dev), 688 chp->ch_channel, xfer->c_drive, 689 chp->ch_status); 690 ata_bio->error = TIMEOUT; 691 drv_err = WDC_ATA_ERR; 692 } 693 } 694 if (wdc->dma_status != 0) { 695 if (drv_err != WDC_ATA_ERR) { 696 ata_bio->error = ERR_DMA; 697 drv_err = WDC_ATA_ERR; 698 } 699 } 700 if (chp->ch_status & WDCS_DRQ) { 701 if (drv_err != WDC_ATA_ERR) { 702 printf("%s:%d:%d: intr with DRQ (st=0x%x)\n", 703 device_xname(atac->atac_dev), 704 chp->ch_channel, 705 xfer->c_drive, chp->ch_status); 706 ata_bio->error = TIMEOUT; 707 drv_err = WDC_ATA_ERR; 708 } 709 } 710 if (drv_err != WDC_ATA_ERR) 711 goto end; 712 if (ata_bio->r_error & WDCE_CRC || ata_bio->error == ERR_DMA) 713 ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0); 714 } 715 #endif /* NATA_DMA */ 716 717 /* if we had an error, end */ 718 if (drv_err == WDC_ATA_ERR) { 719 wdc_ata_bio_done(chp, xfer); 720 return 1; 721 } 722 723 /* If this was a read and not using DMA, fetch the data. */ 724 if ((ata_bio->flags & ATA_READ) != 0) { 725 if ((chp->ch_status & WDCS_DRQ) != WDCS_DRQ) { 726 printf("%s:%d:%d: read intr before drq\n", 727 device_xname(atac->atac_dev), chp->ch_channel, 728 xfer->c_drive); 729 ata_bio->error = TIMEOUT; 730 wdc_ata_bio_done(chp, xfer); 731 return 1; 732 } 733 #if NATA_PIOBM 734 if (xfer->c_flags & C_PIOBM) { 735 /* start the busmastering PIO */ 736 (*wdc->piobm_start)(wdc->dma_arg, 737 chp->ch_channel, xfer->c_drive, 738 xfer->c_skip, ata_bio->nbytes, 739 WDC_PIOBM_XFER_IRQ); 740 chp->ch_flags |= ATACH_DMA_WAIT | ATACH_PIOBM_WAIT | ATACH_IRQ_WAIT; 741 return 1; 742 } else 743 #endif 744 wdc->datain_pio(chp, drvp->drive_flags, 745 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 746 } 747 748 #if NATA_DMA || NATA_PIOBM 749 end: 750 #endif 751 ata_bio->blkno += ata_bio->nblks; 752 ata_bio->blkdone += ata_bio->nblks; 753 xfer->c_skip += ata_bio->nbytes; 754 xfer->c_bcount -= ata_bio->nbytes; 755 /* See if this transfer is complete. */ 756 if (xfer->c_bcount > 0) { 757 if ((ata_bio->flags & ATA_POLL) == 0) { 758 /* Start the next operation */ 759 _wdc_ata_bio_start(chp, xfer); 760 } else { 761 /* Let _wdc_ata_bio_start do the loop */ 762 return 1; 763 } 764 } else { /* Done with this transfer */ 765 ata_bio->error = NOERROR; 766 wdc_ata_bio_done(chp, xfer); 767 } 768 return 1; 769 } 770 771 static void 772 wdc_ata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 773 int reason) 774 { 775 struct ata_bio *ata_bio = &xfer->c_bio; 776 int drive = xfer->c_drive; 777 778 ata_deactivate_xfer(chp, xfer); 779 780 ata_bio->flags |= ATA_ITSDONE; 781 switch (reason) { 782 case KILL_GONE: 783 ata_bio->error = ERR_NODEV; 784 break; 785 case KILL_RESET: 786 ata_bio->error = ERR_RESET; 787 break; 788 default: 789 printf("wdc_ata_bio_kill_xfer: unknown reason %d\n", 790 reason); 791 panic("wdc_ata_bio_kill_xfer"); 792 } 793 ata_bio->r_error = WDCE_ABRT; 794 ATADEBUG_PRINT(("wdc_ata_bio_kill_xfer: drv_done\n"), DEBUG_XFERS); 795 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 796 } 797 798 static void 799 wdc_ata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 800 { 801 struct ata_bio *ata_bio = &xfer->c_bio; 802 int drive = xfer->c_drive; 803 804 ATADEBUG_PRINT(("wdc_ata_bio_done %s:%d:%d: flags 0x%x\n", 805 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 806 xfer->c_drive, (u_int)xfer->c_flags), 807 DEBUG_XFERS); 808 809 callout_stop(&xfer->c_timo_callout); 810 811 /* feed back residual bcount to our caller */ 812 ata_bio->bcount = xfer->c_bcount; 813 814 /* mark controller inactive and free xfer */ 815 ata_deactivate_xfer(chp, xfer); 816 817 if (ata_waitdrain_check(chp, drive)) { 818 ata_bio->error = ERR_NODEV; 819 } 820 ata_bio->flags |= ATA_ITSDONE; 821 ATADEBUG_PRINT(("wdc_ata_done: drv_done\n"), DEBUG_XFERS); 822 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 823 ATADEBUG_PRINT(("atastart from wdc_ata_done, flags 0x%x\n", 824 chp->ch_flags), DEBUG_XFERS); 825 atastart(chp); 826 } 827 828 static int 829 wdc_ata_err(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 830 { 831 struct ata_channel *chp = drvp->chnl_softc; 832 ata_bio->error = 0; 833 if (chp->ch_status & WDCS_BSY) { 834 ata_bio->error = TIMEOUT; 835 return WDC_ATA_ERR; 836 } 837 838 if (chp->ch_status & WDCS_DWF) { 839 ata_bio->error = ERR_DF; 840 return WDC_ATA_ERR; 841 } 842 843 if (chp->ch_status & WDCS_ERR) { 844 ata_bio->error = ERROR; 845 ata_bio->r_error = chp->ch_error; 846 if (ata_bio->r_error & (WDCE_BBK | WDCE_UNC | WDCE_IDNF | 847 WDCE_ABRT | WDCE_TK0NF | WDCE_AMNF)) 848 return WDC_ATA_ERR; 849 return WDC_ATA_NOERR; 850 } 851 852 if (chp->ch_status & WDCS_CORR) 853 ata_bio->flags |= ATA_CORR; 854 return WDC_ATA_NOERR; 855 } 856 857 static int 858 wdc_ata_addref(struct ata_drive_datas *drvp) 859 { 860 struct ata_channel *chp = drvp->chnl_softc; 861 862 return (ata_addref(chp)); 863 } 864 865 static void 866 wdc_ata_delref(struct ata_drive_datas *drvp) 867 { 868 struct ata_channel *chp = drvp->chnl_softc; 869 870 ata_delref(chp); 871 } 872
Indexes created Sat Oct 25 10:09:55 GMT 2025