ata_wdc.c revision 1.105.6.8
1 /* $NetBSD: ata_wdc.c,v 1.105.6.8 2017/08/12 14:41:54 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: ata_wdc.c,v 1.105.6.8 2017/08/12 14:41:54 jdolecek Exp $"); 58 59 #include "opt_ata.h" 60 #include "opt_wdc.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/file.h> 66 #include <sys/stat.h> 67 #include <sys/buf.h> 68 #include <sys/bufq.h> 69 #include <sys/malloc.h> 70 #include <sys/device.h> 71 #include <sys/disklabel.h> 72 #include <sys/syslog.h> 73 #include <sys/proc.h> 74 75 #include <sys/intr.h> 76 #include <sys/bus.h> 77 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 78 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 79 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 80 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 81 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 82 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 83 84 #include <dev/ata/ataconf.h> 85 #include <dev/ata/atareg.h> 86 #include <dev/ata/atavar.h> 87 #include <dev/ic/wdcreg.h> 88 #include <dev/ic/wdcvar.h> 89 90 #define DEBUG_INTR 0x01 91 #define DEBUG_XFERS 0x02 92 #define DEBUG_STATUS 0x04 93 #define DEBUG_FUNCS 0x08 94 #define DEBUG_PROBE 0x10 95 #ifdef ATADEBUG 96 extern int wdcdebug_wd_mask; /* inited in wd.c */ 97 #define ATADEBUG_PRINT(args, level) \ 98 if (wdcdebug_wd_mask & (level)) \ 99 printf args 100 #else 101 #define ATADEBUG_PRINT(args, level) 102 #endif 103 104 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 105 106 static int wdc_ata_bio(struct ata_drive_datas*, struct ata_xfer *); 107 static void wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 108 static void _wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 109 static int wdc_ata_bio_intr(struct ata_channel *, struct ata_xfer *, 110 int); 111 static void wdc_ata_bio_kill_xfer(struct ata_channel *, 112 struct ata_xfer *, int); 113 static void wdc_ata_bio_done(struct ata_channel *, struct ata_xfer *); 114 static int wdc_ata_err(struct ata_drive_datas *, struct ata_bio *, int); 115 #define WDC_ATA_NOERR 0x00 /* Drive doesn't report an error */ 116 #define WDC_ATA_RECOV 0x01 /* There was a recovered error */ 117 #define WDC_ATA_ERR 0x02 /* Drive reports an error */ 118 static int wdc_ata_addref(struct ata_drive_datas *); 119 static void wdc_ata_delref(struct ata_drive_datas *); 120 121 const struct ata_bustype wdc_ata_bustype = { 122 SCSIPI_BUSTYPE_ATA, 123 wdc_ata_bio, 124 wdc_reset_drive, 125 wdc_reset_channel, 126 wdc_exec_command, 127 ata_get_params, 128 wdc_ata_addref, 129 wdc_ata_delref, 130 ata_kill_pending, 131 }; 132 133 /* 134 * Handle block I/O operation. Return ATACMD_COMPLETE, ATACMD_QUEUED, or 135 * ATACMD_TRY_AGAIN. Must be called at splbio(). 136 */ 137 static int 138 wdc_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 139 { 140 struct ata_channel *chp = drvp->chnl_softc; 141 struct atac_softc *atac = chp->ch_atac; 142 struct ata_bio *ata_bio = &xfer->c_bio; 143 144 if (atac->atac_cap & ATAC_CAP_NOIRQ) 145 ata_bio->flags |= ATA_POLL; 146 if (ata_bio->flags & ATA_POLL) 147 xfer->c_flags |= C_POLL; 148 #if NATA_DMA 149 if ((drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) && 150 (ata_bio->flags & ATA_SINGLE) == 0) 151 xfer->c_flags |= C_DMA; 152 #endif 153 #if NATA_DMA && NATA_PIOBM 154 else 155 #endif 156 #if NATA_PIOBM 157 if (atac->atac_cap & ATAC_CAP_PIOBM) 158 xfer->c_flags |= C_PIOBM; 159 #endif 160 xfer->c_drive = drvp->drive; 161 xfer->c_databuf = ata_bio->databuf; 162 xfer->c_bcount = ata_bio->bcount; 163 xfer->c_start = wdc_ata_bio_start; 164 xfer->c_intr = wdc_ata_bio_intr; 165 xfer->c_kill_xfer = wdc_ata_bio_kill_xfer; 166 ata_exec_xfer(chp, xfer); 167 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 168 } 169 170 static void 171 wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 172 { 173 struct atac_softc *atac = chp->ch_atac; 174 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 175 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 176 struct ata_bio *ata_bio = &xfer->c_bio; 177 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 178 int wait_flags, tfd; 179 const char *errstring; 180 #ifdef WDC_NO_IDS 181 wait_flags = AT_POLL; 182 #else 183 wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 184 #endif 185 186 ATADEBUG_PRINT(("wdc_ata_bio_start %s:%d:%d state %d drive_flags 0x%x " 187 "c_flags 0x%x ch_flags 0x%x\n", 188 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 189 drvp->state, drvp->drive_flags, xfer->c_flags, chp->ch_flags), 190 DEBUG_XFERS); 191 192 /* Do control operations specially. */ 193 if (__predict_false(drvp->state < READY)) { 194 /* 195 * Actually, we want to be careful not to mess with the control 196 * state if the device is currently busy, but we can assume 197 * that we never get to this point if that's the case. 198 */ 199 /* If it's not a polled command, we need the kernel thread */ 200 if ((xfer->c_flags & C_POLL) == 0 && 201 (chp->ch_flags & ATACH_TH_RUN) == 0) { 202 ata_thread_wake(chp); 203 return; 204 } 205 /* 206 * disable interrupts, all commands here should be quick 207 * enough to be able to poll, and we don't go here that often 208 */ 209 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 210 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 211 wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS); 212 if (wdc->select) 213 wdc->select(chp, xfer->c_drive); 214 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 215 WDSD_IBM | (xfer->c_drive << 4)); 216 DELAY(10); 217 errstring = "wait"; 218 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 219 &tfd)) 220 goto ctrltimeout; 221 wdccommandshort(chp, xfer->c_drive, WDCC_RECAL); 222 /* Wait for at last 400ns for status bit to be valid */ 223 DELAY(1); 224 errstring = "recal"; 225 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 226 &tfd)) 227 goto ctrltimeout; 228 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 229 goto ctrlerror; 230 /* Don't try to set modes if controller can't be adjusted */ 231 if (atac->atac_set_modes == NULL) 232 goto geometry; 233 /* Also don't try if the drive didn't report its mode */ 234 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 235 goto geometry; 236 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 237 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 238 errstring = "piomode"; 239 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 240 &tfd)) 241 goto ctrltimeout; 242 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 243 goto ctrlerror; 244 #if NATA_DMA 245 #if NATA_UDMA 246 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 247 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 248 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 249 } else 250 #endif 251 if (drvp->drive_flags & ATA_DRIVE_DMA) { 252 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 253 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 254 } else { 255 goto geometry; 256 } 257 errstring = "dmamode"; 258 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 259 &tfd)) 260 goto ctrltimeout; 261 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 262 goto ctrlerror; 263 #endif /* NATA_DMA */ 264 geometry: 265 if (ata_bio->flags & ATA_LBA) 266 goto multimode; 267 wdccommand(chp, xfer->c_drive, WDCC_IDP, 268 drvp->lp->d_ncylinders, 269 drvp->lp->d_ntracks - 1, 0, drvp->lp->d_nsectors, 270 (drvp->lp->d_type == DKTYPE_ST506) ? 271 drvp->lp->d_precompcyl / 4 : 0); 272 errstring = "geometry"; 273 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 274 &tfd)) 275 goto ctrltimeout; 276 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 277 goto ctrlerror; 278 multimode: 279 if (drvp->multi == 1) 280 goto ready; 281 wdccommand(chp, xfer->c_drive, WDCC_SETMULTI, 0, 0, 0, 282 drvp->multi, 0); 283 errstring = "setmulti"; 284 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 285 &tfd)) 286 goto ctrltimeout; 287 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 288 goto ctrlerror; 289 ready: 290 drvp->state = READY; 291 /* 292 * The drive is usable now 293 */ 294 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 295 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 296 wd_aux_ctlr, WDCTL_4BIT); 297 delay(10); /* some drives need a little delay here */ 298 } 299 300 _wdc_ata_bio_start(chp, xfer); 301 return; 302 ctrltimeout: 303 printf("%s:%d:%d: %s timed out\n", 304 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 305 errstring); 306 ata_bio->error = TIMEOUT; 307 goto ctrldone; 308 ctrlerror: 309 printf("%s:%d:%d: %s ", 310 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 311 errstring); 312 if (ATACH_ST(tfd) & WDCS_DWF) { 313 printf("drive fault\n"); 314 ata_bio->error = ERR_DF; 315 } else { 316 ata_bio->r_error = ATACH_ERR(tfd); 317 ata_bio->error = ERROR; 318 printf("error (%x)\n", ata_bio->r_error); 319 } 320 ctrldone: 321 drvp->state = 0; 322 wdc_ata_bio_done(chp, xfer); 323 324 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 325 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 326 WDCTL_4BIT); 327 return; 328 } 329 330 static void 331 _wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 332 { 333 struct atac_softc *atac = chp->ch_atac; 334 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 335 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 336 struct ata_bio *ata_bio = &xfer->c_bio; 337 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 338 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 339 uint16_t cyl; 340 uint8_t head, sect, cmd = 0; 341 int nblks; 342 #if NATA_DMA || NATA_PIOBM 343 int error, dma_flags = 0, tfd; 344 #endif 345 346 ATADEBUG_PRINT(("_wdc_ata_bio_start %s:%d:%d\n", 347 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 348 DEBUG_INTR | DEBUG_XFERS); 349 350 #if NATA_DMA || NATA_PIOBM 351 if (xfer->c_flags & (C_DMA | C_PIOBM)) { 352 #if NATA_DMA 353 if (drvp->n_xfers <= NXFER) 354 drvp->n_xfers++; 355 #endif 356 dma_flags = (ata_bio->flags & ATA_READ) ? WDC_DMA_READ : 0; 357 if (ata_bio->flags & ATA_LBA48) 358 dma_flags |= WDC_DMA_LBA48; 359 } 360 #endif 361 again: 362 /* 363 * 364 * When starting a multi-sector transfer, or doing single-sector 365 * transfers... 366 */ 367 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 368 if (ata_bio->flags & ATA_SINGLE) 369 nblks = 1; 370 else 371 nblks = xfer->c_bcount / drvp->lp->d_secsize; 372 /* Check for bad sectors and adjust transfer, if necessary. */ 373 if ((drvp->lp->d_flags & D_BADSECT) != 0) { 374 long blkdiff; 375 int i; 376 for (i = 0; (blkdiff = drvp->badsect[i]) != -1; 377 i++) { 378 blkdiff -= ata_bio->blkno; 379 if (blkdiff < 0) 380 continue; 381 if (blkdiff == 0) { 382 /* Replace current block of transfer. */ 383 ata_bio->blkno = 384 drvp->lp->d_secperunit - 385 drvp->lp->d_nsectors - i - 1; 386 } 387 if (blkdiff < nblks) { 388 /* Bad block inside transfer. */ 389 ata_bio->flags |= ATA_SINGLE; 390 nblks = 1; 391 } 392 break; 393 } 394 /* Transfer is okay now. */ 395 } 396 if (ata_bio->flags & ATA_LBA48) { 397 sect = 0; 398 cyl = 0; 399 head = 0; 400 } else if (ata_bio->flags & ATA_LBA) { 401 sect = (ata_bio->blkno >> 0) & 0xff; 402 cyl = (ata_bio->blkno >> 8) & 0xffff; 403 head = (ata_bio->blkno >> 24) & 0x0f; 404 head |= WDSD_LBA; 405 } else { 406 int blkno = ata_bio->blkno; 407 sect = blkno % drvp->lp->d_nsectors; 408 sect++; /* Sectors begin with 1, not 0. */ 409 blkno /= drvp->lp->d_nsectors; 410 head = blkno % drvp->lp->d_ntracks; 411 blkno /= drvp->lp->d_ntracks; 412 cyl = blkno; 413 head |= WDSD_CHS; 414 } 415 #if NATA_DMA 416 if (xfer->c_flags & C_DMA) { 417 uint16_t count = nblks, features = 0; 418 419 ata_bio->nblks = nblks; 420 ata_bio->nbytes = xfer->c_bcount; 421 cmd = (ata_bio->flags & ATA_READ) ? 422 WDCC_READDMA : WDCC_WRITEDMA; 423 /* Init the DMA channel. */ 424 error = (*wdc->dma_init)(wdc->dma_arg, 425 chp->ch_channel, xfer->c_drive, 426 (char *)xfer->c_databuf + xfer->c_skip, 427 ata_bio->nbytes, dma_flags); 428 if (error) { 429 if (error == EINVAL) { 430 /* 431 * We can't do DMA on this transfer 432 * for some reason. Fall back to 433 * PIO. 434 */ 435 xfer->c_flags &= ~C_DMA; 436 error = 0; 437 goto do_pio; 438 } 439 ata_bio->error = ERR_DMA; 440 ata_bio->r_error = 0; 441 wdc_ata_bio_done(chp, xfer); 442 return; 443 } 444 /* Initiate command */ 445 if (wdc->select) 446 wdc->select(chp, xfer->c_drive); 447 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 448 0, WDSD_IBM | (xfer->c_drive << 4)); 449 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, 450 &tfd)) { 451 case WDCWAIT_OK: 452 break; 453 case WDCWAIT_TOUT: 454 goto timeout; 455 case WDCWAIT_THR: 456 return; 457 } 458 if (ata_bio->flags & ATA_LBA48) { 459 uint8_t device = WDSD_LBA; 460 cmd = atacmd_to48(cmd); 461 462 atacmd_toncq(xfer, &cmd, &count, &features, 463 &device); 464 465 wdccommandext(chp, xfer->c_drive, cmd, 466 ata_bio->blkno, count, features, device); 467 } else { 468 wdccommand(chp, xfer->c_drive, cmd, cyl, 469 head, sect, count, features); 470 } 471 /* start the DMA channel */ 472 (*wdc->dma_start)(wdc->dma_arg, 473 chp->ch_channel, xfer->c_drive); 474 chp->ch_flags |= ATACH_DMA_WAIT; 475 /* start timeout machinery */ 476 if ((xfer->c_flags & C_POLL) == 0) 477 callout_reset(&xfer->c_timo_callout, 478 ATA_DELAY / 1000 * hz, wdctimeout, xfer); 479 /* wait for irq */ 480 goto intr; 481 } /* else not DMA */ 482 do_pio: 483 #endif /* NATA_DMA */ 484 #if NATA_PIOBM 485 if ((xfer->c_flags & C_PIOBM) && xfer->c_skip == 0) { 486 if (ata_bio->flags & ATA_POLL) { 487 /* XXX not supported yet --- fall back to PIO */ 488 xfer->c_flags &= ~C_PIOBM; 489 } else { 490 /* Init the DMA channel. */ 491 error = (*wdc->dma_init)(wdc->dma_arg, 492 chp->ch_channel, xfer->c_drive, 493 (char *)xfer->c_databuf + xfer->c_skip, 494 xfer->c_bcount, 495 dma_flags | WDC_DMA_PIOBM_ATA); 496 if (error) { 497 if (error == EINVAL) { 498 /* 499 * We can't do DMA on this 500 * transfer for some reason. 501 * Fall back to PIO. 502 */ 503 xfer->c_flags &= ~C_PIOBM; 504 error = 0; 505 } else { 506 ata_bio->error = ERR_DMA; 507 ata_bio->r_error = 0; 508 wdc_ata_bio_done(chp, xfer); 509 return; 510 } 511 } 512 } 513 } 514 #endif 515 ata_bio->nblks = min(nblks, drvp->multi); 516 ata_bio->nbytes = ata_bio->nblks * drvp->lp->d_secsize; 517 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 518 if (ata_bio->nblks > 1) { 519 cmd = (ata_bio->flags & ATA_READ) ? 520 WDCC_READMULTI : WDCC_WRITEMULTI; 521 } else { 522 cmd = (ata_bio->flags & ATA_READ) ? 523 WDCC_READ : WDCC_WRITE; 524 } 525 /* Initiate command! */ 526 if (wdc->select) 527 wdc->select(chp, xfer->c_drive); 528 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 529 WDSD_IBM | (xfer->c_drive << 4)); 530 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, &tfd)) { 531 case WDCWAIT_OK: 532 break; 533 case WDCWAIT_TOUT: 534 goto timeout; 535 case WDCWAIT_THR: 536 return; 537 } 538 if (ata_bio->flags & ATA_LBA48) { 539 wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd), 540 ata_bio->blkno, nblks, 0, WDSD_LBA); 541 } else { 542 wdccommand(chp, xfer->c_drive, cmd, cyl, 543 head, sect, nblks, 544 (drvp->lp->d_type == DKTYPE_ST506) ? 545 drvp->lp->d_precompcyl / 4 : 0); 546 } 547 /* start timeout machinery */ 548 if ((xfer->c_flags & C_POLL) == 0) 549 callout_reset(&xfer->c_timo_callout, 550 ATA_DELAY / 1000 * hz, wdctimeout, xfer); 551 } else if (ata_bio->nblks > 1) { 552 /* The number of blocks in the last stretch may be smaller. */ 553 nblks = xfer->c_bcount / drvp->lp->d_secsize; 554 if (ata_bio->nblks > nblks) { 555 ata_bio->nblks = nblks; 556 ata_bio->nbytes = xfer->c_bcount; 557 } 558 } 559 /* If this was a write and not using DMA, push the data. */ 560 if ((ata_bio->flags & ATA_READ) == 0) { 561 /* 562 * we have to busy-wait here, we can't rely on running in 563 * thread context. 564 */ 565 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL, &tfd) != 0) { 566 printf("%s:%d:%d: timeout waiting for DRQ, " 567 "st=0x%02x, err=0x%02x\n", 568 device_xname(atac->atac_dev), chp->ch_channel, 569 xfer->c_drive, 570 ATACH_ST(tfd), ATACH_ERR(tfd)); 571 if (wdc_ata_err(drvp, ata_bio, tfd) != WDC_ATA_ERR) 572 ata_bio->error = TIMEOUT; 573 wdc_ata_bio_done(chp, xfer); 574 return; 575 } 576 if (wdc_ata_err(drvp, ata_bio, tfd) == WDC_ATA_ERR) { 577 wdc_ata_bio_done(chp, xfer); 578 return; 579 } 580 #if NATA_PIOBM 581 if (xfer->c_flags & C_PIOBM) { 582 /* start the busmastering PIO */ 583 (*wdc->piobm_start)(wdc->dma_arg, 584 chp->ch_channel, xfer->c_drive, 585 xfer->c_skip, ata_bio->nbytes, 0); 586 chp->ch_flags |= ATACH_DMA_WAIT; 587 } else 588 #endif 589 590 wdc->dataout_pio(chp, drvp->drive_flags, 591 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 592 } 593 594 #if NATA_DMA 595 intr: 596 #endif 597 /* Wait for IRQ (either real or polled) */ 598 if ((ata_bio->flags & ATA_POLL) != 0) { 599 /* Wait for at last 400ns for status bit to be valid */ 600 delay(1); 601 #if NATA_DMA 602 if (chp->ch_flags & ATACH_DMA_WAIT) { 603 wdc_dmawait(chp, xfer, ATA_DELAY); 604 chp->ch_flags &= ~ATACH_DMA_WAIT; 605 } 606 #endif 607 wdc_ata_bio_intr(chp, xfer, 0); 608 if ((ata_bio->flags & ATA_ITSDONE) == 0) 609 goto again; 610 } 611 return; 612 timeout: 613 printf("%s:%d:%d: not ready, st=0x%02x, err=0x%02x\n", 614 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 615 ATACH_ST(tfd), ATACH_ERR(tfd)); 616 if (wdc_ata_err(drvp, ata_bio, tfd) != WDC_ATA_ERR) 617 ata_bio->error = TIMEOUT; 618 wdc_ata_bio_done(chp, xfer); 619 return; 620 } 621 622 static int 623 wdc_ata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int is) 624 { 625 struct atac_softc *atac = chp->ch_atac; 626 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 627 struct ata_bio *ata_bio = &xfer->c_bio; 628 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 629 int drv_err, tfd; 630 bool poll = ((xfer->c_flags & C_POLL) != 0); 631 632 ATADEBUG_PRINT(("wdc_ata_bio_intr %s:%d:%d\n", 633 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 634 DEBUG_INTR | DEBUG_XFERS); 635 636 637 /* Is it not a transfer, but a control operation? */ 638 if (drvp->state < READY) { 639 printf("%s:%d:%d: bad state %d in wdc_ata_bio_intr\n", 640 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 641 drvp->state); 642 panic("wdc_ata_bio_intr: bad state"); 643 } 644 645 /* 646 * if we missed an interrupt in a PIO transfer, reset and restart. 647 * Don't try to continue transfer, we may have missed cycles. 648 */ 649 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 650 ata_bio->error = TIMEOUT; 651 wdc_ata_bio_done(chp, xfer); 652 return 1; 653 } 654 655 #if NATA_PIOBM 656 /* Transfer-done interrupt for busmastering PIO read */ 657 if ((xfer->c_flags & C_PIOBM) && (chp->ch_flags & ATACH_PIOBM_WAIT)) { 658 chp->ch_flags &= ~ATACH_PIOBM_WAIT; 659 goto end; 660 } 661 #endif 662 663 /* Ack interrupt done by wdc_wait_for_unbusy */ 664 if (wdc_wait_for_unbusy(chp, poll ? ATA_DELAY : 0, AT_POLL, &tfd) < 0) { 665 if (!poll && (xfer->c_flags & C_TIMEOU) == 0) 666 return 0; /* IRQ was not for us */ 667 printf("%s:%d:%d: device timeout, c_bcount=%d, c_skip%d\n", 668 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 669 xfer->c_bcount, xfer->c_skip); 670 ata_bio->error = TIMEOUT; 671 wdc_ata_bio_done(chp, xfer); 672 return 1; 673 } 674 if (wdc->irqack) 675 wdc->irqack(chp); 676 677 drv_err = wdc_ata_err(drvp, ata_bio, tfd); 678 679 #if NATA_DMA 680 /* If we were using DMA, Turn off the DMA channel and check for error */ 681 if (xfer->c_flags & C_DMA) { 682 if (ata_bio->flags & ATA_POLL) { 683 /* 684 * IDE drives deassert WDCS_BSY before transfer is 685 * complete when using DMA. Polling for DRQ to deassert 686 * is not enough DRQ is not required to be 687 * asserted for DMA transfers, so poll for DRDY. 688 */ 689 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 690 ATA_DELAY, ATA_POLL, &tfd) == WDCWAIT_TOUT) { 691 printf("%s:%d:%d: polled transfer timed out " 692 "(st=0x%x)\n", 693 device_xname(atac->atac_dev), 694 chp->ch_channel, xfer->c_drive, 695 ATACH_ST(tfd)); 696 ata_bio->error = TIMEOUT; 697 drv_err = WDC_ATA_ERR; 698 } 699 } 700 if (wdc->dma_status != 0) { 701 if (drv_err != WDC_ATA_ERR) { 702 ata_bio->error = ERR_DMA; 703 drv_err = WDC_ATA_ERR; 704 } 705 } 706 if (ATACH_ST(tfd) & WDCS_DRQ) { 707 if (drv_err != WDC_ATA_ERR) { 708 printf("%s:%d:%d: intr with DRQ (st=0x%x)\n", 709 device_xname(atac->atac_dev), 710 chp->ch_channel, 711 xfer->c_drive, ATACH_ST(tfd)); 712 ata_bio->error = TIMEOUT; 713 drv_err = WDC_ATA_ERR; 714 } 715 } 716 if (drv_err != WDC_ATA_ERR) 717 goto end; 718 if (ata_bio->r_error & WDCE_CRC || ata_bio->error == ERR_DMA) 719 ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0); 720 } 721 #endif /* NATA_DMA */ 722 723 /* if we had an error, end */ 724 if (drv_err == WDC_ATA_ERR) { 725 wdc_ata_bio_done(chp, xfer); 726 return 1; 727 } 728 729 /* If this was a read and not using DMA, fetch the data. */ 730 if ((ata_bio->flags & ATA_READ) != 0) { 731 if ((ATACH_ST(tfd) & WDCS_DRQ) != WDCS_DRQ) { 732 printf("%s:%d:%d: read intr before drq\n", 733 device_xname(atac->atac_dev), chp->ch_channel, 734 xfer->c_drive); 735 ata_bio->error = TIMEOUT; 736 wdc_ata_bio_done(chp, xfer); 737 return 1; 738 } 739 #if NATA_PIOBM 740 if (xfer->c_flags & C_PIOBM) { 741 /* start the busmastering PIO */ 742 (*wdc->piobm_start)(wdc->dma_arg, 743 chp->ch_channel, xfer->c_drive, 744 xfer->c_skip, ata_bio->nbytes, 745 WDC_PIOBM_XFER_IRQ); 746 chp->ch_flags |= ATACH_DMA_WAIT | ATACH_PIOBM_WAIT; 747 return 1; 748 } else 749 #endif 750 wdc->datain_pio(chp, drvp->drive_flags, 751 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 752 } 753 754 #if NATA_DMA || NATA_PIOBM 755 end: 756 #endif 757 ata_bio->blkno += ata_bio->nblks; 758 ata_bio->blkdone += ata_bio->nblks; 759 xfer->c_skip += ata_bio->nbytes; 760 xfer->c_bcount -= ata_bio->nbytes; 761 /* See if this transfer is complete. */ 762 if (xfer->c_bcount > 0) { 763 if ((ata_bio->flags & ATA_POLL) == 0) { 764 /* Start the next operation */ 765 _wdc_ata_bio_start(chp, xfer); 766 } else { 767 /* Let _wdc_ata_bio_start do the loop */ 768 return 1; 769 } 770 } else { /* Done with this transfer */ 771 ata_bio->error = NOERROR; 772 wdc_ata_bio_done(chp, xfer); 773 } 774 return 1; 775 } 776 777 static void 778 wdc_ata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 779 int reason) 780 { 781 struct ata_bio *ata_bio = &xfer->c_bio; 782 int drive = xfer->c_drive; 783 bool deactivate = true; 784 785 ata_bio->flags |= ATA_ITSDONE; 786 switch (reason) { 787 case KILL_GONE_INACTIVE: 788 deactivate = false; 789 /* FALLTHROUGH */ 790 case KILL_GONE: 791 ata_bio->error = ERR_NODEV; 792 break; 793 case KILL_RESET: 794 ata_bio->error = ERR_RESET; 795 break; 796 default: 797 printf("wdc_ata_bio_kill_xfer: unknown reason %d\n", 798 reason); 799 panic("wdc_ata_bio_kill_xfer"); 800 } 801 ata_bio->r_error = WDCE_ABRT; 802 803 if (deactivate) 804 ata_deactivate_xfer(chp, xfer); 805 806 ATADEBUG_PRINT(("wdc_ata_bio_kill_xfer: drv_done\n"), DEBUG_XFERS); 807 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 808 } 809 810 static void 811 wdc_ata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 812 { 813 struct ata_bio *ata_bio = &xfer->c_bio; 814 int drive = xfer->c_drive; 815 816 ATADEBUG_PRINT(("wdc_ata_bio_done %s:%d:%d: flags 0x%x\n", 817 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 818 xfer->c_drive, (u_int)xfer->c_flags), 819 DEBUG_XFERS); 820 821 if (ata_waitdrain_xfer_check(chp, xfer)) 822 return; 823 824 /* feed back residual bcount to our caller */ 825 ata_bio->bcount = xfer->c_bcount; 826 827 /* mark controller inactive and free xfer */ 828 ata_deactivate_xfer(chp, xfer); 829 830 ata_bio->flags |= ATA_ITSDONE; 831 ATADEBUG_PRINT(("wdc_ata_done: drv_done\n"), DEBUG_XFERS); 832 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 833 ATADEBUG_PRINT(("atastart from wdc_ata_done, flags 0x%x\n", 834 chp->ch_flags), DEBUG_XFERS); 835 atastart(chp); 836 } 837 838 static int 839 wdc_ata_err(struct ata_drive_datas *drvp, struct ata_bio *ata_bio, int tfd) 840 { 841 ata_bio->error = 0; 842 if (ATACH_ST(tfd) & WDCS_BSY) { 843 ata_bio->error = TIMEOUT; 844 return WDC_ATA_ERR; 845 } 846 847 if (ATACH_ST(tfd) & WDCS_DWF) { 848 ata_bio->error = ERR_DF; 849 return WDC_ATA_ERR; 850 } 851 852 if (ATACH_ST(tfd) & WDCS_ERR) { 853 ata_bio->error = ERROR; 854 ata_bio->r_error = ATACH_ERR(tfd); 855 if (ata_bio->r_error & (WDCE_BBK | WDCE_UNC | WDCE_IDNF | 856 WDCE_ABRT | WDCE_TK0NF | WDCE_AMNF)) 857 return WDC_ATA_ERR; 858 return WDC_ATA_NOERR; 859 } 860 861 if (ATACH_ST(tfd) & WDCS_CORR) 862 ata_bio->flags |= ATA_CORR; 863 return WDC_ATA_NOERR; 864 } 865 866 static int 867 wdc_ata_addref(struct ata_drive_datas *drvp) 868 { 869 struct ata_channel *chp = drvp->chnl_softc; 870 871 return (ata_addref(chp)); 872 } 873 874 static void 875 wdc_ata_delref(struct ata_drive_datas *drvp) 876 { 877 struct ata_channel *chp = drvp->chnl_softc; 878 879 ata_delref(chp); 880 } 881
Indexes created Sat Oct 25 10:09:55 GMT 2025