ata_wdc.c revision 1.107
1 /* $NetBSD: ata_wdc.c,v 1.107 2017/10/08 13:35:03 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: ata_wdc.c,v 1.107 2017/10/08 13:35:03 christos Exp $"); 58 59 #include "opt_ata.h" 60 #include "opt_wdc.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/file.h> 66 #include <sys/stat.h> 67 #include <sys/buf.h> 68 #include <sys/bufq.h> 69 #include <sys/malloc.h> 70 #include <sys/device.h> 71 #include <sys/disklabel.h> 72 #include <sys/syslog.h> 73 #include <sys/proc.h> 74 75 #include <sys/intr.h> 76 #include <sys/bus.h> 77 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 78 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 79 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 80 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 81 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 82 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 83 84 #include <dev/ata/ataconf.h> 85 #include <dev/ata/atareg.h> 86 #include <dev/ata/atavar.h> 87 #include <dev/ic/wdcreg.h> 88 #include <dev/ic/wdcvar.h> 89 90 #define DEBUG_INTR 0x01 91 #define DEBUG_XFERS 0x02 92 #define DEBUG_STATUS 0x04 93 #define DEBUG_FUNCS 0x08 94 #define DEBUG_PROBE 0x10 95 #ifdef ATADEBUG 96 extern int wdcdebug_wd_mask; /* inited in wd.c */ 97 #define ATADEBUG_PRINT(args, level) \ 98 if (wdcdebug_wd_mask & (level)) \ 99 printf args 100 #else 101 #define ATADEBUG_PRINT(args, level) 102 #endif 103 104 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 105 106 static int wdc_ata_bio(struct ata_drive_datas*, struct ata_xfer *); 107 static int wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 108 static int _wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 109 static void wdc_ata_bio_poll(struct ata_channel *,struct ata_xfer *); 110 static int wdc_ata_bio_intr(struct ata_channel *, struct ata_xfer *, 111 int); 112 static void wdc_ata_bio_kill_xfer(struct ata_channel *, 113 struct ata_xfer *, int); 114 static void wdc_ata_bio_done(struct ata_channel *, struct ata_xfer *); 115 static int wdc_ata_err(struct ata_drive_datas *, struct ata_bio *, int); 116 #define WDC_ATA_NOERR 0x00 /* Drive doesn't report an error */ 117 #define WDC_ATA_RECOV 0x01 /* There was a recovered error */ 118 #define WDC_ATA_ERR 0x02 /* Drive reports an error */ 119 static int wdc_ata_addref(struct ata_drive_datas *); 120 static void wdc_ata_delref(struct ata_drive_datas *); 121 122 const struct ata_bustype wdc_ata_bustype = { 123 SCSIPI_BUSTYPE_ATA, 124 wdc_ata_bio, 125 wdc_reset_drive, 126 wdc_reset_channel, 127 wdc_exec_command, 128 ata_get_params, 129 wdc_ata_addref, 130 wdc_ata_delref, 131 ata_kill_pending, 132 }; 133 134 /* 135 * Handle block I/O operation. Return ATACMD_COMPLETE, ATACMD_QUEUED, or 136 * ATACMD_TRY_AGAIN. Must be called at splbio(). 137 */ 138 static int 139 wdc_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 140 { 141 struct ata_channel *chp = drvp->chnl_softc; 142 struct atac_softc *atac = chp->ch_atac; 143 struct ata_bio *ata_bio = &xfer->c_bio; 144 145 if (atac->atac_cap & ATAC_CAP_NOIRQ) 146 ata_bio->flags |= ATA_POLL; 147 if (ata_bio->flags & ATA_POLL) 148 xfer->c_flags |= C_POLL; 149 #if NATA_DMA 150 if ((drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) && 151 (ata_bio->flags & ATA_SINGLE) == 0) 152 xfer->c_flags |= C_DMA; 153 #endif 154 #if NATA_DMA && NATA_PIOBM 155 else 156 #endif 157 #if NATA_PIOBM 158 if (atac->atac_cap & ATAC_CAP_PIOBM) 159 xfer->c_flags |= C_PIOBM; 160 #endif 161 xfer->c_drive = drvp->drive; 162 xfer->c_databuf = ata_bio->databuf; 163 xfer->c_bcount = ata_bio->bcount; 164 xfer->c_start = wdc_ata_bio_start; 165 xfer->c_poll = wdc_ata_bio_poll; 166 xfer->c_abort = wdc_ata_bio_done; 167 xfer->c_intr = wdc_ata_bio_intr; 168 xfer->c_kill_xfer = wdc_ata_bio_kill_xfer; 169 ata_exec_xfer(chp, xfer); 170 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 171 } 172 173 static int 174 wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 175 { 176 struct atac_softc *atac = chp->ch_atac; 177 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 178 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 179 struct ata_bio *ata_bio = &xfer->c_bio; 180 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 181 int wait_flags, tfd; 182 const char *errstring; 183 #ifdef WDC_NO_IDS 184 wait_flags = AT_POLL; 185 #else 186 wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 187 #endif 188 189 ATADEBUG_PRINT(("wdc_ata_bio_start %s:%d:%d state %d drive_flags 0x%x " 190 "c_flags 0x%x ch_flags 0x%x\n", 191 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 192 drvp->state, drvp->drive_flags, xfer->c_flags, chp->ch_flags), 193 DEBUG_XFERS); 194 195 ata_channel_lock_owned(chp); 196 197 /* Do control operations specially. */ 198 if (__predict_false(drvp->state < READY)) { 199 /* 200 * Actually, we want to be careful not to mess with the control 201 * state if the device is currently busy, but we can assume 202 * that we never get to this point if that's the case. 203 */ 204 /* If it's not a polled command, we need the kernel thread */ 205 if ((xfer->c_flags & C_POLL) == 0 && 206 (chp->ch_flags & ATACH_TH_RUN) == 0) { 207 return ATASTART_TH; 208 } 209 /* 210 * disable interrupts, all commands here should be quick 211 * enough to be able to poll, and we don't go here that often 212 */ 213 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 214 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 215 wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS); 216 if (wdc->select) 217 wdc->select(chp, xfer->c_drive); 218 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 219 WDSD_IBM | (xfer->c_drive << 4)); 220 DELAY(10); 221 errstring = "wait"; 222 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 223 &tfd)) 224 goto ctrltimeout; 225 wdccommandshort(chp, xfer->c_drive, WDCC_RECAL); 226 /* Wait for at last 400ns for status bit to be valid */ 227 DELAY(1); 228 errstring = "recal"; 229 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 230 &tfd)) 231 goto ctrltimeout; 232 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 233 goto ctrlerror; 234 /* Don't try to set modes if controller can't be adjusted */ 235 if (atac->atac_set_modes == NULL) 236 goto geometry; 237 /* Also don't try if the drive didn't report its mode */ 238 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 239 goto geometry; 240 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 241 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 242 errstring = "piomode"; 243 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 244 &tfd)) 245 goto ctrltimeout; 246 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 247 goto ctrlerror; 248 #if NATA_DMA 249 #if NATA_UDMA 250 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 251 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 252 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 253 } else 254 #endif 255 if (drvp->drive_flags & ATA_DRIVE_DMA) { 256 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 257 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 258 } else { 259 goto geometry; 260 } 261 errstring = "dmamode"; 262 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 263 &tfd)) 264 goto ctrltimeout; 265 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 266 goto ctrlerror; 267 #endif /* NATA_DMA */ 268 geometry: 269 if (ata_bio->flags & ATA_LBA) 270 goto multimode; 271 wdccommand(chp, xfer->c_drive, WDCC_IDP, 272 drvp->lp->d_ncylinders, 273 drvp->lp->d_ntracks - 1, 0, drvp->lp->d_nsectors, 274 (drvp->lp->d_type == DKTYPE_ST506) ? 275 drvp->lp->d_precompcyl / 4 : 0); 276 errstring = "geometry"; 277 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 278 &tfd)) 279 goto ctrltimeout; 280 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 281 goto ctrlerror; 282 multimode: 283 if (drvp->multi == 1) 284 goto ready; 285 wdccommand(chp, xfer->c_drive, WDCC_SETMULTI, 0, 0, 0, 286 drvp->multi, 0); 287 errstring = "setmulti"; 288 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 289 &tfd)) 290 goto ctrltimeout; 291 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 292 goto ctrlerror; 293 ready: 294 drvp->state = READY; 295 /* 296 * The drive is usable now 297 */ 298 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 299 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 300 wd_aux_ctlr, WDCTL_4BIT); 301 delay(10); /* some drives need a little delay here */ 302 } 303 304 return _wdc_ata_bio_start(chp, xfer); 305 ctrltimeout: 306 printf("%s:%d:%d: %s timed out\n", 307 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 308 errstring); 309 ata_bio->error = TIMEOUT; 310 goto ctrldone; 311 ctrlerror: 312 printf("%s:%d:%d: %s ", 313 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 314 errstring); 315 if (ATACH_ST(tfd) & WDCS_DWF) { 316 printf("drive fault\n"); 317 ata_bio->error = ERR_DF; 318 } else { 319 ata_bio->r_error = ATACH_ERR(tfd); 320 ata_bio->error = ERROR; 321 printf("error (%x)\n", ata_bio->r_error); 322 } 323 ctrldone: 324 drvp->state = 0; 325 326 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 327 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 328 WDCTL_4BIT); 329 return ATASTART_ABORT; 330 } 331 332 static int 333 _wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 334 { 335 struct atac_softc *atac = chp->ch_atac; 336 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 337 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 338 struct ata_bio *ata_bio = &xfer->c_bio; 339 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 340 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 341 uint16_t cyl; 342 uint8_t head, sect, cmd = 0; 343 int nblks, tfd; 344 #if NATA_DMA || NATA_PIOBM 345 int error, dma_flags = 0; 346 #endif 347 348 ATADEBUG_PRINT(("_wdc_ata_bio_start %s:%d:%d\n", 349 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 350 DEBUG_INTR | DEBUG_XFERS); 351 352 #if NATA_DMA || NATA_PIOBM 353 if (xfer->c_flags & (C_DMA | C_PIOBM)) { 354 #if NATA_DMA 355 if (drvp->n_xfers <= NXFER) 356 drvp->n_xfers++; 357 #endif 358 dma_flags = (ata_bio->flags & ATA_READ) ? WDC_DMA_READ : 0; 359 if (ata_bio->flags & ATA_LBA48) 360 dma_flags |= WDC_DMA_LBA48; 361 } 362 #endif 363 /* 364 * 365 * When starting a multi-sector transfer, or doing single-sector 366 * transfers... 367 */ 368 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 369 if (ata_bio->flags & ATA_SINGLE) 370 nblks = 1; 371 else 372 nblks = xfer->c_bcount / drvp->lp->d_secsize; 373 /* Check for bad sectors and adjust transfer, if necessary. */ 374 if ((drvp->lp->d_flags & D_BADSECT) != 0) { 375 long blkdiff; 376 int i; 377 for (i = 0; (blkdiff = drvp->badsect[i]) != -1; 378 i++) { 379 blkdiff -= ata_bio->blkno; 380 if (blkdiff < 0) 381 continue; 382 if (blkdiff == 0) { 383 /* Replace current block of transfer. */ 384 ata_bio->blkno = 385 drvp->lp->d_secperunit - 386 drvp->lp->d_nsectors - i - 1; 387 } 388 if (blkdiff < nblks) { 389 /* Bad block inside transfer. */ 390 ata_bio->flags |= ATA_SINGLE; 391 nblks = 1; 392 } 393 break; 394 } 395 /* Transfer is okay now. */ 396 } 397 if (ata_bio->flags & ATA_LBA48) { 398 sect = 0; 399 cyl = 0; 400 head = 0; 401 } else if (ata_bio->flags & ATA_LBA) { 402 sect = (ata_bio->blkno >> 0) & 0xff; 403 cyl = (ata_bio->blkno >> 8) & 0xffff; 404 head = (ata_bio->blkno >> 24) & 0x0f; 405 head |= WDSD_LBA; 406 } else { 407 int blkno = ata_bio->blkno; 408 sect = blkno % drvp->lp->d_nsectors; 409 sect++; /* Sectors begin with 1, not 0. */ 410 blkno /= drvp->lp->d_nsectors; 411 head = blkno % drvp->lp->d_ntracks; 412 blkno /= drvp->lp->d_ntracks; 413 cyl = blkno; 414 head |= WDSD_CHS; 415 } 416 #if NATA_DMA 417 if (xfer->c_flags & C_DMA) { 418 uint16_t count = nblks, features = 0; 419 420 ata_bio->nblks = nblks; 421 ata_bio->nbytes = xfer->c_bcount; 422 cmd = (ata_bio->flags & ATA_READ) ? 423 WDCC_READDMA : WDCC_WRITEDMA; 424 /* Init the DMA channel. */ 425 error = (*wdc->dma_init)(wdc->dma_arg, 426 chp->ch_channel, xfer->c_drive, 427 (char *)xfer->c_databuf + xfer->c_skip, 428 ata_bio->nbytes, dma_flags); 429 if (error) { 430 if (error == EINVAL) { 431 /* 432 * We can't do DMA on this transfer 433 * for some reason. Fall back to 434 * PIO. 435 */ 436 xfer->c_flags &= ~C_DMA; 437 error = 0; 438 goto do_pio; 439 } 440 ata_bio->error = ERR_DMA; 441 ata_bio->r_error = 0; 442 return ATASTART_ABORT; 443 } 444 /* Initiate command */ 445 if (wdc->select) 446 wdc->select(chp, xfer->c_drive); 447 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 448 0, WDSD_IBM | (xfer->c_drive << 4)); 449 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, 450 &tfd)) { 451 case WDCWAIT_OK: 452 break; 453 case WDCWAIT_TOUT: 454 goto timeout; 455 case WDCWAIT_THR: 456 return ATASTART_TH; 457 } 458 if (ata_bio->flags & ATA_LBA48) { 459 uint8_t device = WDSD_LBA; 460 cmd = atacmd_to48(cmd); 461 462 atacmd_toncq(xfer, &cmd, &count, &features, 463 &device); 464 465 wdccommandext(chp, xfer->c_drive, cmd, 466 ata_bio->blkno, count, features, device); 467 } else { 468 wdccommand(chp, xfer->c_drive, cmd, cyl, 469 head, sect, count, features); 470 } 471 /* start the DMA channel */ 472 (*wdc->dma_start)(wdc->dma_arg, 473 chp->ch_channel, xfer->c_drive); 474 chp->ch_flags |= ATACH_DMA_WAIT; 475 /* start timeout machinery */ 476 if ((xfer->c_flags & C_POLL) == 0) 477 callout_reset(&xfer->c_timo_callout, 478 ATA_DELAY / 1000 * hz, wdctimeout, xfer); 479 /* wait for irq */ 480 goto intr; 481 } /* else not DMA */ 482 do_pio: 483 #endif /* NATA_DMA */ 484 #if NATA_PIOBM 485 if ((xfer->c_flags & C_PIOBM) && xfer->c_skip == 0) { 486 if (ata_bio->flags & ATA_POLL) { 487 /* XXX not supported yet --- fall back to PIO */ 488 xfer->c_flags &= ~C_PIOBM; 489 } else { 490 /* Init the DMA channel. */ 491 error = (*wdc->dma_init)(wdc->dma_arg, 492 chp->ch_channel, xfer->c_drive, 493 (char *)xfer->c_databuf + xfer->c_skip, 494 xfer->c_bcount, 495 dma_flags | WDC_DMA_PIOBM_ATA); 496 if (error) { 497 if (error == EINVAL) { 498 /* 499 * We can't do DMA on this 500 * transfer for some reason. 501 * Fall back to PIO. 502 */ 503 xfer->c_flags &= ~C_PIOBM; 504 error = 0; 505 } else { 506 ata_bio->error = ERR_DMA; 507 ata_bio->r_error = 0; 508 return ATASTART_ABORT; 509 } 510 } 511 } 512 } 513 #endif 514 ata_bio->nblks = min(nblks, drvp->multi); 515 ata_bio->nbytes = ata_bio->nblks * drvp->lp->d_secsize; 516 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 517 if (ata_bio->nblks > 1) { 518 cmd = (ata_bio->flags & ATA_READ) ? 519 WDCC_READMULTI : WDCC_WRITEMULTI; 520 } else { 521 cmd = (ata_bio->flags & ATA_READ) ? 522 WDCC_READ : WDCC_WRITE; 523 } 524 /* Initiate command! */ 525 if (wdc->select) 526 wdc->select(chp, xfer->c_drive); 527 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 528 WDSD_IBM | (xfer->c_drive << 4)); 529 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, &tfd)) { 530 case WDCWAIT_OK: 531 break; 532 case WDCWAIT_TOUT: 533 goto timeout; 534 case WDCWAIT_THR: 535 return ATASTART_TH; 536 } 537 if (ata_bio->flags & ATA_LBA48) { 538 wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd), 539 ata_bio->blkno, nblks, 0, WDSD_LBA); 540 } else { 541 wdccommand(chp, xfer->c_drive, cmd, cyl, 542 head, sect, nblks, 543 (drvp->lp->d_type == DKTYPE_ST506) ? 544 drvp->lp->d_precompcyl / 4 : 0); 545 } 546 /* start timeout machinery */ 547 if ((xfer->c_flags & C_POLL) == 0) 548 callout_reset(&xfer->c_timo_callout, 549 ATA_DELAY / 1000 * hz, wdctimeout, xfer); 550 } else if (ata_bio->nblks > 1) { 551 /* The number of blocks in the last stretch may be smaller. */ 552 nblks = xfer->c_bcount / drvp->lp->d_secsize; 553 if (ata_bio->nblks > nblks) { 554 ata_bio->nblks = nblks; 555 ata_bio->nbytes = xfer->c_bcount; 556 } 557 } 558 /* If this was a write and not using DMA, push the data. */ 559 if ((ata_bio->flags & ATA_READ) == 0) { 560 /* 561 * we have to busy-wait here, we can't rely on running in 562 * thread context. 563 */ 564 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL, &tfd) != 0) { 565 printf("%s:%d:%d: timeout waiting for DRQ, " 566 "st=0x%02x, err=0x%02x\n", 567 device_xname(atac->atac_dev), chp->ch_channel, 568 xfer->c_drive, 569 ATACH_ST(tfd), ATACH_ERR(tfd)); 570 if (wdc_ata_err(drvp, ata_bio, tfd) != WDC_ATA_ERR) 571 ata_bio->error = TIMEOUT; 572 return ATASTART_ABORT; 573 } 574 if (wdc_ata_err(drvp, ata_bio, tfd) == WDC_ATA_ERR) { 575 return ATASTART_ABORT; 576 } 577 #if NATA_PIOBM 578 if (xfer->c_flags & C_PIOBM) { 579 /* start the busmastering PIO */ 580 (*wdc->piobm_start)(wdc->dma_arg, 581 chp->ch_channel, xfer->c_drive, 582 xfer->c_skip, ata_bio->nbytes, 0); 583 chp->ch_flags |= ATACH_DMA_WAIT; 584 } else 585 #endif 586 587 wdc->dataout_pio(chp, drvp->drive_flags, 588 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 589 } 590 591 #if NATA_DMA 592 intr: 593 #endif 594 /* Wait for IRQ (either real or polled) */ 595 return (ata_bio->flags & ATA_POLL) ? ATASTART_POLL : ATASTART_STARTED; 596 597 timeout: 598 printf("%s:%d:%d: not ready, st=0x%02x, err=0x%02x\n", 599 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 600 ATACH_ST(tfd), ATACH_ERR(tfd)); 601 if (wdc_ata_err(drvp, ata_bio, tfd) != WDC_ATA_ERR) 602 ata_bio->error = TIMEOUT; 603 return ATASTART_ABORT; 604 } 605 606 static void 607 wdc_ata_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 608 { 609 /* Wait for at last 400ns for status bit to be valid */ 610 delay(1); 611 #if NATA_DMA 612 if (chp->ch_flags & ATACH_DMA_WAIT) { 613 wdc_dmawait(chp, xfer, ATA_DELAY); 614 chp->ch_flags &= ~ATACH_DMA_WAIT; 615 } 616 #endif 617 wdc_ata_bio_intr(chp, xfer, 0); 618 } 619 620 static int 621 wdc_ata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int is) 622 { 623 struct atac_softc *atac = chp->ch_atac; 624 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 625 struct ata_bio *ata_bio = &xfer->c_bio; 626 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 627 int drv_err, tfd; 628 bool poll = ((xfer->c_flags & C_POLL) != 0); 629 630 ATADEBUG_PRINT(("wdc_ata_bio_intr %s:%d:%d\n", 631 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 632 DEBUG_INTR | DEBUG_XFERS); 633 634 ata_channel_lock(chp); 635 636 /* Is it not a transfer, but a control operation? */ 637 if (drvp->state < READY) { 638 printf("%s:%d:%d: bad state %d in wdc_ata_bio_intr\n", 639 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 640 drvp->state); 641 panic("wdc_ata_bio_intr: bad state"); 642 } 643 644 /* 645 * if we missed an interrupt in a PIO transfer, reset and restart. 646 * Don't try to continue transfer, we may have missed cycles. 647 */ 648 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 649 ata_bio->error = TIMEOUT; 650 goto err; 651 } 652 653 #if NATA_PIOBM 654 /* Transfer-done interrupt for busmastering PIO read */ 655 if ((xfer->c_flags & C_PIOBM) && (chp->ch_flags & ATACH_PIOBM_WAIT)) { 656 chp->ch_flags &= ~ATACH_PIOBM_WAIT; 657 goto end; 658 } 659 #endif 660 661 /* Ack interrupt done by wdc_wait_for_unbusy */ 662 if (wdc_wait_for_unbusy(chp, poll ? ATA_DELAY : 0, AT_POLL, &tfd) < 0) { 663 if (!poll && (xfer->c_flags & C_TIMEOU) == 0) { 664 ata_channel_unlock(chp); 665 return 0; /* IRQ was not for us */ 666 } 667 printf("%s:%d:%d: device timeout, c_bcount=%d, c_skip%d\n", 668 device_xname(atac->atac_dev), chp->ch_channel, 669 xfer->c_drive, xfer->c_bcount, xfer->c_skip); 670 ata_bio->error = TIMEOUT; 671 goto err; 672 } 673 if (wdc->irqack) 674 wdc->irqack(chp); 675 676 drv_err = wdc_ata_err(drvp, ata_bio, tfd); 677 678 #if NATA_DMA 679 /* If we were using DMA, Turn off the DMA channel and check for error */ 680 if (xfer->c_flags & C_DMA) { 681 if (ata_bio->flags & ATA_POLL) { 682 /* 683 * IDE drives deassert WDCS_BSY before transfer is 684 * complete when using DMA. Polling for DRQ to deassert 685 * is not enough DRQ is not required to be 686 * asserted for DMA transfers, so poll for DRDY. 687 */ 688 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 689 ATA_DELAY, ATA_POLL, &tfd) == WDCWAIT_TOUT) { 690 printf("%s:%d:%d: polled transfer timed out " 691 "(st=0x%x)\n", 692 device_xname(atac->atac_dev), 693 chp->ch_channel, xfer->c_drive, 694 ATACH_ST(tfd)); 695 ata_bio->error = TIMEOUT; 696 drv_err = WDC_ATA_ERR; 697 } 698 } 699 if (wdc->dma_status != 0) { 700 if (drv_err != WDC_ATA_ERR) { 701 ata_bio->error = ERR_DMA; 702 drv_err = WDC_ATA_ERR; 703 } 704 } 705 if (ATACH_ST(tfd) & WDCS_DRQ) { 706 if (drv_err != WDC_ATA_ERR) { 707 printf("%s:%d:%d: intr with DRQ (st=0x%x)\n", 708 device_xname(atac->atac_dev), 709 chp->ch_channel, 710 xfer->c_drive, ATACH_ST(tfd)); 711 ata_bio->error = TIMEOUT; 712 drv_err = WDC_ATA_ERR; 713 } 714 } 715 if (drv_err != WDC_ATA_ERR) 716 goto end; 717 if (ata_bio->r_error & WDCE_CRC || ata_bio->error == ERR_DMA) { 718 ata_channel_unlock(chp); 719 ata_dmaerr(drvp, 720 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 721 ata_channel_lock(chp); 722 goto err; 723 } 724 } 725 #endif /* NATA_DMA */ 726 727 /* if we had an error, end */ 728 if (drv_err == WDC_ATA_ERR) 729 goto err; 730 731 /* If this was a read and not using DMA, fetch the data. */ 732 if ((ata_bio->flags & ATA_READ) != 0) { 733 if ((ATACH_ST(tfd) & WDCS_DRQ) != WDCS_DRQ) { 734 printf("%s:%d:%d: read intr before drq\n", 735 device_xname(atac->atac_dev), chp->ch_channel, 736 xfer->c_drive); 737 ata_bio->error = TIMEOUT; 738 goto err; 739 } 740 #if NATA_PIOBM 741 if (xfer->c_flags & C_PIOBM) { 742 /* start the busmastering PIO */ 743 (*wdc->piobm_start)(wdc->dma_arg, 744 chp->ch_channel, xfer->c_drive, 745 xfer->c_skip, ata_bio->nbytes, 746 WDC_PIOBM_XFER_IRQ); 747 chp->ch_flags |= ATACH_DMA_WAIT | ATACH_PIOBM_WAIT; 748 ata_channel_unlock(chp); 749 return 1; 750 } 751 #endif 752 wdc->datain_pio(chp, drvp->drive_flags, 753 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 754 } 755 756 #if NATA_DMA || NATA_PIOBM 757 end: 758 #endif 759 ata_bio->blkno += ata_bio->nblks; 760 ata_bio->blkdone += ata_bio->nblks; 761 xfer->c_skip += ata_bio->nbytes; 762 xfer->c_bcount -= ata_bio->nbytes; 763 764 /* See if this transfer is complete. */ 765 if (xfer->c_bcount > 0) { 766 if ((ata_bio->flags & ATA_POLL) == 0) { 767 /* Start the next operation */ 768 ata_xfer_start(xfer); 769 } else { 770 /* Let _wdc_ata_bio_start do the loop */ 771 } 772 ata_channel_unlock(chp); 773 return 1; 774 } 775 776 /* Done with this transfer */ 777 ata_bio->error = NOERROR; 778 err: ata_channel_unlock(chp); 779 wdc_ata_bio_done(chp, xfer); 780 return 1; 781 } 782 783 static void 784 wdc_ata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 785 int reason) 786 { 787 struct ata_bio *ata_bio = &xfer->c_bio; 788 int drive = xfer->c_drive; 789 bool deactivate = true; 790 791 ata_bio->flags |= ATA_ITSDONE; 792 switch (reason) { 793 case KILL_GONE_INACTIVE: 794 deactivate = false; 795 /* FALLTHROUGH */ 796 case KILL_GONE: 797 ata_bio->error = ERR_NODEV; 798 break; 799 case KILL_RESET: 800 ata_bio->error = ERR_RESET; 801 break; 802 default: 803 printf("wdc_ata_bio_kill_xfer: unknown reason %d\n", 804 reason); 805 panic("wdc_ata_bio_kill_xfer"); 806 } 807 ata_bio->r_error = WDCE_ABRT; 808 809 if (deactivate) 810 ata_deactivate_xfer(chp, xfer); 811 812 ATADEBUG_PRINT(("wdc_ata_bio_kill_xfer: drv_done\n"), DEBUG_XFERS); 813 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 814 } 815 816 static void 817 wdc_ata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 818 { 819 struct ata_bio *ata_bio = &xfer->c_bio; 820 int drive = xfer->c_drive; 821 822 ATADEBUG_PRINT(("wdc_ata_bio_done %s:%d:%d: flags 0x%x\n", 823 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 824 xfer->c_drive, (u_int)xfer->c_flags), 825 DEBUG_XFERS); 826 827 if (ata_waitdrain_xfer_check(chp, xfer)) 828 return; 829 830 /* feed back residual bcount to our caller */ 831 ata_bio->bcount = xfer->c_bcount; 832 833 /* mark controller inactive and free xfer */ 834 ata_deactivate_xfer(chp, xfer); 835 836 ata_bio->flags |= ATA_ITSDONE; 837 ATADEBUG_PRINT(("wdc_ata_done: drv_done\n"), DEBUG_XFERS); 838 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 839 ATADEBUG_PRINT(("atastart from wdc_ata_done, flags 0x%x\n", 840 chp->ch_flags), DEBUG_XFERS); 841 atastart(chp); 842 } 843 844 static int 845 wdc_ata_err(struct ata_drive_datas *drvp, struct ata_bio *ata_bio, int tfd) 846 { 847 ata_bio->error = 0; 848 if (ATACH_ST(tfd) & WDCS_BSY) { 849 ata_bio->error = TIMEOUT; 850 return WDC_ATA_ERR; 851 } 852 853 if (ATACH_ST(tfd) & WDCS_DWF) { 854 ata_bio->error = ERR_DF; 855 return WDC_ATA_ERR; 856 } 857 858 if (ATACH_ST(tfd) & WDCS_ERR) { 859 ata_bio->error = ERROR; 860 ata_bio->r_error = ATACH_ERR(tfd); 861 if (ata_bio->r_error & (WDCE_BBK | WDCE_UNC | WDCE_IDNF | 862 WDCE_ABRT | WDCE_TK0NF | WDCE_AMNF)) 863 return WDC_ATA_ERR; 864 return WDC_ATA_NOERR; 865 } 866 867 if (ATACH_ST(tfd) & WDCS_CORR) 868 ata_bio->flags |= ATA_CORR; 869 return WDC_ATA_NOERR; 870 } 871 872 static int 873 wdc_ata_addref(struct ata_drive_datas *drvp) 874 { 875 struct ata_channel *chp = drvp->chnl_softc; 876 877 return (ata_addref(chp)); 878 } 879 880 static void 881 wdc_ata_delref(struct ata_drive_datas *drvp) 882 { 883 struct ata_channel *chp = drvp->chnl_softc; 884 885 ata_delref(chp); 886 } 887
Indexes created Fri Sep 26 08:10:20 GMT 2025