ata_wdc.c revision 1.109.2.2
1 /* $NetBSD: ata_wdc.c,v 1.109.2.2 2018/09/06 06:55:48 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: ata_wdc.c,v 1.109.2.2 2018/09/06 06:55:48 pgoyette Exp $"); 58 59 #include "opt_ata.h" 60 #include "opt_wdc.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/file.h> 66 #include <sys/stat.h> 67 #include <sys/buf.h> 68 #include <sys/bufq.h> 69 #include <sys/malloc.h> 70 #include <sys/device.h> 71 #include <sys/disklabel.h> 72 #include <sys/syslog.h> 73 #include <sys/proc.h> 74 75 #include <sys/intr.h> 76 #include <sys/bus.h> 77 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 78 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 79 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 80 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 81 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 82 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 83 84 #include <dev/ata/ataconf.h> 85 #include <dev/ata/atareg.h> 86 #include <dev/ata/atavar.h> 87 #include <dev/ic/wdcreg.h> 88 #include <dev/ic/wdcvar.h> 89 90 #define DEBUG_INTR 0x01 91 #define DEBUG_XFERS 0x02 92 #define DEBUG_STATUS 0x04 93 #define DEBUG_FUNCS 0x08 94 #define DEBUG_PROBE 0x10 95 #ifdef ATADEBUG 96 extern int wdcdebug_wd_mask; /* inited in wd.c */ 97 #define ATADEBUG_PRINT(args, level) \ 98 if (wdcdebug_wd_mask & (level)) \ 99 printf args 100 #else 101 #define ATADEBUG_PRINT(args, level) 102 #endif 103 104 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 105 106 static int wdc_ata_bio(struct ata_drive_datas*, struct ata_xfer *); 107 static int wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 108 static int _wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 109 static void wdc_ata_bio_poll(struct ata_channel *,struct ata_xfer *); 110 static int wdc_ata_bio_intr(struct ata_channel *, struct ata_xfer *, 111 int); 112 static void wdc_ata_bio_kill_xfer(struct ata_channel *, 113 struct ata_xfer *, int); 114 static void wdc_ata_bio_done(struct ata_channel *, struct ata_xfer *); 115 static int wdc_ata_err(struct ata_drive_datas *, struct ata_bio *, int); 116 #define WDC_ATA_NOERR 0x00 /* Drive doesn't report an error */ 117 #define WDC_ATA_RECOV 0x01 /* There was a recovered error */ 118 #define WDC_ATA_ERR 0x02 /* Drive reports an error */ 119 static int wdc_ata_addref(struct ata_drive_datas *); 120 static void wdc_ata_delref(struct ata_drive_datas *); 121 122 const struct ata_bustype wdc_ata_bustype = { 123 SCSIPI_BUSTYPE_ATA, 124 wdc_ata_bio, 125 wdc_reset_drive, 126 wdc_reset_channel, 127 wdc_exec_command, 128 ata_get_params, 129 wdc_ata_addref, 130 wdc_ata_delref, 131 ata_kill_pending, 132 }; 133 134 /* 135 * Handle block I/O operation. Return ATACMD_COMPLETE, ATACMD_QUEUED, or 136 * ATACMD_TRY_AGAIN. Must be called at splbio(). 137 */ 138 static int 139 wdc_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 140 { 141 struct ata_channel *chp = drvp->chnl_softc; 142 struct atac_softc *atac = chp->ch_atac; 143 struct ata_bio *ata_bio = &xfer->c_bio; 144 145 if (atac->atac_cap & ATAC_CAP_NOIRQ) 146 ata_bio->flags |= ATA_POLL; 147 if (ata_bio->flags & ATA_POLL) 148 xfer->c_flags |= C_POLL; 149 #if NATA_DMA 150 if ((drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) && 151 (ata_bio->flags & ATA_SINGLE) == 0) 152 xfer->c_flags |= C_DMA; 153 #endif 154 #if NATA_DMA && NATA_PIOBM 155 else 156 #endif 157 #if NATA_PIOBM 158 if (atac->atac_cap & ATAC_CAP_PIOBM) 159 xfer->c_flags |= C_PIOBM; 160 #endif 161 xfer->c_drive = drvp->drive; 162 xfer->c_databuf = ata_bio->databuf; 163 xfer->c_bcount = ata_bio->bcount; 164 xfer->c_start = wdc_ata_bio_start; 165 xfer->c_poll = wdc_ata_bio_poll; 166 xfer->c_abort = wdc_ata_bio_done; 167 xfer->c_intr = wdc_ata_bio_intr; 168 xfer->c_kill_xfer = wdc_ata_bio_kill_xfer; 169 ata_exec_xfer(chp, xfer); 170 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 171 } 172 173 static int 174 wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 175 { 176 struct atac_softc *atac = chp->ch_atac; 177 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 178 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 179 struct ata_bio *ata_bio = &xfer->c_bio; 180 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 181 int wait_flags, tfd; 182 const char *errstring; 183 #ifdef WDC_NO_IDS 184 wait_flags = AT_POLL; 185 #else 186 wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 187 #endif 188 189 ATADEBUG_PRINT(("wdc_ata_bio_start %s:%d:%d state %d drive_flags 0x%x " 190 "c_flags 0x%x ch_flags 0x%x\n", 191 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 192 drvp->state, drvp->drive_flags, xfer->c_flags, chp->ch_flags), 193 DEBUG_XFERS); 194 195 ata_channel_lock_owned(chp); 196 197 /* Do control operations specially. */ 198 if (__predict_false(drvp->state < READY)) { 199 /* 200 * Actually, we want to be careful not to mess with the control 201 * state if the device is currently busy, but we can assume 202 * that we never get to this point if that's the case. 203 */ 204 /* If it's not a polled command, we need the kernel thread */ 205 if ((xfer->c_flags & C_POLL) == 0 && 206 (chp->ch_flags & ATACH_TH_RUN) == 0) { 207 return ATASTART_TH; 208 } 209 /* 210 * disable interrupts, all commands here should be quick 211 * enough to be able to poll, and we don't go here that often 212 */ 213 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 214 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 215 wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS); 216 if (wdc->select) 217 wdc->select(chp, xfer->c_drive); 218 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 219 WDSD_IBM | (xfer->c_drive << 4)); 220 DELAY(10); 221 errstring = "wait"; 222 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 223 &tfd)) 224 goto ctrltimeout; 225 wdccommandshort(chp, xfer->c_drive, WDCC_RECAL); 226 /* Wait for at last 400ns for status bit to be valid */ 227 DELAY(1); 228 errstring = "recal"; 229 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 230 &tfd)) 231 goto ctrltimeout; 232 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 233 goto ctrlerror; 234 /* Don't try to set modes if controller can't be adjusted */ 235 if (atac->atac_set_modes == NULL) 236 goto geometry; 237 /* Also don't try if the drive didn't report its mode */ 238 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 239 goto geometry; 240 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 241 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 242 errstring = "piomode"; 243 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 244 &tfd)) 245 goto ctrltimeout; 246 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 247 goto ctrlerror; 248 #if NATA_DMA 249 #if NATA_UDMA 250 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 251 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 252 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 253 } else 254 #endif 255 if (drvp->drive_flags & ATA_DRIVE_DMA) { 256 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 257 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 258 } else { 259 goto geometry; 260 } 261 errstring = "dmamode"; 262 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 263 &tfd)) 264 goto ctrltimeout; 265 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 266 goto ctrlerror; 267 #endif /* NATA_DMA */ 268 geometry: 269 if (ata_bio->flags & ATA_LBA) 270 goto multimode; 271 wdccommand(chp, xfer->c_drive, WDCC_IDP, 272 drvp->lp->d_ncylinders, 273 drvp->lp->d_ntracks - 1, 0, drvp->lp->d_nsectors, 274 (drvp->lp->d_type == DKTYPE_ST506) ? 275 drvp->lp->d_precompcyl / 4 : 0); 276 errstring = "geometry"; 277 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 278 &tfd)) 279 goto ctrltimeout; 280 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 281 goto ctrlerror; 282 multimode: 283 if (drvp->multi == 1) 284 goto ready; 285 wdccommand(chp, xfer->c_drive, WDCC_SETMULTI, 0, 0, 0, 286 drvp->multi, 0); 287 errstring = "setmulti"; 288 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 289 &tfd)) 290 goto ctrltimeout; 291 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 292 goto ctrlerror; 293 ready: 294 drvp->state = READY; 295 /* 296 * The drive is usable now 297 */ 298 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 299 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 300 wd_aux_ctlr, WDCTL_4BIT); 301 delay(10); /* some drives need a little delay here */ 302 } 303 304 return _wdc_ata_bio_start(chp, xfer); 305 ctrltimeout: 306 printf("%s:%d:%d: %s timed out\n", 307 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 308 errstring); 309 ata_bio->error = TIMEOUT; 310 goto ctrldone; 311 ctrlerror: 312 printf("%s:%d:%d: %s ", 313 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 314 errstring); 315 if (ATACH_ST(tfd) & WDCS_DWF) { 316 printf("drive fault\n"); 317 ata_bio->error = ERR_DF; 318 } else { 319 ata_bio->r_error = ATACH_ERR(tfd); 320 ata_bio->error = ERROR; 321 printf("error (%x)\n", ata_bio->r_error); 322 } 323 ctrldone: 324 drvp->state = 0; 325 326 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 327 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 328 WDCTL_4BIT); 329 return ATASTART_ABORT; 330 } 331 332 static int 333 _wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 334 { 335 struct atac_softc *atac = chp->ch_atac; 336 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 337 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 338 struct ata_bio *ata_bio = &xfer->c_bio; 339 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 340 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 341 uint16_t cyl; 342 uint8_t head, sect, cmd = 0; 343 int nblks, tfd; 344 #if NATA_DMA || NATA_PIOBM 345 int error, dma_flags = 0; 346 #endif 347 348 ATADEBUG_PRINT(("_wdc_ata_bio_start %s:%d:%d\n", 349 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 350 DEBUG_INTR | DEBUG_XFERS); 351 352 #if NATA_DMA || NATA_PIOBM 353 if (xfer->c_flags & (C_DMA | C_PIOBM)) { 354 #if NATA_DMA 355 if (drvp->n_xfers <= NXFER) 356 drvp->n_xfers++; 357 #endif 358 dma_flags = (ata_bio->flags & ATA_READ) ? WDC_DMA_READ : 0; 359 if (ata_bio->flags & ATA_LBA48) 360 dma_flags |= WDC_DMA_LBA48; 361 } 362 #endif 363 /* 364 * 365 * When starting a multi-sector transfer, or doing single-sector 366 * transfers... 367 */ 368 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 369 if (ata_bio->flags & ATA_SINGLE) 370 nblks = 1; 371 else 372 nblks = xfer->c_bcount / drvp->lp->d_secsize; 373 /* Check for bad sectors and adjust transfer, if necessary. */ 374 if ((drvp->lp->d_flags & D_BADSECT) != 0) { 375 long blkdiff; 376 int i; 377 for (i = 0; (blkdiff = drvp->badsect[i]) != -1; 378 i++) { 379 blkdiff -= ata_bio->blkno; 380 if (blkdiff < 0) 381 continue; 382 if (blkdiff == 0) { 383 /* Replace current block of transfer. */ 384 ata_bio->blkno = 385 drvp->lp->d_secperunit - 386 drvp->lp->d_nsectors - i - 1; 387 } 388 if (blkdiff < nblks) { 389 /* Bad block inside transfer. */ 390 ata_bio->flags |= ATA_SINGLE; 391 nblks = 1; 392 } 393 break; 394 } 395 /* Transfer is okay now. */ 396 } 397 if (ata_bio->flags & ATA_LBA48) { 398 sect = 0; 399 cyl = 0; 400 head = 0; 401 } else if (ata_bio->flags & ATA_LBA) { 402 sect = (ata_bio->blkno >> 0) & 0xff; 403 cyl = (ata_bio->blkno >> 8) & 0xffff; 404 head = (ata_bio->blkno >> 24) & 0x0f; 405 head |= WDSD_LBA; 406 } else { 407 int blkno = ata_bio->blkno; 408 sect = blkno % drvp->lp->d_nsectors; 409 sect++; /* Sectors begin with 1, not 0. */ 410 blkno /= drvp->lp->d_nsectors; 411 head = blkno % drvp->lp->d_ntracks; 412 blkno /= drvp->lp->d_ntracks; 413 cyl = blkno; 414 head |= WDSD_CHS; 415 } 416 #if NATA_DMA 417 if (xfer->c_flags & C_DMA) { 418 uint16_t count = nblks, features = 0; 419 420 ata_bio->nblks = nblks; 421 ata_bio->nbytes = xfer->c_bcount; 422 cmd = (ata_bio->flags & ATA_READ) ? 423 WDCC_READDMA : WDCC_WRITEDMA; 424 /* Init the DMA channel. */ 425 error = (*wdc->dma_init)(wdc->dma_arg, 426 chp->ch_channel, xfer->c_drive, 427 (char *)xfer->c_databuf + xfer->c_skip, 428 ata_bio->nbytes, dma_flags); 429 if (error) { 430 if (error == EINVAL) { 431 /* 432 * We can't do DMA on this transfer 433 * for some reason. Fall back to 434 * PIO. 435 */ 436 xfer->c_flags &= ~C_DMA; 437 error = 0; 438 goto do_pio; 439 } 440 ata_bio->error = ERR_DMA; 441 ata_bio->r_error = 0; 442 return ATASTART_ABORT; 443 } 444 /* Initiate command */ 445 if (wdc->select) 446 wdc->select(chp, xfer->c_drive); 447 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 448 0, WDSD_IBM | (xfer->c_drive << 4)); 449 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, 450 &tfd)) { 451 case WDCWAIT_OK: 452 break; 453 case WDCWAIT_TOUT: 454 goto timeout; 455 case WDCWAIT_THR: 456 return ATASTART_TH; 457 } 458 /* start the DMA channel before */ 459 if ((chp->ch_flags & ATACH_DMA_BEFORE_CMD) != 0) 460 (*wdc->dma_start)(wdc->dma_arg, 461 chp->ch_channel, xfer->c_drive); 462 if (ata_bio->flags & ATA_LBA48) { 463 uint8_t device = WDSD_LBA; 464 cmd = atacmd_to48(cmd); 465 466 atacmd_toncq(xfer, &cmd, &count, &features, 467 &device); 468 469 wdccommandext(chp, xfer->c_drive, cmd, 470 ata_bio->blkno, count, features, device); 471 } else { 472 wdccommand(chp, xfer->c_drive, cmd, cyl, 473 head, sect, count, features); 474 } 475 /* start the DMA channel after */ 476 if ((chp->ch_flags & ATACH_DMA_BEFORE_CMD) == 0) 477 (*wdc->dma_start)(wdc->dma_arg, 478 chp->ch_channel, xfer->c_drive); 479 chp->ch_flags |= ATACH_DMA_WAIT; 480 /* start timeout machinery */ 481 if ((xfer->c_flags & C_POLL) == 0) 482 callout_reset(&xfer->c_timo_callout, 483 ATA_DELAY / 1000 * hz, wdctimeout, xfer); 484 /* wait for irq */ 485 goto intr; 486 } /* else not DMA */ 487 do_pio: 488 #endif /* NATA_DMA */ 489 #if NATA_PIOBM 490 if ((xfer->c_flags & C_PIOBM) && xfer->c_skip == 0) { 491 if (ata_bio->flags & ATA_POLL) { 492 /* XXX not supported yet --- fall back to PIO */ 493 xfer->c_flags &= ~C_PIOBM; 494 } else { 495 /* Init the DMA channel. */ 496 error = (*wdc->dma_init)(wdc->dma_arg, 497 chp->ch_channel, xfer->c_drive, 498 (char *)xfer->c_databuf + xfer->c_skip, 499 xfer->c_bcount, 500 dma_flags | WDC_DMA_PIOBM_ATA); 501 if (error) { 502 if (error == EINVAL) { 503 /* 504 * We can't do DMA on this 505 * transfer for some reason. 506 * Fall back to PIO. 507 */ 508 xfer->c_flags &= ~C_PIOBM; 509 error = 0; 510 } else { 511 ata_bio->error = ERR_DMA; 512 ata_bio->r_error = 0; 513 return ATASTART_ABORT; 514 } 515 } 516 } 517 } 518 #endif 519 ata_bio->nblks = uimin(nblks, drvp->multi); 520 ata_bio->nbytes = ata_bio->nblks * drvp->lp->d_secsize; 521 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 522 if (ata_bio->nblks > 1) { 523 cmd = (ata_bio->flags & ATA_READ) ? 524 WDCC_READMULTI : WDCC_WRITEMULTI; 525 } else { 526 cmd = (ata_bio->flags & ATA_READ) ? 527 WDCC_READ : WDCC_WRITE; 528 } 529 /* Initiate command! */ 530 if (wdc->select) 531 wdc->select(chp, xfer->c_drive); 532 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 533 WDSD_IBM | (xfer->c_drive << 4)); 534 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, &tfd)) { 535 case WDCWAIT_OK: 536 break; 537 case WDCWAIT_TOUT: 538 goto timeout; 539 case WDCWAIT_THR: 540 return ATASTART_TH; 541 } 542 if (ata_bio->flags & ATA_LBA48) { 543 wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd), 544 ata_bio->blkno, nblks, 0, WDSD_LBA); 545 } else { 546 wdccommand(chp, xfer->c_drive, cmd, cyl, 547 head, sect, nblks, 548 (drvp->lp->d_type == DKTYPE_ST506) ? 549 drvp->lp->d_precompcyl / 4 : 0); 550 } 551 /* start timeout machinery */ 552 if ((xfer->c_flags & C_POLL) == 0) 553 callout_reset(&xfer->c_timo_callout, 554 ATA_DELAY / 1000 * hz, wdctimeout, xfer); 555 } else if (ata_bio->nblks > 1) { 556 /* The number of blocks in the last stretch may be smaller. */ 557 nblks = xfer->c_bcount / drvp->lp->d_secsize; 558 if (ata_bio->nblks > nblks) { 559 ata_bio->nblks = nblks; 560 ata_bio->nbytes = xfer->c_bcount; 561 } 562 } 563 /* If this was a write and not using DMA, push the data. */ 564 if ((ata_bio->flags & ATA_READ) == 0) { 565 /* 566 * we have to busy-wait here, we can't rely on running in 567 * thread context. 568 */ 569 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL, &tfd) != 0) { 570 printf("%s:%d:%d: timeout waiting for DRQ, " 571 "st=0x%02x, err=0x%02x\n", 572 device_xname(atac->atac_dev), chp->ch_channel, 573 xfer->c_drive, 574 ATACH_ST(tfd), ATACH_ERR(tfd)); 575 if (wdc_ata_err(drvp, ata_bio, tfd) != WDC_ATA_ERR) 576 ata_bio->error = TIMEOUT; 577 return ATASTART_ABORT; 578 } 579 if (wdc_ata_err(drvp, ata_bio, tfd) == WDC_ATA_ERR) { 580 return ATASTART_ABORT; 581 } 582 #if NATA_PIOBM 583 if (xfer->c_flags & C_PIOBM) { 584 /* start the busmastering PIO */ 585 (*wdc->piobm_start)(wdc->dma_arg, 586 chp->ch_channel, xfer->c_drive, 587 xfer->c_skip, ata_bio->nbytes, 0); 588 chp->ch_flags |= ATACH_DMA_WAIT; 589 } else 590 #endif 591 592 wdc->dataout_pio(chp, drvp->drive_flags, 593 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 594 } 595 596 #if NATA_DMA 597 intr: 598 #endif 599 /* Wait for IRQ (either real or polled) */ 600 if ((ata_bio->flags & ATA_POLL) == 0) { 601 chp->ch_flags |= ATACH_IRQ_WAIT; 602 return ATASTART_STARTED; 603 } else { 604 return ATASTART_POLL; 605 } 606 607 timeout: 608 printf("%s:%d:%d: not ready, st=0x%02x, err=0x%02x\n", 609 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 610 ATACH_ST(tfd), ATACH_ERR(tfd)); 611 if (wdc_ata_err(drvp, ata_bio, tfd) != WDC_ATA_ERR) 612 ata_bio->error = TIMEOUT; 613 return ATASTART_ABORT; 614 } 615 616 static void 617 wdc_ata_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 618 { 619 /* Wait for at last 400ns for status bit to be valid */ 620 delay(1); 621 #if NATA_DMA 622 if (chp->ch_flags & ATACH_DMA_WAIT) { 623 wdc_dmawait(chp, xfer, ATA_DELAY); 624 chp->ch_flags &= ~ATACH_DMA_WAIT; 625 } 626 #endif 627 wdc_ata_bio_intr(chp, xfer, 0); 628 } 629 630 static int 631 wdc_ata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 632 { 633 struct atac_softc *atac = chp->ch_atac; 634 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 635 struct ata_bio *ata_bio = &xfer->c_bio; 636 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 637 int drv_err, tfd; 638 639 ATADEBUG_PRINT(("wdc_ata_bio_intr %s:%d:%d\n", 640 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 641 DEBUG_INTR | DEBUG_XFERS); 642 643 ata_channel_lock(chp); 644 645 /* Is it not a transfer, but a control operation? */ 646 if (drvp->state < READY) { 647 printf("%s:%d:%d: bad state %d in wdc_ata_bio_intr\n", 648 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 649 drvp->state); 650 panic("wdc_ata_bio_intr: bad state"); 651 } 652 653 /* 654 * if we missed an interrupt in a PIO transfer, reset and restart. 655 * Don't try to continue transfer, we may have missed cycles. 656 */ 657 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 658 ata_bio->error = TIMEOUT; 659 goto err; 660 } 661 662 #if NATA_PIOBM 663 /* Transfer-done interrupt for busmastering PIO read */ 664 if ((xfer->c_flags & C_PIOBM) && (chp->ch_flags & ATACH_PIOBM_WAIT)) { 665 chp->ch_flags &= ~ATACH_PIOBM_WAIT; 666 goto end; 667 } 668 #endif 669 670 /* Ack interrupt done by wdc_wait_for_unbusy */ 671 if (wdc_wait_for_unbusy(chp, 672 (irq == 0) ? ATA_DELAY : 0, AT_POLL, &tfd) < 0) { 673 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 674 ata_channel_unlock(chp); 675 return 0; /* IRQ was not for us */ 676 } 677 printf("%s:%d:%d: device timeout, c_bcount=%d, c_skip%d\n", 678 device_xname(atac->atac_dev), chp->ch_channel, 679 xfer->c_drive, xfer->c_bcount, xfer->c_skip); 680 ata_bio->error = TIMEOUT; 681 goto err; 682 } 683 if (wdc->irqack) 684 wdc->irqack(chp); 685 686 drv_err = wdc_ata_err(drvp, ata_bio, tfd); 687 688 #if NATA_DMA 689 /* If we were using DMA, Turn off the DMA channel and check for error */ 690 if (xfer->c_flags & C_DMA) { 691 if (ata_bio->flags & ATA_POLL) { 692 /* 693 * IDE drives deassert WDCS_BSY before transfer is 694 * complete when using DMA. Polling for DRQ to deassert 695 * is not enough DRQ is not required to be 696 * asserted for DMA transfers, so poll for DRDY. 697 */ 698 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 699 ATA_DELAY, ATA_POLL, &tfd) == WDCWAIT_TOUT) { 700 printf("%s:%d:%d: polled transfer timed out " 701 "(st=0x%x)\n", 702 device_xname(atac->atac_dev), 703 chp->ch_channel, xfer->c_drive, 704 ATACH_ST(tfd)); 705 ata_bio->error = TIMEOUT; 706 drv_err = WDC_ATA_ERR; 707 } 708 } 709 if (wdc->dma_status != 0) { 710 if (drv_err != WDC_ATA_ERR) { 711 ata_bio->error = ERR_DMA; 712 drv_err = WDC_ATA_ERR; 713 } 714 } 715 if (ATACH_ST(tfd) & WDCS_DRQ) { 716 if (drv_err != WDC_ATA_ERR) { 717 printf("%s:%d:%d: intr with DRQ (st=0x%x)\n", 718 device_xname(atac->atac_dev), 719 chp->ch_channel, 720 xfer->c_drive, ATACH_ST(tfd)); 721 ata_bio->error = TIMEOUT; 722 drv_err = WDC_ATA_ERR; 723 } 724 } 725 if (drv_err != WDC_ATA_ERR) 726 goto end; 727 if (ata_bio->r_error & WDCE_CRC || ata_bio->error == ERR_DMA) { 728 ata_channel_unlock(chp); 729 ata_dmaerr(drvp, 730 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 731 ata_channel_lock(chp); 732 goto err; 733 } 734 } 735 #endif /* NATA_DMA */ 736 737 /* if we had an error, end */ 738 if (drv_err == WDC_ATA_ERR) 739 goto err; 740 741 /* If this was a read and not using DMA, fetch the data. */ 742 if ((ata_bio->flags & ATA_READ) != 0) { 743 if ((ATACH_ST(tfd) & WDCS_DRQ) != WDCS_DRQ) { 744 printf("%s:%d:%d: read intr before drq\n", 745 device_xname(atac->atac_dev), chp->ch_channel, 746 xfer->c_drive); 747 ata_bio->error = TIMEOUT; 748 goto err; 749 } 750 #if NATA_PIOBM 751 if (xfer->c_flags & C_PIOBM) { 752 /* start the busmastering PIO */ 753 (*wdc->piobm_start)(wdc->dma_arg, 754 chp->ch_channel, xfer->c_drive, 755 xfer->c_skip, ata_bio->nbytes, 756 WDC_PIOBM_XFER_IRQ); 757 chp->ch_flags |= ATACH_DMA_WAIT | ATACH_PIOBM_WAIT; 758 ata_channel_unlock(chp); 759 return 1; 760 } 761 #endif 762 wdc->datain_pio(chp, drvp->drive_flags, 763 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 764 } 765 766 #if NATA_DMA || NATA_PIOBM 767 end: 768 #endif 769 ata_bio->blkno += ata_bio->nblks; 770 ata_bio->blkdone += ata_bio->nblks; 771 xfer->c_skip += ata_bio->nbytes; 772 xfer->c_bcount -= ata_bio->nbytes; 773 774 /* See if this transfer is complete. */ 775 if (xfer->c_bcount > 0) { 776 if ((ata_bio->flags & ATA_POLL) == 0) { 777 /* Start the next operation */ 778 ata_xfer_start(xfer); 779 } else { 780 /* Let _wdc_ata_bio_start do the loop */ 781 } 782 ata_channel_unlock(chp); 783 return 1; 784 } 785 786 /* Done with this transfer */ 787 ata_bio->error = NOERROR; 788 err: ata_channel_unlock(chp); 789 wdc_ata_bio_done(chp, xfer); 790 return 1; 791 } 792 793 static void 794 wdc_ata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 795 int reason) 796 { 797 struct ata_bio *ata_bio = &xfer->c_bio; 798 int drive = xfer->c_drive; 799 bool deactivate = true; 800 801 ata_bio->flags |= ATA_ITSDONE; 802 switch (reason) { 803 case KILL_GONE_INACTIVE: 804 deactivate = false; 805 /* FALLTHROUGH */ 806 case KILL_GONE: 807 ata_bio->error = ERR_NODEV; 808 break; 809 case KILL_RESET: 810 ata_bio->error = ERR_RESET; 811 break; 812 default: 813 printf("wdc_ata_bio_kill_xfer: unknown reason %d\n", 814 reason); 815 panic("wdc_ata_bio_kill_xfer"); 816 } 817 ata_bio->r_error = WDCE_ABRT; 818 819 if (deactivate) 820 ata_deactivate_xfer(chp, xfer); 821 822 ATADEBUG_PRINT(("wdc_ata_bio_kill_xfer: drv_done\n"), DEBUG_XFERS); 823 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 824 } 825 826 static void 827 wdc_ata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 828 { 829 struct ata_bio *ata_bio = &xfer->c_bio; 830 int drive = xfer->c_drive; 831 832 ATADEBUG_PRINT(("wdc_ata_bio_done %s:%d:%d: flags 0x%x\n", 833 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 834 xfer->c_drive, (u_int)xfer->c_flags), 835 DEBUG_XFERS); 836 837 if (ata_waitdrain_xfer_check(chp, xfer)) 838 return; 839 840 /* feed back residual bcount to our caller */ 841 ata_bio->bcount = xfer->c_bcount; 842 843 /* mark controller inactive and free xfer */ 844 ata_deactivate_xfer(chp, xfer); 845 846 ata_bio->flags |= ATA_ITSDONE; 847 ATADEBUG_PRINT(("wdc_ata_done: drv_done\n"), DEBUG_XFERS); 848 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 849 ATADEBUG_PRINT(("atastart from wdc_ata_done, flags 0x%x\n", 850 chp->ch_flags), DEBUG_XFERS); 851 atastart(chp); 852 } 853 854 static int 855 wdc_ata_err(struct ata_drive_datas *drvp, struct ata_bio *ata_bio, int tfd) 856 { 857 ata_bio->error = 0; 858 if (ATACH_ST(tfd) & WDCS_BSY) { 859 ata_bio->error = TIMEOUT; 860 return WDC_ATA_ERR; 861 } 862 863 if (ATACH_ST(tfd) & WDCS_DWF) { 864 ata_bio->error = ERR_DF; 865 return WDC_ATA_ERR; 866 } 867 868 if (ATACH_ST(tfd) & WDCS_ERR) { 869 ata_bio->error = ERROR; 870 ata_bio->r_error = ATACH_ERR(tfd); 871 if (ata_bio->r_error & (WDCE_BBK | WDCE_UNC | WDCE_IDNF | 872 WDCE_ABRT | WDCE_TK0NF | WDCE_AMNF)) 873 return WDC_ATA_ERR; 874 return WDC_ATA_NOERR; 875 } 876 877 if (ATACH_ST(tfd) & WDCS_CORR) 878 ata_bio->flags |= ATA_CORR; 879 return WDC_ATA_NOERR; 880 } 881 882 static int 883 wdc_ata_addref(struct ata_drive_datas *drvp) 884 { 885 struct ata_channel *chp = drvp->chnl_softc; 886 887 return (ata_addref(chp)); 888 } 889 890 static void 891 wdc_ata_delref(struct ata_drive_datas *drvp) 892 { 893 struct ata_channel *chp = drvp->chnl_softc; 894 895 ata_delref(chp); 896 } 897
Indexes created Thu Oct 23 22:10:10 GMT 2025