ata_wdc.c revision 1.109.2.3
1 /* $NetBSD: ata_wdc.c,v 1.109.2.3 2018/11/26 01:52:30 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: ata_wdc.c,v 1.109.2.3 2018/11/26 01:52:30 pgoyette Exp $"); 58 59 #include "opt_ata.h" 60 #include "opt_wdc.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/file.h> 66 #include <sys/stat.h> 67 #include <sys/buf.h> 68 #include <sys/bufq.h> 69 #include <sys/device.h> 70 #include <sys/disklabel.h> 71 #include <sys/syslog.h> 72 #include <sys/proc.h> 73 74 #include <sys/intr.h> 75 #include <sys/bus.h> 76 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 77 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 78 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 79 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 80 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 81 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 82 83 #include <dev/ata/ataconf.h> 84 #include <dev/ata/atareg.h> 85 #include <dev/ata/atavar.h> 86 #include <dev/ic/wdcreg.h> 87 #include <dev/ic/wdcvar.h> 88 89 #define DEBUG_INTR 0x01 90 #define DEBUG_XFERS 0x02 91 #define DEBUG_STATUS 0x04 92 #define DEBUG_FUNCS 0x08 93 #define DEBUG_PROBE 0x10 94 #ifdef ATADEBUG 95 extern int wdcdebug_wd_mask; /* inited in wd.c */ 96 #define ATADEBUG_PRINT(args, level) \ 97 if (wdcdebug_wd_mask & (level)) \ 98 printf args 99 #else 100 #define ATADEBUG_PRINT(args, level) 101 #endif 102 103 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 104 105 static int wdc_ata_bio(struct ata_drive_datas*, struct ata_xfer *); 106 static int wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 107 static int _wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 108 static void wdc_ata_bio_poll(struct ata_channel *,struct ata_xfer *); 109 static int wdc_ata_bio_intr(struct ata_channel *, struct ata_xfer *, 110 int); 111 static void wdc_ata_bio_kill_xfer(struct ata_channel *, 112 struct ata_xfer *, int); 113 static void wdc_ata_bio_done(struct ata_channel *, struct ata_xfer *); 114 static int wdc_ata_err(struct ata_drive_datas *, struct ata_bio *, int); 115 #define WDC_ATA_NOERR 0x00 /* Drive doesn't report an error */ 116 #define WDC_ATA_RECOV 0x01 /* There was a recovered error */ 117 #define WDC_ATA_ERR 0x02 /* Drive reports an error */ 118 static int wdc_ata_addref(struct ata_drive_datas *); 119 static void wdc_ata_delref(struct ata_drive_datas *); 120 121 const struct ata_bustype wdc_ata_bustype = { 122 SCSIPI_BUSTYPE_ATA, 123 wdc_ata_bio, 124 wdc_reset_drive, 125 wdc_reset_channel, 126 wdc_exec_command, 127 ata_get_params, 128 wdc_ata_addref, 129 wdc_ata_delref, 130 ata_kill_pending, 131 NULL, 132 }; 133 134 static const struct ata_xfer_ops wdc_bio_xfer_ops = { 135 .c_start = wdc_ata_bio_start, 136 .c_poll = wdc_ata_bio_poll, 137 .c_abort = wdc_ata_bio_done, 138 .c_intr = wdc_ata_bio_intr, 139 .c_kill_xfer = wdc_ata_bio_kill_xfer 140 }; 141 142 /* 143 * Handle block I/O operation. Return ATACMD_COMPLETE, ATACMD_QUEUED, or 144 * ATACMD_TRY_AGAIN. Must be called at splbio(). 145 */ 146 static int 147 wdc_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 148 { 149 struct ata_channel *chp = drvp->chnl_softc; 150 struct atac_softc *atac = chp->ch_atac; 151 struct ata_bio *ata_bio = &xfer->c_bio; 152 153 if (atac->atac_cap & ATAC_CAP_NOIRQ) 154 ata_bio->flags |= ATA_POLL; 155 if (ata_bio->flags & ATA_POLL) 156 xfer->c_flags |= C_POLL; 157 #if NATA_DMA 158 if ((drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) && 159 (ata_bio->flags & ATA_SINGLE) == 0) 160 xfer->c_flags |= C_DMA; 161 #endif 162 #if NATA_DMA && NATA_PIOBM 163 else 164 #endif 165 #if NATA_PIOBM 166 if (atac->atac_cap & ATAC_CAP_PIOBM) 167 xfer->c_flags |= C_PIOBM; 168 #endif 169 xfer->c_drive = drvp->drive; 170 xfer->c_databuf = ata_bio->databuf; 171 xfer->c_bcount = ata_bio->bcount; 172 xfer->ops = &wdc_bio_xfer_ops; 173 ata_exec_xfer(chp, xfer); 174 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 175 } 176 177 static int 178 wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 179 { 180 struct atac_softc *atac = chp->ch_atac; 181 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 182 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 183 struct ata_bio *ata_bio = &xfer->c_bio; 184 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 185 int wait_flags, tfd; 186 const char *errstring; 187 #ifdef WDC_NO_IDS 188 wait_flags = AT_POLL; 189 #else 190 wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 191 #endif 192 193 ATADEBUG_PRINT(("wdc_ata_bio_start %s:%d:%d state %d drive_flags 0x%x " 194 "c_flags 0x%x ch_flags 0x%x\n", 195 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 196 drvp->state, drvp->drive_flags, xfer->c_flags, chp->ch_flags), 197 DEBUG_XFERS); 198 199 ata_channel_lock_owned(chp); 200 201 /* Do control operations specially. */ 202 if (__predict_false(drvp->state < READY)) { 203 /* 204 * Actually, we want to be careful not to mess with the control 205 * state if the device is currently busy, but we can assume 206 * that we never get to this point if that's the case. 207 */ 208 /* If it's not a polled command, we need the kernel thread */ 209 if ((xfer->c_flags & C_POLL) == 0 && 210 (chp->ch_flags & ATACH_TH_RUN) == 0) { 211 return ATASTART_TH; 212 } 213 /* 214 * disable interrupts, all commands here should be quick 215 * enough to be able to poll, and we don't go here that often 216 */ 217 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 218 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 219 wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS); 220 if (wdc->select) 221 wdc->select(chp, xfer->c_drive); 222 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 223 WDSD_IBM | (xfer->c_drive << 4)); 224 DELAY(10); 225 errstring = "wait"; 226 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 227 &tfd)) 228 goto ctrltimeout; 229 wdccommandshort(chp, xfer->c_drive, WDCC_RECAL); 230 /* Wait for at last 400ns for status bit to be valid */ 231 DELAY(1); 232 errstring = "recal"; 233 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 234 &tfd)) 235 goto ctrltimeout; 236 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 237 goto ctrlerror; 238 /* Don't try to set modes if controller can't be adjusted */ 239 if (atac->atac_set_modes == NULL) 240 goto geometry; 241 /* Also don't try if the drive didn't report its mode */ 242 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 243 goto geometry; 244 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 245 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 246 errstring = "piomode"; 247 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 248 &tfd)) 249 goto ctrltimeout; 250 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 251 goto ctrlerror; 252 #if NATA_DMA 253 #if NATA_UDMA 254 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 255 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 256 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 257 } else 258 #endif 259 if (drvp->drive_flags & ATA_DRIVE_DMA) { 260 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 261 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 262 } else { 263 goto geometry; 264 } 265 errstring = "dmamode"; 266 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 267 &tfd)) 268 goto ctrltimeout; 269 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 270 goto ctrlerror; 271 #endif /* NATA_DMA */ 272 geometry: 273 if (ata_bio->flags & ATA_LBA) 274 goto multimode; 275 wdccommand(chp, xfer->c_drive, WDCC_IDP, 276 drvp->lp->d_ncylinders, 277 drvp->lp->d_ntracks - 1, 0, drvp->lp->d_nsectors, 278 (drvp->lp->d_type == DKTYPE_ST506) ? 279 drvp->lp->d_precompcyl / 4 : 0); 280 errstring = "geometry"; 281 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 282 &tfd)) 283 goto ctrltimeout; 284 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 285 goto ctrlerror; 286 multimode: 287 if (drvp->multi == 1) 288 goto ready; 289 wdccommand(chp, xfer->c_drive, WDCC_SETMULTI, 0, 0, 0, 290 drvp->multi, 0); 291 errstring = "setmulti"; 292 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 293 &tfd)) 294 goto ctrltimeout; 295 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 296 goto ctrlerror; 297 ready: 298 drvp->state = READY; 299 /* 300 * The drive is usable now 301 */ 302 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 303 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 304 wd_aux_ctlr, WDCTL_4BIT); 305 delay(10); /* some drives need a little delay here */ 306 } 307 308 return _wdc_ata_bio_start(chp, xfer); 309 ctrltimeout: 310 printf("%s:%d:%d: %s timed out\n", 311 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 312 errstring); 313 ata_bio->error = TIMEOUT; 314 goto ctrldone; 315 ctrlerror: 316 printf("%s:%d:%d: %s ", 317 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 318 errstring); 319 if (ATACH_ST(tfd) & WDCS_DWF) { 320 printf("drive fault\n"); 321 ata_bio->error = ERR_DF; 322 } else { 323 ata_bio->r_error = ATACH_ERR(tfd); 324 ata_bio->error = ERROR; 325 printf("error (%x)\n", ata_bio->r_error); 326 } 327 ctrldone: 328 drvp->state = 0; 329 330 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 331 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 332 WDCTL_4BIT); 333 return ATASTART_ABORT; 334 } 335 336 static int 337 _wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 338 { 339 struct atac_softc *atac = chp->ch_atac; 340 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 341 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 342 struct ata_bio *ata_bio = &xfer->c_bio; 343 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 344 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 345 uint16_t cyl; 346 uint8_t head, sect, cmd = 0; 347 int nblks, tfd; 348 #if NATA_DMA || NATA_PIOBM 349 int error, dma_flags = 0; 350 #endif 351 352 ATADEBUG_PRINT(("_wdc_ata_bio_start %s:%d:%d\n", 353 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 354 DEBUG_INTR | DEBUG_XFERS); 355 356 #if NATA_DMA || NATA_PIOBM 357 if (xfer->c_flags & (C_DMA | C_PIOBM)) { 358 #if NATA_DMA 359 if (drvp->n_xfers <= NXFER) 360 drvp->n_xfers++; 361 #endif 362 dma_flags = (ata_bio->flags & ATA_READ) ? WDC_DMA_READ : 0; 363 if (ata_bio->flags & ATA_LBA48) 364 dma_flags |= WDC_DMA_LBA48; 365 } 366 #endif 367 /* 368 * 369 * When starting a multi-sector transfer, or doing single-sector 370 * transfers... 371 */ 372 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 373 if (ata_bio->flags & ATA_SINGLE) 374 nblks = 1; 375 else 376 nblks = xfer->c_bcount / drvp->lp->d_secsize; 377 /* Check for bad sectors and adjust transfer, if necessary. */ 378 if ((drvp->lp->d_flags & D_BADSECT) != 0) { 379 long blkdiff; 380 int i; 381 for (i = 0; (blkdiff = drvp->badsect[i]) != -1; 382 i++) { 383 blkdiff -= ata_bio->blkno; 384 if (blkdiff < 0) 385 continue; 386 if (blkdiff == 0) { 387 /* Replace current block of transfer. */ 388 ata_bio->blkno = 389 drvp->lp->d_secperunit - 390 drvp->lp->d_nsectors - i - 1; 391 } 392 if (blkdiff < nblks) { 393 /* Bad block inside transfer. */ 394 ata_bio->flags |= ATA_SINGLE; 395 nblks = 1; 396 } 397 break; 398 } 399 /* Transfer is okay now. */ 400 } 401 if (ata_bio->flags & ATA_LBA48) { 402 sect = 0; 403 cyl = 0; 404 head = 0; 405 } else if (ata_bio->flags & ATA_LBA) { 406 sect = (ata_bio->blkno >> 0) & 0xff; 407 cyl = (ata_bio->blkno >> 8) & 0xffff; 408 head = (ata_bio->blkno >> 24) & 0x0f; 409 head |= WDSD_LBA; 410 } else { 411 int blkno = ata_bio->blkno; 412 sect = blkno % drvp->lp->d_nsectors; 413 sect++; /* Sectors begin with 1, not 0. */ 414 blkno /= drvp->lp->d_nsectors; 415 head = blkno % drvp->lp->d_ntracks; 416 blkno /= drvp->lp->d_ntracks; 417 cyl = blkno; 418 head |= WDSD_CHS; 419 } 420 #if NATA_DMA 421 if (xfer->c_flags & C_DMA) { 422 uint16_t count = nblks, features = 0; 423 424 ata_bio->nblks = nblks; 425 ata_bio->nbytes = xfer->c_bcount; 426 cmd = (ata_bio->flags & ATA_READ) ? 427 WDCC_READDMA : WDCC_WRITEDMA; 428 /* Init the DMA channel. */ 429 error = (*wdc->dma_init)(wdc->dma_arg, 430 chp->ch_channel, xfer->c_drive, 431 (char *)xfer->c_databuf + xfer->c_skip, 432 ata_bio->nbytes, dma_flags); 433 if (error) { 434 if (error == EINVAL) { 435 /* 436 * We can't do DMA on this transfer 437 * for some reason. Fall back to 438 * PIO. 439 */ 440 xfer->c_flags &= ~C_DMA; 441 error = 0; 442 goto do_pio; 443 } 444 ata_bio->error = ERR_DMA; 445 ata_bio->r_error = 0; 446 return ATASTART_ABORT; 447 } 448 /* Initiate command */ 449 if (wdc->select) 450 wdc->select(chp, xfer->c_drive); 451 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 452 0, WDSD_IBM | (xfer->c_drive << 4)); 453 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, 454 &tfd)) { 455 case WDCWAIT_OK: 456 break; 457 case WDCWAIT_TOUT: 458 goto timeout; 459 case WDCWAIT_THR: 460 return ATASTART_TH; 461 } 462 /* start the DMA channel before */ 463 if ((chp->ch_flags & ATACH_DMA_BEFORE_CMD) != 0) 464 (*wdc->dma_start)(wdc->dma_arg, 465 chp->ch_channel, xfer->c_drive); 466 if (ata_bio->flags & ATA_LBA48) { 467 uint8_t device = WDSD_LBA; 468 cmd = atacmd_to48(cmd); 469 470 atacmd_toncq(xfer, &cmd, &count, &features, 471 &device); 472 473 wdccommandext(chp, xfer->c_drive, cmd, 474 ata_bio->blkno, count, features, device); 475 } else { 476 wdccommand(chp, xfer->c_drive, cmd, cyl, 477 head, sect, count, features); 478 } 479 /* start the DMA channel after */ 480 if ((chp->ch_flags & ATACH_DMA_BEFORE_CMD) == 0) 481 (*wdc->dma_start)(wdc->dma_arg, 482 chp->ch_channel, xfer->c_drive); 483 chp->ch_flags |= ATACH_DMA_WAIT; 484 /* start timeout machinery */ 485 if ((xfer->c_flags & C_POLL) == 0) 486 callout_reset(&chp->c_timo_callout, 487 ATA_DELAY / 1000 * hz, wdctimeout, chp); 488 /* wait for irq */ 489 goto intr; 490 } /* else not DMA */ 491 do_pio: 492 #endif /* NATA_DMA */ 493 #if NATA_PIOBM 494 if ((xfer->c_flags & C_PIOBM) && xfer->c_skip == 0) { 495 if (ata_bio->flags & ATA_POLL) { 496 /* XXX not supported yet --- fall back to PIO */ 497 xfer->c_flags &= ~C_PIOBM; 498 } else { 499 /* Init the DMA channel. */ 500 error = (*wdc->dma_init)(wdc->dma_arg, 501 chp->ch_channel, xfer->c_drive, 502 (char *)xfer->c_databuf + xfer->c_skip, 503 xfer->c_bcount, 504 dma_flags | WDC_DMA_PIOBM_ATA); 505 if (error) { 506 if (error == EINVAL) { 507 /* 508 * We can't do DMA on this 509 * transfer for some reason. 510 * Fall back to PIO. 511 */ 512 xfer->c_flags &= ~C_PIOBM; 513 error = 0; 514 } else { 515 ata_bio->error = ERR_DMA; 516 ata_bio->r_error = 0; 517 return ATASTART_ABORT; 518 } 519 } 520 } 521 } 522 #endif 523 ata_bio->nblks = uimin(nblks, drvp->multi); 524 ata_bio->nbytes = ata_bio->nblks * drvp->lp->d_secsize; 525 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 526 if (ata_bio->nblks > 1) { 527 cmd = (ata_bio->flags & ATA_READ) ? 528 WDCC_READMULTI : WDCC_WRITEMULTI; 529 } else { 530 cmd = (ata_bio->flags & ATA_READ) ? 531 WDCC_READ : WDCC_WRITE; 532 } 533 /* Initiate command! */ 534 if (wdc->select) 535 wdc->select(chp, xfer->c_drive); 536 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 537 WDSD_IBM | (xfer->c_drive << 4)); 538 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, &tfd)) { 539 case WDCWAIT_OK: 540 break; 541 case WDCWAIT_TOUT: 542 goto timeout; 543 case WDCWAIT_THR: 544 return ATASTART_TH; 545 } 546 if (ata_bio->flags & ATA_LBA48) { 547 wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd), 548 ata_bio->blkno, nblks, 0, WDSD_LBA); 549 } else { 550 wdccommand(chp, xfer->c_drive, cmd, cyl, 551 head, sect, nblks, 552 (drvp->lp->d_type == DKTYPE_ST506) ? 553 drvp->lp->d_precompcyl / 4 : 0); 554 } 555 /* start timeout machinery */ 556 if ((xfer->c_flags & C_POLL) == 0) 557 callout_reset(&chp->c_timo_callout, 558 ATA_DELAY / 1000 * hz, wdctimeout, chp); 559 } else if (ata_bio->nblks > 1) { 560 /* The number of blocks in the last stretch may be smaller. */ 561 nblks = xfer->c_bcount / drvp->lp->d_secsize; 562 if (ata_bio->nblks > nblks) { 563 ata_bio->nblks = nblks; 564 ata_bio->nbytes = xfer->c_bcount; 565 } 566 } 567 /* If this was a write and not using DMA, push the data. */ 568 if ((ata_bio->flags & ATA_READ) == 0) { 569 /* 570 * we have to busy-wait here, we can't rely on running in 571 * thread context. 572 */ 573 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL, &tfd) != 0) { 574 printf("%s:%d:%d: timeout waiting for DRQ, " 575 "st=0x%02x, err=0x%02x\n", 576 device_xname(atac->atac_dev), chp->ch_channel, 577 xfer->c_drive, 578 ATACH_ST(tfd), ATACH_ERR(tfd)); 579 if (wdc_ata_err(drvp, ata_bio, tfd) != WDC_ATA_ERR) 580 ata_bio->error = TIMEOUT; 581 return ATASTART_ABORT; 582 } 583 if (wdc_ata_err(drvp, ata_bio, tfd) == WDC_ATA_ERR) { 584 return ATASTART_ABORT; 585 } 586 #if NATA_PIOBM 587 if (xfer->c_flags & C_PIOBM) { 588 /* start the busmastering PIO */ 589 (*wdc->piobm_start)(wdc->dma_arg, 590 chp->ch_channel, xfer->c_drive, 591 xfer->c_skip, ata_bio->nbytes, 0); 592 chp->ch_flags |= ATACH_DMA_WAIT; 593 } else 594 #endif 595 596 wdc->dataout_pio(chp, drvp->drive_flags, 597 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 598 } 599 600 #if NATA_DMA 601 intr: 602 #endif 603 /* Wait for IRQ (either real or polled) */ 604 if ((ata_bio->flags & ATA_POLL) == 0) { 605 chp->ch_flags |= ATACH_IRQ_WAIT; 606 return ATASTART_STARTED; 607 } else { 608 return ATASTART_POLL; 609 } 610 611 timeout: 612 printf("%s:%d:%d: not ready, st=0x%02x, err=0x%02x\n", 613 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 614 ATACH_ST(tfd), ATACH_ERR(tfd)); 615 if (wdc_ata_err(drvp, ata_bio, tfd) != WDC_ATA_ERR) 616 ata_bio->error = TIMEOUT; 617 return ATASTART_ABORT; 618 } 619 620 static void 621 wdc_ata_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 622 { 623 /* Wait for at last 400ns for status bit to be valid */ 624 delay(1); 625 #if NATA_DMA 626 if (chp->ch_flags & ATACH_DMA_WAIT) { 627 wdc_dmawait(chp, xfer, ATA_DELAY); 628 chp->ch_flags &= ~ATACH_DMA_WAIT; 629 } 630 #endif 631 wdc_ata_bio_intr(chp, xfer, 0); 632 } 633 634 static int 635 wdc_ata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 636 { 637 struct atac_softc *atac = chp->ch_atac; 638 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 639 struct ata_bio *ata_bio = &xfer->c_bio; 640 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 641 int drv_err, tfd; 642 643 ATADEBUG_PRINT(("wdc_ata_bio_intr %s:%d:%d\n", 644 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 645 DEBUG_INTR | DEBUG_XFERS); 646 647 ata_channel_lock(chp); 648 649 /* Is it not a transfer, but a control operation? */ 650 if (drvp->state < READY) { 651 printf("%s:%d:%d: bad state %d in wdc_ata_bio_intr\n", 652 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 653 drvp->state); 654 panic("wdc_ata_bio_intr: bad state"); 655 } 656 657 /* 658 * if we missed an interrupt in a PIO transfer, reset and restart. 659 * Don't try to continue transfer, we may have missed cycles. 660 */ 661 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 662 ata_bio->error = TIMEOUT; 663 goto err; 664 } 665 666 #if NATA_PIOBM 667 /* Transfer-done interrupt for busmastering PIO read */ 668 if ((xfer->c_flags & C_PIOBM) && (chp->ch_flags & ATACH_PIOBM_WAIT)) { 669 chp->ch_flags &= ~ATACH_PIOBM_WAIT; 670 goto end; 671 } 672 #endif 673 674 /* Ack interrupt done by wdc_wait_for_unbusy */ 675 if (wdc_wait_for_unbusy(chp, 676 (irq == 0) ? ATA_DELAY : 0, AT_POLL, &tfd) < 0) { 677 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 678 ata_channel_unlock(chp); 679 return 0; /* IRQ was not for us */ 680 } 681 printf("%s:%d:%d: device timeout, c_bcount=%d, c_skip%d\n", 682 device_xname(atac->atac_dev), chp->ch_channel, 683 xfer->c_drive, xfer->c_bcount, xfer->c_skip); 684 ata_bio->error = TIMEOUT; 685 goto err; 686 } 687 if (wdc->irqack) 688 wdc->irqack(chp); 689 690 drv_err = wdc_ata_err(drvp, ata_bio, tfd); 691 692 #if NATA_DMA 693 /* If we were using DMA, Turn off the DMA channel and check for error */ 694 if (xfer->c_flags & C_DMA) { 695 if (ata_bio->flags & ATA_POLL) { 696 /* 697 * IDE drives deassert WDCS_BSY before transfer is 698 * complete when using DMA. Polling for DRQ to deassert 699 * is not enough DRQ is not required to be 700 * asserted for DMA transfers, so poll for DRDY. 701 */ 702 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 703 ATA_DELAY, ATA_POLL, &tfd) == WDCWAIT_TOUT) { 704 printf("%s:%d:%d: polled transfer timed out " 705 "(st=0x%x)\n", 706 device_xname(atac->atac_dev), 707 chp->ch_channel, xfer->c_drive, 708 ATACH_ST(tfd)); 709 ata_bio->error = TIMEOUT; 710 drv_err = WDC_ATA_ERR; 711 } 712 } 713 if (wdc->dma_status != 0) { 714 if (drv_err != WDC_ATA_ERR) { 715 ata_bio->error = ERR_DMA; 716 drv_err = WDC_ATA_ERR; 717 } 718 } 719 if (ATACH_ST(tfd) & WDCS_DRQ) { 720 if (drv_err != WDC_ATA_ERR) { 721 printf("%s:%d:%d: intr with DRQ (st=0x%x)\n", 722 device_xname(atac->atac_dev), 723 chp->ch_channel, 724 xfer->c_drive, ATACH_ST(tfd)); 725 ata_bio->error = TIMEOUT; 726 drv_err = WDC_ATA_ERR; 727 } 728 } 729 if (drv_err != WDC_ATA_ERR) 730 goto end; 731 if (ata_bio->r_error & WDCE_CRC || ata_bio->error == ERR_DMA) { 732 ata_dmaerr(drvp, 733 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 734 goto err; 735 } 736 } 737 #endif /* NATA_DMA */ 738 739 /* if we had an error, end */ 740 if (drv_err == WDC_ATA_ERR) 741 goto err; 742 743 /* If this was a read and not using DMA, fetch the data. */ 744 if ((ata_bio->flags & ATA_READ) != 0) { 745 if ((ATACH_ST(tfd) & WDCS_DRQ) != WDCS_DRQ) { 746 printf("%s:%d:%d: read intr before drq\n", 747 device_xname(atac->atac_dev), chp->ch_channel, 748 xfer->c_drive); 749 ata_bio->error = TIMEOUT; 750 goto err; 751 } 752 #if NATA_PIOBM 753 if (xfer->c_flags & C_PIOBM) { 754 /* start the busmastering PIO */ 755 (*wdc->piobm_start)(wdc->dma_arg, 756 chp->ch_channel, xfer->c_drive, 757 xfer->c_skip, ata_bio->nbytes, 758 WDC_PIOBM_XFER_IRQ); 759 chp->ch_flags |= ATACH_DMA_WAIT | ATACH_PIOBM_WAIT; 760 ata_channel_unlock(chp); 761 return 1; 762 } 763 #endif 764 wdc->datain_pio(chp, drvp->drive_flags, 765 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 766 } 767 768 #if NATA_DMA || NATA_PIOBM 769 end: 770 #endif 771 ata_bio->blkno += ata_bio->nblks; 772 ata_bio->blkdone += ata_bio->nblks; 773 xfer->c_skip += ata_bio->nbytes; 774 xfer->c_bcount -= ata_bio->nbytes; 775 776 /* See if this transfer is complete. */ 777 if (xfer->c_bcount > 0) { 778 if ((ata_bio->flags & ATA_POLL) == 0) { 779 /* Start the next operation */ 780 ata_xfer_start(xfer); 781 } else { 782 /* Let _wdc_ata_bio_start do the loop */ 783 } 784 ata_channel_unlock(chp); 785 return 1; 786 } 787 788 /* Done with this transfer */ 789 ata_bio->error = NOERROR; 790 err: ata_channel_unlock(chp); 791 wdc_ata_bio_done(chp, xfer); 792 return 1; 793 } 794 795 static void 796 wdc_ata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 797 int reason) 798 { 799 struct ata_bio *ata_bio = &xfer->c_bio; 800 int drive = xfer->c_drive; 801 bool deactivate = true; 802 803 ata_bio->flags |= ATA_ITSDONE; 804 switch (reason) { 805 case KILL_GONE_INACTIVE: 806 deactivate = false; 807 /* FALLTHROUGH */ 808 case KILL_GONE: 809 ata_bio->error = ERR_NODEV; 810 break; 811 case KILL_RESET: 812 ata_bio->error = ERR_RESET; 813 break; 814 default: 815 printf("wdc_ata_bio_kill_xfer: unknown reason %d\n", 816 reason); 817 panic("wdc_ata_bio_kill_xfer"); 818 } 819 ata_bio->r_error = WDCE_ABRT; 820 821 if (deactivate) 822 ata_deactivate_xfer(chp, xfer); 823 824 ATADEBUG_PRINT(("wdc_ata_bio_kill_xfer: drv_done\n"), DEBUG_XFERS); 825 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 826 } 827 828 static void 829 wdc_ata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 830 { 831 struct ata_bio *ata_bio = &xfer->c_bio; 832 int drive = xfer->c_drive; 833 834 ATADEBUG_PRINT(("wdc_ata_bio_done %s:%d:%d: flags 0x%x\n", 835 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 836 xfer->c_drive, (u_int)xfer->c_flags), 837 DEBUG_XFERS); 838 839 if (ata_waitdrain_xfer_check(chp, xfer)) 840 return; 841 842 /* feed back residual bcount to our caller */ 843 ata_bio->bcount = xfer->c_bcount; 844 845 /* mark controller inactive and free xfer */ 846 ata_deactivate_xfer(chp, xfer); 847 848 ata_bio->flags |= ATA_ITSDONE; 849 ATADEBUG_PRINT(("wdc_ata_done: drv_done\n"), DEBUG_XFERS); 850 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 851 ATADEBUG_PRINT(("atastart from wdc_ata_done, flags 0x%x\n", 852 chp->ch_flags), DEBUG_XFERS); 853 atastart(chp); 854 } 855 856 static int 857 wdc_ata_err(struct ata_drive_datas *drvp, struct ata_bio *ata_bio, int tfd) 858 { 859 ata_bio->error = 0; 860 if (ATACH_ST(tfd) & WDCS_BSY) { 861 ata_bio->error = TIMEOUT; 862 return WDC_ATA_ERR; 863 } 864 865 if (ATACH_ST(tfd) & WDCS_DWF) { 866 ata_bio->error = ERR_DF; 867 return WDC_ATA_ERR; 868 } 869 870 if (ATACH_ST(tfd) & WDCS_ERR) { 871 ata_bio->error = ERROR; 872 ata_bio->r_error = ATACH_ERR(tfd); 873 if (ata_bio->r_error & (WDCE_BBK | WDCE_UNC | WDCE_IDNF | 874 WDCE_ABRT | WDCE_TK0NF | WDCE_AMNF)) 875 return WDC_ATA_ERR; 876 return WDC_ATA_NOERR; 877 } 878 879 if (ATACH_ST(tfd) & WDCS_CORR) 880 ata_bio->flags |= ATA_CORR; 881 return WDC_ATA_NOERR; 882 } 883 884 static int 885 wdc_ata_addref(struct ata_drive_datas *drvp) 886 { 887 struct ata_channel *chp = drvp->chnl_softc; 888 889 return (ata_addref(chp)); 890 } 891 892 static void 893 wdc_ata_delref(struct ata_drive_datas *drvp) 894 { 895 struct ata_channel *chp = drvp->chnl_softc; 896 897 ata_delref(chp); 898 } 899
Indexes created Thu Oct 23 22:10:10 GMT 2025