ata_wdc.c revision 1.110.4.3
1 /* $NetBSD: ata_wdc.c,v 1.110.4.3 2018/09/17 20:54:41 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: ata_wdc.c,v 1.110.4.3 2018/09/17 20:54:41 jdolecek Exp $"); 58 59 #include "opt_ata.h" 60 #include "opt_wdc.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/file.h> 66 #include <sys/stat.h> 67 #include <sys/buf.h> 68 #include <sys/bufq.h> 69 #include <sys/device.h> 70 #include <sys/disklabel.h> 71 #include <sys/syslog.h> 72 #include <sys/proc.h> 73 74 #include <sys/intr.h> 75 #include <sys/bus.h> 76 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 77 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 78 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 79 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 80 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 81 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 82 83 #include <dev/ata/ataconf.h> 84 #include <dev/ata/atareg.h> 85 #include <dev/ata/atavar.h> 86 #include <dev/ic/wdcreg.h> 87 #include <dev/ic/wdcvar.h> 88 89 #define DEBUG_INTR 0x01 90 #define DEBUG_XFERS 0x02 91 #define DEBUG_STATUS 0x04 92 #define DEBUG_FUNCS 0x08 93 #define DEBUG_PROBE 0x10 94 #ifdef ATADEBUG 95 extern int wdcdebug_wd_mask; /* inited in wd.c */ 96 #define ATADEBUG_PRINT(args, level) \ 97 if (wdcdebug_wd_mask & (level)) \ 98 printf args 99 #else 100 #define ATADEBUG_PRINT(args, level) 101 #endif 102 103 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 104 105 static int wdc_ata_bio(struct ata_drive_datas*, struct ata_xfer *); 106 static int wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 107 static int _wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 108 static void wdc_ata_bio_poll(struct ata_channel *,struct ata_xfer *); 109 static int wdc_ata_bio_intr(struct ata_channel *, struct ata_xfer *, 110 int); 111 static void wdc_ata_bio_kill_xfer(struct ata_channel *, 112 struct ata_xfer *, int); 113 static void wdc_ata_bio_done(struct ata_channel *, struct ata_xfer *); 114 static int wdc_ata_err(struct ata_drive_datas *, struct ata_bio *, int); 115 #define WDC_ATA_NOERR 0x00 /* Drive doesn't report an error */ 116 #define WDC_ATA_RECOV 0x01 /* There was a recovered error */ 117 #define WDC_ATA_ERR 0x02 /* Drive reports an error */ 118 static int wdc_ata_addref(struct ata_drive_datas *); 119 static void wdc_ata_delref(struct ata_drive_datas *); 120 121 const struct ata_bustype wdc_ata_bustype = { 122 SCSIPI_BUSTYPE_ATA, 123 wdc_ata_bio, 124 wdc_reset_drive, 125 wdc_reset_channel, 126 wdc_exec_command, 127 ata_get_params, 128 wdc_ata_addref, 129 wdc_ata_delref, 130 ata_kill_pending, 131 }; 132 133 static const struct ata_xfer_ops wdc_bio_xfer_ops = { 134 .c_start = wdc_ata_bio_start, 135 .c_poll = wdc_ata_bio_poll, 136 .c_abort = wdc_ata_bio_done, 137 .c_intr = wdc_ata_bio_intr, 138 .c_kill_xfer = wdc_ata_bio_kill_xfer 139 }; 140 141 /* 142 * Handle block I/O operation. Return ATACMD_COMPLETE, ATACMD_QUEUED, or 143 * ATACMD_TRY_AGAIN. Must be called at splbio(). 144 */ 145 static int 146 wdc_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 147 { 148 struct ata_channel *chp = drvp->chnl_softc; 149 struct atac_softc *atac = chp->ch_atac; 150 struct ata_bio *ata_bio = &xfer->c_bio; 151 152 if (atac->atac_cap & ATAC_CAP_NOIRQ) 153 ata_bio->flags |= ATA_POLL; 154 if (ata_bio->flags & ATA_POLL) 155 xfer->c_flags |= C_POLL; 156 #if NATA_DMA 157 if ((drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) && 158 (ata_bio->flags & ATA_SINGLE) == 0) 159 xfer->c_flags |= C_DMA; 160 #endif 161 #if NATA_DMA && NATA_PIOBM 162 else 163 #endif 164 #if NATA_PIOBM 165 if (atac->atac_cap & ATAC_CAP_PIOBM) 166 xfer->c_flags |= C_PIOBM; 167 #endif 168 xfer->c_drive = drvp->drive; 169 xfer->c_databuf = ata_bio->databuf; 170 xfer->c_bcount = ata_bio->bcount; 171 xfer->ops = &wdc_bio_xfer_ops; 172 ata_exec_xfer(chp, xfer); 173 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 174 } 175 176 static int 177 wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 178 { 179 struct atac_softc *atac = chp->ch_atac; 180 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 181 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 182 struct ata_bio *ata_bio = &xfer->c_bio; 183 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 184 int wait_flags, tfd; 185 const char *errstring; 186 #ifdef WDC_NO_IDS 187 wait_flags = AT_POLL; 188 #else 189 wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 190 #endif 191 192 ATADEBUG_PRINT(("wdc_ata_bio_start %s:%d:%d state %d drive_flags 0x%x " 193 "c_flags 0x%x ch_flags 0x%x\n", 194 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 195 drvp->state, drvp->drive_flags, xfer->c_flags, chp->ch_flags), 196 DEBUG_XFERS); 197 198 ata_channel_lock_owned(chp); 199 200 /* Do control operations specially. */ 201 if (__predict_false(drvp->state < READY)) { 202 /* 203 * Actually, we want to be careful not to mess with the control 204 * state if the device is currently busy, but we can assume 205 * that we never get to this point if that's the case. 206 */ 207 /* If it's not a polled command, we need the kernel thread */ 208 if ((xfer->c_flags & C_POLL) == 0 && 209 (chp->ch_flags & ATACH_TH_RUN) == 0) { 210 return ATASTART_TH; 211 } 212 /* 213 * disable interrupts, all commands here should be quick 214 * enough to be able to poll, and we don't go here that often 215 */ 216 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 217 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 218 wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS); 219 if (wdc->select) 220 wdc->select(chp, xfer->c_drive); 221 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 222 WDSD_IBM | (xfer->c_drive << 4)); 223 DELAY(10); 224 errstring = "wait"; 225 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 226 &tfd)) 227 goto ctrltimeout; 228 wdccommandshort(chp, xfer->c_drive, WDCC_RECAL); 229 /* Wait for at last 400ns for status bit to be valid */ 230 DELAY(1); 231 errstring = "recal"; 232 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 233 &tfd)) 234 goto ctrltimeout; 235 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 236 goto ctrlerror; 237 /* Don't try to set modes if controller can't be adjusted */ 238 if (atac->atac_set_modes == NULL) 239 goto geometry; 240 /* Also don't try if the drive didn't report its mode */ 241 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 242 goto geometry; 243 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 244 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 245 errstring = "piomode"; 246 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 247 &tfd)) 248 goto ctrltimeout; 249 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 250 goto ctrlerror; 251 #if NATA_DMA 252 #if NATA_UDMA 253 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 254 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 255 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 256 } else 257 #endif 258 if (drvp->drive_flags & ATA_DRIVE_DMA) { 259 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 260 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 261 } else { 262 goto geometry; 263 } 264 errstring = "dmamode"; 265 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 266 &tfd)) 267 goto ctrltimeout; 268 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 269 goto ctrlerror; 270 #endif /* NATA_DMA */ 271 geometry: 272 if (ata_bio->flags & ATA_LBA) 273 goto multimode; 274 wdccommand(chp, xfer->c_drive, WDCC_IDP, 275 drvp->lp->d_ncylinders, 276 drvp->lp->d_ntracks - 1, 0, drvp->lp->d_nsectors, 277 (drvp->lp->d_type == DKTYPE_ST506) ? 278 drvp->lp->d_precompcyl / 4 : 0); 279 errstring = "geometry"; 280 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 281 &tfd)) 282 goto ctrltimeout; 283 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 284 goto ctrlerror; 285 multimode: 286 if (drvp->multi == 1) 287 goto ready; 288 wdccommand(chp, xfer->c_drive, WDCC_SETMULTI, 0, 0, 0, 289 drvp->multi, 0); 290 errstring = "setmulti"; 291 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 292 &tfd)) 293 goto ctrltimeout; 294 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 295 goto ctrlerror; 296 ready: 297 drvp->state = READY; 298 /* 299 * The drive is usable now 300 */ 301 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 302 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 303 wd_aux_ctlr, WDCTL_4BIT); 304 delay(10); /* some drives need a little delay here */ 305 } 306 307 return _wdc_ata_bio_start(chp, xfer); 308 ctrltimeout: 309 printf("%s:%d:%d: %s timed out\n", 310 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 311 errstring); 312 ata_bio->error = TIMEOUT; 313 goto ctrldone; 314 ctrlerror: 315 printf("%s:%d:%d: %s ", 316 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 317 errstring); 318 if (ATACH_ST(tfd) & WDCS_DWF) { 319 printf("drive fault\n"); 320 ata_bio->error = ERR_DF; 321 } else { 322 ata_bio->r_error = ATACH_ERR(tfd); 323 ata_bio->error = ERROR; 324 printf("error (%x)\n", ata_bio->r_error); 325 } 326 ctrldone: 327 drvp->state = 0; 328 329 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 330 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 331 WDCTL_4BIT); 332 return ATASTART_ABORT; 333 } 334 335 static int 336 _wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 337 { 338 struct atac_softc *atac = chp->ch_atac; 339 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 340 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 341 struct ata_bio *ata_bio = &xfer->c_bio; 342 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 343 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 344 uint16_t cyl; 345 uint8_t head, sect, cmd = 0; 346 int nblks, tfd; 347 #if NATA_DMA || NATA_PIOBM 348 int error, dma_flags = 0; 349 #endif 350 351 ATADEBUG_PRINT(("_wdc_ata_bio_start %s:%d:%d\n", 352 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 353 DEBUG_INTR | DEBUG_XFERS); 354 355 #if NATA_DMA || NATA_PIOBM 356 if (xfer->c_flags & (C_DMA | C_PIOBM)) { 357 #if NATA_DMA 358 if (drvp->n_xfers <= NXFER) 359 drvp->n_xfers++; 360 #endif 361 dma_flags = (ata_bio->flags & ATA_READ) ? WDC_DMA_READ : 0; 362 if (ata_bio->flags & ATA_LBA48) 363 dma_flags |= WDC_DMA_LBA48; 364 } 365 #endif 366 /* 367 * 368 * When starting a multi-sector transfer, or doing single-sector 369 * transfers... 370 */ 371 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 372 if (ata_bio->flags & ATA_SINGLE) 373 nblks = 1; 374 else 375 nblks = xfer->c_bcount / drvp->lp->d_secsize; 376 /* Check for bad sectors and adjust transfer, if necessary. */ 377 if ((drvp->lp->d_flags & D_BADSECT) != 0) { 378 long blkdiff; 379 int i; 380 for (i = 0; (blkdiff = drvp->badsect[i]) != -1; 381 i++) { 382 blkdiff -= ata_bio->blkno; 383 if (blkdiff < 0) 384 continue; 385 if (blkdiff == 0) { 386 /* Replace current block of transfer. */ 387 ata_bio->blkno = 388 drvp->lp->d_secperunit - 389 drvp->lp->d_nsectors - i - 1; 390 } 391 if (blkdiff < nblks) { 392 /* Bad block inside transfer. */ 393 ata_bio->flags |= ATA_SINGLE; 394 nblks = 1; 395 } 396 break; 397 } 398 /* Transfer is okay now. */ 399 } 400 if (ata_bio->flags & ATA_LBA48) { 401 sect = 0; 402 cyl = 0; 403 head = 0; 404 } else if (ata_bio->flags & ATA_LBA) { 405 sect = (ata_bio->blkno >> 0) & 0xff; 406 cyl = (ata_bio->blkno >> 8) & 0xffff; 407 head = (ata_bio->blkno >> 24) & 0x0f; 408 head |= WDSD_LBA; 409 } else { 410 int blkno = ata_bio->blkno; 411 sect = blkno % drvp->lp->d_nsectors; 412 sect++; /* Sectors begin with 1, not 0. */ 413 blkno /= drvp->lp->d_nsectors; 414 head = blkno % drvp->lp->d_ntracks; 415 blkno /= drvp->lp->d_ntracks; 416 cyl = blkno; 417 head |= WDSD_CHS; 418 } 419 #if NATA_DMA 420 if (xfer->c_flags & C_DMA) { 421 uint16_t count = nblks, features = 0; 422 423 ata_bio->nblks = nblks; 424 ata_bio->nbytes = xfer->c_bcount; 425 cmd = (ata_bio->flags & ATA_READ) ? 426 WDCC_READDMA : WDCC_WRITEDMA; 427 /* Init the DMA channel. */ 428 error = (*wdc->dma_init)(wdc->dma_arg, 429 chp->ch_channel, xfer->c_drive, 430 (char *)xfer->c_databuf + xfer->c_skip, 431 ata_bio->nbytes, dma_flags); 432 if (error) { 433 if (error == EINVAL) { 434 /* 435 * We can't do DMA on this transfer 436 * for some reason. Fall back to 437 * PIO. 438 */ 439 xfer->c_flags &= ~C_DMA; 440 error = 0; 441 goto do_pio; 442 } 443 ata_bio->error = ERR_DMA; 444 ata_bio->r_error = 0; 445 return ATASTART_ABORT; 446 } 447 /* Initiate command */ 448 if (wdc->select) 449 wdc->select(chp, xfer->c_drive); 450 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 451 0, WDSD_IBM | (xfer->c_drive << 4)); 452 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, 453 &tfd)) { 454 case WDCWAIT_OK: 455 break; 456 case WDCWAIT_TOUT: 457 goto timeout; 458 case WDCWAIT_THR: 459 return ATASTART_TH; 460 } 461 /* start the DMA channel before */ 462 if ((chp->ch_flags & ATACH_DMA_BEFORE_CMD) != 0) 463 (*wdc->dma_start)(wdc->dma_arg, 464 chp->ch_channel, xfer->c_drive); 465 if (ata_bio->flags & ATA_LBA48) { 466 uint8_t device = WDSD_LBA; 467 cmd = atacmd_to48(cmd); 468 469 atacmd_toncq(xfer, &cmd, &count, &features, 470 &device); 471 472 wdccommandext(chp, xfer->c_drive, cmd, 473 ata_bio->blkno, count, features, device); 474 } else { 475 wdccommand(chp, xfer->c_drive, cmd, cyl, 476 head, sect, count, features); 477 } 478 /* start the DMA channel after */ 479 if ((chp->ch_flags & ATACH_DMA_BEFORE_CMD) == 0) 480 (*wdc->dma_start)(wdc->dma_arg, 481 chp->ch_channel, xfer->c_drive); 482 chp->ch_flags |= ATACH_DMA_WAIT; 483 /* start timeout machinery */ 484 if ((xfer->c_flags & C_POLL) == 0) 485 callout_reset(&chp->c_timo_callout, 486 ATA_DELAY / 1000 * hz, wdctimeout, chp); 487 /* wait for irq */ 488 goto intr; 489 } /* else not DMA */ 490 do_pio: 491 #endif /* NATA_DMA */ 492 #if NATA_PIOBM 493 if ((xfer->c_flags & C_PIOBM) && xfer->c_skip == 0) { 494 if (ata_bio->flags & ATA_POLL) { 495 /* XXX not supported yet --- fall back to PIO */ 496 xfer->c_flags &= ~C_PIOBM; 497 } else { 498 /* Init the DMA channel. */ 499 error = (*wdc->dma_init)(wdc->dma_arg, 500 chp->ch_channel, xfer->c_drive, 501 (char *)xfer->c_databuf + xfer->c_skip, 502 xfer->c_bcount, 503 dma_flags | WDC_DMA_PIOBM_ATA); 504 if (error) { 505 if (error == EINVAL) { 506 /* 507 * We can't do DMA on this 508 * transfer for some reason. 509 * Fall back to PIO. 510 */ 511 xfer->c_flags &= ~C_PIOBM; 512 error = 0; 513 } else { 514 ata_bio->error = ERR_DMA; 515 ata_bio->r_error = 0; 516 return ATASTART_ABORT; 517 } 518 } 519 } 520 } 521 #endif 522 ata_bio->nblks = min(nblks, drvp->multi); 523 ata_bio->nbytes = ata_bio->nblks * drvp->lp->d_secsize; 524 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 525 if (ata_bio->nblks > 1) { 526 cmd = (ata_bio->flags & ATA_READ) ? 527 WDCC_READMULTI : WDCC_WRITEMULTI; 528 } else { 529 cmd = (ata_bio->flags & ATA_READ) ? 530 WDCC_READ : WDCC_WRITE; 531 } 532 /* Initiate command! */ 533 if (wdc->select) 534 wdc->select(chp, xfer->c_drive); 535 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 536 WDSD_IBM | (xfer->c_drive << 4)); 537 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, &tfd)) { 538 case WDCWAIT_OK: 539 break; 540 case WDCWAIT_TOUT: 541 goto timeout; 542 case WDCWAIT_THR: 543 return ATASTART_TH; 544 } 545 if (ata_bio->flags & ATA_LBA48) { 546 wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd), 547 ata_bio->blkno, nblks, 0, WDSD_LBA); 548 } else { 549 wdccommand(chp, xfer->c_drive, cmd, cyl, 550 head, sect, nblks, 551 (drvp->lp->d_type == DKTYPE_ST506) ? 552 drvp->lp->d_precompcyl / 4 : 0); 553 } 554 /* start timeout machinery */ 555 if ((xfer->c_flags & C_POLL) == 0) 556 callout_reset(&chp->c_timo_callout, 557 ATA_DELAY / 1000 * hz, wdctimeout, chp); 558 } else if (ata_bio->nblks > 1) { 559 /* The number of blocks in the last stretch may be smaller. */ 560 nblks = xfer->c_bcount / drvp->lp->d_secsize; 561 if (ata_bio->nblks > nblks) { 562 ata_bio->nblks = nblks; 563 ata_bio->nbytes = xfer->c_bcount; 564 } 565 } 566 /* If this was a write and not using DMA, push the data. */ 567 if ((ata_bio->flags & ATA_READ) == 0) { 568 /* 569 * we have to busy-wait here, we can't rely on running in 570 * thread context. 571 */ 572 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL, &tfd) != 0) { 573 printf("%s:%d:%d: timeout waiting for DRQ, " 574 "st=0x%02x, err=0x%02x\n", 575 device_xname(atac->atac_dev), chp->ch_channel, 576 xfer->c_drive, 577 ATACH_ST(tfd), ATACH_ERR(tfd)); 578 if (wdc_ata_err(drvp, ata_bio, tfd) != WDC_ATA_ERR) 579 ata_bio->error = TIMEOUT; 580 return ATASTART_ABORT; 581 } 582 if (wdc_ata_err(drvp, ata_bio, tfd) == WDC_ATA_ERR) { 583 return ATASTART_ABORT; 584 } 585 #if NATA_PIOBM 586 if (xfer->c_flags & C_PIOBM) { 587 /* start the busmastering PIO */ 588 (*wdc->piobm_start)(wdc->dma_arg, 589 chp->ch_channel, xfer->c_drive, 590 xfer->c_skip, ata_bio->nbytes, 0); 591 chp->ch_flags |= ATACH_DMA_WAIT; 592 } else 593 #endif 594 595 wdc->dataout_pio(chp, drvp->drive_flags, 596 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 597 } 598 599 #if NATA_DMA 600 intr: 601 #endif 602 /* Wait for IRQ (either real or polled) */ 603 if ((ata_bio->flags & ATA_POLL) == 0) { 604 chp->ch_flags |= ATACH_IRQ_WAIT; 605 return ATASTART_STARTED; 606 } else { 607 return ATASTART_POLL; 608 } 609 610 timeout: 611 printf("%s:%d:%d: not ready, st=0x%02x, err=0x%02x\n", 612 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 613 ATACH_ST(tfd), ATACH_ERR(tfd)); 614 if (wdc_ata_err(drvp, ata_bio, tfd) != WDC_ATA_ERR) 615 ata_bio->error = TIMEOUT; 616 return ATASTART_ABORT; 617 } 618 619 static void 620 wdc_ata_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 621 { 622 /* Wait for at last 400ns for status bit to be valid */ 623 delay(1); 624 #if NATA_DMA 625 if (chp->ch_flags & ATACH_DMA_WAIT) { 626 wdc_dmawait(chp, xfer, ATA_DELAY); 627 chp->ch_flags &= ~ATACH_DMA_WAIT; 628 } 629 #endif 630 wdc_ata_bio_intr(chp, xfer, 0); 631 } 632 633 static int 634 wdc_ata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 635 { 636 struct atac_softc *atac = chp->ch_atac; 637 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 638 struct ata_bio *ata_bio = &xfer->c_bio; 639 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 640 int drv_err, tfd; 641 642 ATADEBUG_PRINT(("wdc_ata_bio_intr %s:%d:%d\n", 643 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 644 DEBUG_INTR | DEBUG_XFERS); 645 646 ata_channel_lock(chp); 647 648 /* Is it not a transfer, but a control operation? */ 649 if (drvp->state < READY) { 650 printf("%s:%d:%d: bad state %d in wdc_ata_bio_intr\n", 651 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 652 drvp->state); 653 panic("wdc_ata_bio_intr: bad state"); 654 } 655 656 /* 657 * if we missed an interrupt in a PIO transfer, reset and restart. 658 * Don't try to continue transfer, we may have missed cycles. 659 */ 660 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 661 ata_bio->error = TIMEOUT; 662 goto err; 663 } 664 665 #if NATA_PIOBM 666 /* Transfer-done interrupt for busmastering PIO read */ 667 if ((xfer->c_flags & C_PIOBM) && (chp->ch_flags & ATACH_PIOBM_WAIT)) { 668 chp->ch_flags &= ~ATACH_PIOBM_WAIT; 669 goto end; 670 } 671 #endif 672 673 /* Ack interrupt done by wdc_wait_for_unbusy */ 674 if (wdc_wait_for_unbusy(chp, 675 (irq == 0) ? ATA_DELAY : 0, AT_POLL, &tfd) < 0) { 676 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 677 ata_channel_unlock(chp); 678 return 0; /* IRQ was not for us */ 679 } 680 printf("%s:%d:%d: device timeout, c_bcount=%d, c_skip%d\n", 681 device_xname(atac->atac_dev), chp->ch_channel, 682 xfer->c_drive, xfer->c_bcount, xfer->c_skip); 683 ata_bio->error = TIMEOUT; 684 goto err; 685 } 686 if (wdc->irqack) 687 wdc->irqack(chp); 688 689 drv_err = wdc_ata_err(drvp, ata_bio, tfd); 690 691 #if NATA_DMA 692 /* If we were using DMA, Turn off the DMA channel and check for error */ 693 if (xfer->c_flags & C_DMA) { 694 if (ata_bio->flags & ATA_POLL) { 695 /* 696 * IDE drives deassert WDCS_BSY before transfer is 697 * complete when using DMA. Polling for DRQ to deassert 698 * is not enough DRQ is not required to be 699 * asserted for DMA transfers, so poll for DRDY. 700 */ 701 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 702 ATA_DELAY, ATA_POLL, &tfd) == WDCWAIT_TOUT) { 703 printf("%s:%d:%d: polled transfer timed out " 704 "(st=0x%x)\n", 705 device_xname(atac->atac_dev), 706 chp->ch_channel, xfer->c_drive, 707 ATACH_ST(tfd)); 708 ata_bio->error = TIMEOUT; 709 drv_err = WDC_ATA_ERR; 710 } 711 } 712 if (wdc->dma_status != 0) { 713 if (drv_err != WDC_ATA_ERR) { 714 ata_bio->error = ERR_DMA; 715 drv_err = WDC_ATA_ERR; 716 } 717 } 718 if (ATACH_ST(tfd) & WDCS_DRQ) { 719 if (drv_err != WDC_ATA_ERR) { 720 printf("%s:%d:%d: intr with DRQ (st=0x%x)\n", 721 device_xname(atac->atac_dev), 722 chp->ch_channel, 723 xfer->c_drive, ATACH_ST(tfd)); 724 ata_bio->error = TIMEOUT; 725 drv_err = WDC_ATA_ERR; 726 } 727 } 728 if (drv_err != WDC_ATA_ERR) 729 goto end; 730 if (ata_bio->r_error & WDCE_CRC || ata_bio->error == ERR_DMA) { 731 ata_channel_unlock(chp); 732 ata_dmaerr(drvp, 733 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 734 ata_channel_lock(chp); 735 goto err; 736 } 737 } 738 #endif /* NATA_DMA */ 739 740 /* if we had an error, end */ 741 if (drv_err == WDC_ATA_ERR) 742 goto err; 743 744 /* If this was a read and not using DMA, fetch the data. */ 745 if ((ata_bio->flags & ATA_READ) != 0) { 746 if ((ATACH_ST(tfd) & WDCS_DRQ) != WDCS_DRQ) { 747 printf("%s:%d:%d: read intr before drq\n", 748 device_xname(atac->atac_dev), chp->ch_channel, 749 xfer->c_drive); 750 ata_bio->error = TIMEOUT; 751 goto err; 752 } 753 #if NATA_PIOBM 754 if (xfer->c_flags & C_PIOBM) { 755 /* start the busmastering PIO */ 756 (*wdc->piobm_start)(wdc->dma_arg, 757 chp->ch_channel, xfer->c_drive, 758 xfer->c_skip, ata_bio->nbytes, 759 WDC_PIOBM_XFER_IRQ); 760 chp->ch_flags |= ATACH_DMA_WAIT | ATACH_PIOBM_WAIT; 761 ata_channel_unlock(chp); 762 return 1; 763 } 764 #endif 765 wdc->datain_pio(chp, drvp->drive_flags, 766 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 767 } 768 769 #if NATA_DMA || NATA_PIOBM 770 end: 771 #endif 772 ata_bio->blkno += ata_bio->nblks; 773 ata_bio->blkdone += ata_bio->nblks; 774 xfer->c_skip += ata_bio->nbytes; 775 xfer->c_bcount -= ata_bio->nbytes; 776 777 /* See if this transfer is complete. */ 778 if (xfer->c_bcount > 0) { 779 if ((ata_bio->flags & ATA_POLL) == 0) { 780 /* Start the next operation */ 781 ata_xfer_start(xfer); 782 } else { 783 /* Let _wdc_ata_bio_start do the loop */ 784 } 785 ata_channel_unlock(chp); 786 return 1; 787 } 788 789 /* Done with this transfer */ 790 ata_bio->error = NOERROR; 791 err: ata_channel_unlock(chp); 792 wdc_ata_bio_done(chp, xfer); 793 return 1; 794 } 795 796 static void 797 wdc_ata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 798 int reason) 799 { 800 struct ata_bio *ata_bio = &xfer->c_bio; 801 int drive = xfer->c_drive; 802 bool deactivate = true; 803 804 ata_bio->flags |= ATA_ITSDONE; 805 switch (reason) { 806 case KILL_GONE_INACTIVE: 807 deactivate = false; 808 /* FALLTHROUGH */ 809 case KILL_GONE: 810 ata_bio->error = ERR_NODEV; 811 break; 812 case KILL_RESET: 813 ata_bio->error = ERR_RESET; 814 break; 815 default: 816 printf("wdc_ata_bio_kill_xfer: unknown reason %d\n", 817 reason); 818 panic("wdc_ata_bio_kill_xfer"); 819 } 820 ata_bio->r_error = WDCE_ABRT; 821 822 if (deactivate) 823 ata_deactivate_xfer(chp, xfer); 824 825 ATADEBUG_PRINT(("wdc_ata_bio_kill_xfer: drv_done\n"), DEBUG_XFERS); 826 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 827 } 828 829 static void 830 wdc_ata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 831 { 832 struct ata_bio *ata_bio = &xfer->c_bio; 833 int drive = xfer->c_drive; 834 835 ATADEBUG_PRINT(("wdc_ata_bio_done %s:%d:%d: flags 0x%x\n", 836 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 837 xfer->c_drive, (u_int)xfer->c_flags), 838 DEBUG_XFERS); 839 840 if (ata_waitdrain_xfer_check(chp, xfer)) 841 return; 842 843 /* feed back residual bcount to our caller */ 844 ata_bio->bcount = xfer->c_bcount; 845 846 /* mark controller inactive and free xfer */ 847 ata_deactivate_xfer(chp, xfer); 848 849 ata_bio->flags |= ATA_ITSDONE; 850 ATADEBUG_PRINT(("wdc_ata_done: drv_done\n"), DEBUG_XFERS); 851 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 852 ATADEBUG_PRINT(("atastart from wdc_ata_done, flags 0x%x\n", 853 chp->ch_flags), DEBUG_XFERS); 854 atastart(chp); 855 } 856 857 static int 858 wdc_ata_err(struct ata_drive_datas *drvp, struct ata_bio *ata_bio, int tfd) 859 { 860 ata_bio->error = 0; 861 if (ATACH_ST(tfd) & WDCS_BSY) { 862 ata_bio->error = TIMEOUT; 863 return WDC_ATA_ERR; 864 } 865 866 if (ATACH_ST(tfd) & WDCS_DWF) { 867 ata_bio->error = ERR_DF; 868 return WDC_ATA_ERR; 869 } 870 871 if (ATACH_ST(tfd) & WDCS_ERR) { 872 ata_bio->error = ERROR; 873 ata_bio->r_error = ATACH_ERR(tfd); 874 if (ata_bio->r_error & (WDCE_BBK | WDCE_UNC | WDCE_IDNF | 875 WDCE_ABRT | WDCE_TK0NF | WDCE_AMNF)) 876 return WDC_ATA_ERR; 877 return WDC_ATA_NOERR; 878 } 879 880 if (ATACH_ST(tfd) & WDCS_CORR) 881 ata_bio->flags |= ATA_CORR; 882 return WDC_ATA_NOERR; 883 } 884 885 static int 886 wdc_ata_addref(struct ata_drive_datas *drvp) 887 { 888 struct ata_channel *chp = drvp->chnl_softc; 889 890 return (ata_addref(chp)); 891 } 892 893 static void 894 wdc_ata_delref(struct ata_drive_datas *drvp) 895 { 896 struct ata_channel *chp = drvp->chnl_softc; 897 898 ata_delref(chp); 899 } 900
Indexes created Sat Oct 25 16:10:12 GMT 2025