ata_wdc.c revision 1.113.4.1
1 /* $NetBSD: ata_wdc.c,v 1.113.4.1 2022/12/30 14:39:10 martin Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: ata_wdc.c,v 1.113.4.1 2022/12/30 14:39:10 martin Exp $"); 58 59 #include "opt_ata.h" 60 #include "opt_wdc.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/file.h> 66 #include <sys/stat.h> 67 #include <sys/buf.h> 68 #include <sys/bufq.h> 69 #include <sys/device.h> 70 #include <sys/disklabel.h> 71 #include <sys/syslog.h> 72 #include <sys/proc.h> 73 74 #include <sys/intr.h> 75 #include <sys/bus.h> 76 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 77 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 78 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 79 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 80 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 81 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 82 83 #include <dev/ata/ataconf.h> 84 #include <dev/ata/atareg.h> 85 #include <dev/ata/atavar.h> 86 #include <dev/ic/wdcreg.h> 87 #include <dev/ic/wdcvar.h> 88 89 #define DEBUG_INTR 0x01 90 #define DEBUG_XFERS 0x02 91 #define DEBUG_STATUS 0x04 92 #define DEBUG_FUNCS 0x08 93 #define DEBUG_PROBE 0x10 94 #ifdef ATADEBUG 95 extern int wdcdebug_wd_mask; /* inited in wd.c */ 96 #define ATADEBUG_PRINT(args, level) \ 97 if (wdcdebug_wd_mask & (level)) \ 98 printf args 99 #else 100 #define ATADEBUG_PRINT(args, level) 101 #endif 102 103 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 104 105 static void wdc_ata_bio(struct ata_drive_datas*, struct ata_xfer *); 106 static int wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 107 static int _wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 108 static int wdc_ata_bio_poll(struct ata_channel *,struct ata_xfer *); 109 static int wdc_ata_bio_intr(struct ata_channel *, struct ata_xfer *, 110 int); 111 static void wdc_ata_bio_kill_xfer(struct ata_channel *, 112 struct ata_xfer *, int); 113 static void wdc_ata_bio_done(struct ata_channel *, struct ata_xfer *); 114 static int wdc_ata_err(struct ata_drive_datas *, struct ata_bio *, int); 115 #define WDC_ATA_NOERR 0x00 /* Drive doesn't report an error */ 116 #define WDC_ATA_RECOV 0x01 /* There was a recovered error */ 117 #define WDC_ATA_ERR 0x02 /* Drive reports an error */ 118 static int wdc_ata_addref(struct ata_drive_datas *); 119 static void wdc_ata_delref(struct ata_drive_datas *); 120 121 const struct ata_bustype wdc_ata_bustype = { 122 SCSIPI_BUSTYPE_ATA, 123 wdc_ata_bio, 124 wdc_reset_drive, 125 wdc_reset_channel, 126 wdc_exec_command, 127 ata_get_params, 128 wdc_ata_addref, 129 wdc_ata_delref, 130 ata_kill_pending, 131 NULL, 132 }; 133 134 static const struct ata_xfer_ops wdc_bio_xfer_ops = { 135 .c_start = wdc_ata_bio_start, 136 .c_poll = wdc_ata_bio_poll, 137 .c_abort = wdc_ata_bio_done, 138 .c_intr = wdc_ata_bio_intr, 139 .c_kill_xfer = wdc_ata_bio_kill_xfer 140 }; 141 142 /* 143 * Handle block I/O operation. 144 */ 145 static void 146 wdc_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 147 { 148 struct ata_channel *chp = drvp->chnl_softc; 149 struct atac_softc *atac = chp->ch_atac; 150 struct ata_bio *ata_bio = &xfer->c_bio; 151 152 if (atac->atac_cap & ATAC_CAP_NOIRQ) 153 ata_bio->flags |= ATA_POLL; 154 if (ata_bio->flags & ATA_POLL) 155 xfer->c_flags |= C_POLL; 156 #if NATA_DMA 157 if ((drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) && 158 (ata_bio->flags & ATA_SINGLE) == 0) 159 xfer->c_flags |= C_DMA; 160 #endif 161 #if NATA_DMA && NATA_PIOBM 162 else 163 #endif 164 #if NATA_PIOBM 165 if (atac->atac_cap & ATAC_CAP_PIOBM) 166 xfer->c_flags |= C_PIOBM; 167 #endif 168 xfer->c_drive = drvp->drive; 169 xfer->c_databuf = ata_bio->databuf; 170 xfer->c_bcount = ata_bio->bcount; 171 xfer->ops = &wdc_bio_xfer_ops; 172 ata_exec_xfer(chp, xfer); 173 } 174 175 static int 176 wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 177 { 178 struct atac_softc *atac = chp->ch_atac; 179 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 180 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 181 struct ata_bio *ata_bio = &xfer->c_bio; 182 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 183 int wait_flags, tfd; 184 const char *errstring; 185 #ifdef WDC_NO_IDS 186 wait_flags = AT_POLL; 187 #else 188 wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 189 #endif 190 191 ATADEBUG_PRINT(("wdc_ata_bio_start %s:%d:%d state %d drive_flags 0x%x " 192 "c_flags 0x%x ch_flags 0x%x\n", 193 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 194 drvp->state, drvp->drive_flags, xfer->c_flags, chp->ch_flags), 195 DEBUG_XFERS); 196 197 ata_channel_lock_owned(chp); 198 199 /* Do control operations specially. */ 200 if (__predict_false(drvp->state < READY)) { 201 /* 202 * Actually, we want to be careful not to mess with the control 203 * state if the device is currently busy, but we can assume 204 * that we never get to this point if that's the case. 205 */ 206 /* If it's not a polled command, we need the kernel thread */ 207 if ((xfer->c_flags & C_POLL) == 0 && 208 (chp->ch_flags & ATACH_TH_RUN) == 0) { 209 return ATASTART_TH; 210 } 211 /* 212 * disable interrupts, all commands here should be quick 213 * enough to be able to poll, and we don't go here that often 214 */ 215 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 216 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 217 wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS); 218 if (wdc->select) 219 wdc->select(chp, xfer->c_drive); 220 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 221 WDSD_IBM | (xfer->c_drive << 4)); 222 DELAY(10); 223 errstring = "wait"; 224 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 225 &tfd)) 226 goto ctrltimeout; 227 wdccommandshort(chp, xfer->c_drive, WDCC_RECAL); 228 /* Wait for at last 400ns for status bit to be valid */ 229 DELAY(1); 230 errstring = "recal"; 231 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 232 &tfd)) 233 goto ctrltimeout; 234 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 235 goto ctrlerror; 236 /* Don't try to set modes if controller can't be adjusted */ 237 if (atac->atac_set_modes == NULL) 238 goto geometry; 239 /* Also don't try if the drive didn't report its mode */ 240 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 241 goto geometry; 242 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 243 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 244 errstring = "piomode"; 245 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 246 &tfd)) 247 goto ctrltimeout; 248 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 249 goto ctrlerror; 250 #if NATA_DMA 251 #if NATA_UDMA 252 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 253 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 254 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 255 } else 256 #endif 257 if (drvp->drive_flags & ATA_DRIVE_DMA) { 258 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 259 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 260 } else { 261 goto geometry; 262 } 263 errstring = "dmamode"; 264 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 265 &tfd)) 266 goto ctrltimeout; 267 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 268 goto ctrlerror; 269 #endif /* NATA_DMA */ 270 geometry: 271 if (ata_bio->flags & ATA_LBA) 272 goto multimode; 273 wdccommand(chp, xfer->c_drive, WDCC_IDP, 274 drvp->lp->d_ncylinders, 275 drvp->lp->d_ntracks - 1, 0, drvp->lp->d_nsectors, 276 (drvp->lp->d_type == DKTYPE_ST506) ? 277 drvp->lp->d_precompcyl / 4 : 0); 278 errstring = "geometry"; 279 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 280 &tfd)) 281 goto ctrltimeout; 282 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 283 goto ctrlerror; 284 multimode: 285 if (drvp->multi == 1) 286 goto ready; 287 wdccommand(chp, xfer->c_drive, WDCC_SETMULTI, 0, 0, 0, 288 drvp->multi, 0); 289 errstring = "setmulti"; 290 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 291 &tfd)) 292 goto ctrltimeout; 293 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 294 goto ctrlerror; 295 ready: 296 drvp->state = READY; 297 /* 298 * The drive is usable now 299 */ 300 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 301 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 302 wd_aux_ctlr, WDCTL_4BIT); 303 delay(10); /* some drives need a little delay here */ 304 } 305 306 return _wdc_ata_bio_start(chp, xfer); 307 ctrltimeout: 308 printf("%s:%d:%d: %s timed out\n", 309 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 310 errstring); 311 ata_bio->error = TIMEOUT; 312 goto ctrldone; 313 ctrlerror: 314 printf("%s:%d:%d: %s ", 315 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 316 errstring); 317 if (ATACH_ST(tfd) & WDCS_DWF) { 318 printf("drive fault\n"); 319 ata_bio->error = ERR_DF; 320 } else { 321 ata_bio->r_error = ATACH_ERR(tfd); 322 ata_bio->error = ERROR; 323 printf("error (%x)\n", ata_bio->r_error); 324 } 325 ctrldone: 326 drvp->state = 0; 327 328 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 329 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 330 WDCTL_4BIT); 331 return ATASTART_ABORT; 332 } 333 334 static int 335 _wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 336 { 337 struct atac_softc *atac = chp->ch_atac; 338 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 339 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 340 struct ata_bio *ata_bio = &xfer->c_bio; 341 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 342 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 343 uint16_t cyl; 344 uint8_t head, sect, cmd = 0; 345 int nblks, tfd; 346 #if NATA_DMA || NATA_PIOBM 347 int error, dma_flags = 0; 348 #endif 349 350 ATADEBUG_PRINT(("_wdc_ata_bio_start %s:%d:%d\n", 351 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 352 DEBUG_INTR | DEBUG_XFERS); 353 354 #if NATA_DMA || NATA_PIOBM 355 if (xfer->c_flags & (C_DMA | C_PIOBM)) { 356 #if NATA_DMA 357 if (drvp->n_xfers <= NXFER) 358 drvp->n_xfers++; 359 #endif 360 dma_flags = (ata_bio->flags & ATA_READ) ? WDC_DMA_READ : 0; 361 if (ata_bio->flags & ATA_LBA48) 362 dma_flags |= WDC_DMA_LBA48; 363 } 364 #endif 365 /* 366 * 367 * When starting a multi-sector transfer, or doing single-sector 368 * transfers... 369 */ 370 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 371 if (ata_bio->flags & ATA_SINGLE) 372 nblks = 1; 373 else 374 nblks = xfer->c_bcount / drvp->lp->d_secsize; 375 /* Check for bad sectors and adjust transfer, if necessary. */ 376 if ((drvp->lp->d_flags & D_BADSECT) != 0) { 377 long blkdiff; 378 int i; 379 for (i = 0; (blkdiff = drvp->badsect[i]) != -1; 380 i++) { 381 blkdiff -= ata_bio->blkno; 382 if (blkdiff < 0) 383 continue; 384 if (blkdiff == 0) { 385 /* Replace current block of transfer. */ 386 ata_bio->blkno = 387 drvp->lp->d_secperunit - 388 drvp->lp->d_nsectors - i - 1; 389 } 390 if (blkdiff < nblks) { 391 /* Bad block inside transfer. */ 392 ata_bio->flags |= ATA_SINGLE; 393 nblks = 1; 394 } 395 break; 396 } 397 /* Transfer is okay now. */ 398 } 399 if (ata_bio->flags & ATA_LBA48) { 400 sect = 0; 401 cyl = 0; 402 head = 0; 403 } else if (ata_bio->flags & ATA_LBA) { 404 sect = (ata_bio->blkno >> 0) & 0xff; 405 cyl = (ata_bio->blkno >> 8) & 0xffff; 406 head = (ata_bio->blkno >> 24) & 0x0f; 407 head |= WDSD_LBA; 408 } else { 409 int blkno = ata_bio->blkno; 410 sect = blkno % drvp->lp->d_nsectors; 411 sect++; /* Sectors begin with 1, not 0. */ 412 blkno /= drvp->lp->d_nsectors; 413 head = blkno % drvp->lp->d_ntracks; 414 blkno /= drvp->lp->d_ntracks; 415 cyl = blkno; 416 head |= WDSD_CHS; 417 } 418 #if NATA_DMA 419 if (xfer->c_flags & C_DMA) { 420 uint16_t count = nblks, features = 0; 421 422 ata_bio->nblks = nblks; 423 ata_bio->nbytes = xfer->c_bcount; 424 cmd = (ata_bio->flags & ATA_READ) ? 425 WDCC_READDMA : WDCC_WRITEDMA; 426 /* Init the DMA channel. */ 427 error = (*wdc->dma_init)(wdc->dma_arg, 428 chp->ch_channel, xfer->c_drive, 429 (char *)xfer->c_databuf + xfer->c_skip, 430 ata_bio->nbytes, dma_flags); 431 if (error) { 432 if (error == EINVAL) { 433 /* 434 * We can't do DMA on this transfer 435 * for some reason. Fall back to 436 * PIO. 437 */ 438 xfer->c_flags &= ~C_DMA; 439 error = 0; 440 goto do_pio; 441 } 442 ata_bio->error = ERR_DMA; 443 ata_bio->r_error = 0; 444 return ATASTART_ABORT; 445 } 446 /* Initiate command */ 447 if (wdc->select) 448 wdc->select(chp, xfer->c_drive); 449 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 450 0, WDSD_IBM | (xfer->c_drive << 4)); 451 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, 452 &tfd)) { 453 case WDCWAIT_OK: 454 break; 455 case WDCWAIT_TOUT: 456 goto timeout; 457 case WDCWAIT_THR: 458 return ATASTART_TH; 459 } 460 /* start the DMA channel before */ 461 if ((chp->ch_flags & ATACH_DMA_BEFORE_CMD) != 0) 462 (*wdc->dma_start)(wdc->dma_arg, 463 chp->ch_channel, xfer->c_drive); 464 if (ata_bio->flags & ATA_LBA48) { 465 uint8_t device = WDSD_LBA; 466 cmd = atacmd_to48(cmd); 467 468 atacmd_toncq(xfer, &cmd, &count, &features, 469 &device); 470 471 wdccommandext(chp, xfer->c_drive, cmd, 472 ata_bio->blkno, count, features, device); 473 } else { 474 wdccommand(chp, xfer->c_drive, cmd, cyl, 475 head, sect, count, features); 476 } 477 /* start the DMA channel after */ 478 if ((chp->ch_flags & ATACH_DMA_BEFORE_CMD) == 0) 479 (*wdc->dma_start)(wdc->dma_arg, 480 chp->ch_channel, xfer->c_drive); 481 chp->ch_flags |= ATACH_DMA_WAIT; 482 /* start timeout machinery */ 483 if ((xfer->c_flags & C_POLL) == 0) 484 callout_reset(&chp->c_timo_callout, 485 ATA_DELAY / 1000 * hz, wdctimeout, chp); 486 /* wait for irq */ 487 goto intr; 488 } /* else not DMA */ 489 do_pio: 490 #endif /* NATA_DMA */ 491 #if NATA_PIOBM 492 if ((xfer->c_flags & C_PIOBM) && xfer->c_skip == 0) { 493 if (ata_bio->flags & ATA_POLL) { 494 /* XXX not supported yet --- fall back to PIO */ 495 xfer->c_flags &= ~C_PIOBM; 496 } else { 497 /* Init the DMA channel. */ 498 error = (*wdc->dma_init)(wdc->dma_arg, 499 chp->ch_channel, xfer->c_drive, 500 (char *)xfer->c_databuf + xfer->c_skip, 501 xfer->c_bcount, 502 dma_flags | WDC_DMA_PIOBM_ATA); 503 if (error) { 504 if (error == EINVAL) { 505 /* 506 * We can't do DMA on this 507 * transfer for some reason. 508 * Fall back to PIO. 509 */ 510 xfer->c_flags &= ~C_PIOBM; 511 error = 0; 512 } else { 513 ata_bio->error = ERR_DMA; 514 ata_bio->r_error = 0; 515 return ATASTART_ABORT; 516 } 517 } 518 } 519 } 520 #endif 521 ata_bio->nblks = uimin(nblks, drvp->multi); 522 ata_bio->nbytes = ata_bio->nblks * drvp->lp->d_secsize; 523 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 524 if (ata_bio->nblks > 1) { 525 cmd = (ata_bio->flags & ATA_READ) ? 526 WDCC_READMULTI : WDCC_WRITEMULTI; 527 } else { 528 cmd = (ata_bio->flags & ATA_READ) ? 529 WDCC_READ : WDCC_WRITE; 530 } 531 /* Initiate command! */ 532 if (wdc->select) 533 wdc->select(chp, xfer->c_drive); 534 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 535 WDSD_IBM | (xfer->c_drive << 4)); 536 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, &tfd)) { 537 case WDCWAIT_OK: 538 break; 539 case WDCWAIT_TOUT: 540 goto timeout; 541 case WDCWAIT_THR: 542 return ATASTART_TH; 543 } 544 if (ata_bio->flags & ATA_LBA48) { 545 wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd), 546 ata_bio->blkno, nblks, 0, WDSD_LBA); 547 } else { 548 wdccommand(chp, xfer->c_drive, cmd, cyl, 549 head, sect, nblks, 550 (drvp->lp->d_type == DKTYPE_ST506) ? 551 drvp->lp->d_precompcyl / 4 : 0); 552 } 553 /* start timeout machinery */ 554 if ((xfer->c_flags & C_POLL) == 0) 555 callout_reset(&chp->c_timo_callout, 556 ATA_DELAY / 1000 * hz, wdctimeout, chp); 557 } else if (ata_bio->nblks > 1) { 558 /* The number of blocks in the last stretch may be smaller. */ 559 nblks = xfer->c_bcount / drvp->lp->d_secsize; 560 if (ata_bio->nblks > nblks) { 561 ata_bio->nblks = nblks; 562 ata_bio->nbytes = xfer->c_bcount; 563 } 564 } 565 /* If this was a write and not using DMA, push the data. */ 566 if ((ata_bio->flags & ATA_READ) == 0) { 567 /* 568 * we have to busy-wait here, we can't rely on running in 569 * thread context. 570 */ 571 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL, &tfd) != 0) { 572 printf("%s:%d:%d: timeout waiting for DRQ, " 573 "st=0x%02x, err=0x%02x\n", 574 device_xname(atac->atac_dev), chp->ch_channel, 575 xfer->c_drive, 576 ATACH_ST(tfd), ATACH_ERR(tfd)); 577 if (wdc_ata_err(drvp, ata_bio, tfd) != WDC_ATA_ERR) 578 ata_bio->error = TIMEOUT; 579 return ATASTART_ABORT; 580 } 581 if (wdc_ata_err(drvp, ata_bio, tfd) == WDC_ATA_ERR) { 582 return ATASTART_ABORT; 583 } 584 #if NATA_PIOBM 585 if (xfer->c_flags & C_PIOBM) { 586 /* start the busmastering PIO */ 587 (*wdc->piobm_start)(wdc->dma_arg, 588 chp->ch_channel, xfer->c_drive, 589 xfer->c_skip, ata_bio->nbytes, 0); 590 chp->ch_flags |= ATACH_DMA_WAIT; 591 } else 592 #endif 593 594 wdc->dataout_pio(chp, drvp->drive_flags, 595 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 596 } 597 598 #if NATA_DMA 599 intr: 600 #endif 601 /* Wait for IRQ (either real or polled) */ 602 if ((ata_bio->flags & ATA_POLL) == 0) { 603 chp->ch_flags |= ATACH_IRQ_WAIT; 604 return ATASTART_STARTED; 605 } else { 606 return ATASTART_POLL; 607 } 608 609 timeout: 610 printf("%s:%d:%d: not ready, st=0x%02x, err=0x%02x\n", 611 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 612 ATACH_ST(tfd), ATACH_ERR(tfd)); 613 if (wdc_ata_err(drvp, ata_bio, tfd) != WDC_ATA_ERR) 614 ata_bio->error = TIMEOUT; 615 return ATASTART_ABORT; 616 } 617 618 static int 619 wdc_ata_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 620 { 621 /* Wait for at last 400ns for status bit to be valid */ 622 delay(1); 623 #if NATA_DMA 624 if (chp->ch_flags & ATACH_DMA_WAIT) { 625 wdc_dmawait(chp, xfer, ATA_DELAY); 626 chp->ch_flags &= ~ATACH_DMA_WAIT; 627 } 628 #endif 629 wdc_ata_bio_intr(chp, xfer, 0); 630 return (xfer->c_bio.flags & ATA_ITSDONE) ? ATAPOLL_DONE : ATAPOLL_AGAIN; 631 } 632 633 static int 634 wdc_ata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 635 { 636 struct atac_softc *atac = chp->ch_atac; 637 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 638 struct ata_bio *ata_bio = &xfer->c_bio; 639 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 640 int drv_err, tfd; 641 642 ATADEBUG_PRINT(("wdc_ata_bio_intr %s:%d:%d\n", 643 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 644 DEBUG_INTR | DEBUG_XFERS); 645 646 ata_channel_lock(chp); 647 648 /* Is it not a transfer, but a control operation? */ 649 if (drvp->state < READY) { 650 printf("%s:%d:%d: bad state %d in wdc_ata_bio_intr\n", 651 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 652 drvp->state); 653 panic("wdc_ata_bio_intr: bad state"); 654 } 655 656 /* 657 * if we missed an interrupt in a PIO transfer, reset and restart. 658 * Don't try to continue transfer, we may have missed cycles. 659 */ 660 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 661 ata_bio->error = TIMEOUT; 662 goto err; 663 } 664 665 #if NATA_PIOBM 666 /* Transfer-done interrupt for busmastering PIO read */ 667 if ((xfer->c_flags & C_PIOBM) && (chp->ch_flags & ATACH_PIOBM_WAIT)) { 668 chp->ch_flags &= ~ATACH_PIOBM_WAIT; 669 goto end; 670 } 671 #endif 672 673 /* Ack interrupt done by wdc_wait_for_unbusy */ 674 if (wdc_wait_for_unbusy(chp, 675 (irq == 0) ? ATA_DELAY : 0, AT_POLL, &tfd) < 0) { 676 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 677 ata_channel_unlock(chp); 678 return 0; /* IRQ was not for us */ 679 } 680 printf("%s:%d:%d: device timeout, c_bcount=%d, c_skip%d\n", 681 device_xname(atac->atac_dev), chp->ch_channel, 682 xfer->c_drive, xfer->c_bcount, xfer->c_skip); 683 ata_bio->error = TIMEOUT; 684 goto err; 685 } 686 if (wdc->irqack) 687 wdc->irqack(chp); 688 689 drv_err = wdc_ata_err(drvp, ata_bio, tfd); 690 691 #if NATA_DMA 692 /* If we were using DMA, Turn off the DMA channel and check for error */ 693 if (xfer->c_flags & C_DMA) { 694 if (ata_bio->flags & ATA_POLL) { 695 /* 696 * IDE drives deassert WDCS_BSY before transfer is 697 * complete when using DMA. Polling for DRQ to deassert 698 * is not enough DRQ is not required to be 699 * asserted for DMA transfers, so poll for DRDY. 700 */ 701 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 702 ATA_DELAY, ATA_POLL, &tfd) == WDCWAIT_TOUT) { 703 printf("%s:%d:%d: polled transfer timed out " 704 "(st=0x%x)\n", 705 device_xname(atac->atac_dev), 706 chp->ch_channel, xfer->c_drive, 707 ATACH_ST(tfd)); 708 ata_bio->error = TIMEOUT; 709 drv_err = WDC_ATA_ERR; 710 } 711 } 712 if (wdc->dma_status != 0) { 713 if (drv_err != WDC_ATA_ERR) { 714 ata_bio->error = ERR_DMA; 715 drv_err = WDC_ATA_ERR; 716 } 717 } 718 if (ATACH_ST(tfd) & WDCS_DRQ) { 719 if (drv_err != WDC_ATA_ERR) { 720 printf("%s:%d:%d: intr with DRQ (st=0x%x)\n", 721 device_xname(atac->atac_dev), 722 chp->ch_channel, 723 xfer->c_drive, ATACH_ST(tfd)); 724 ata_bio->error = TIMEOUT; 725 drv_err = WDC_ATA_ERR; 726 } 727 } 728 if (drv_err != WDC_ATA_ERR) 729 goto end; 730 if (ata_bio->r_error & WDCE_CRC || ata_bio->error == ERR_DMA) { 731 ata_dmaerr(drvp, 732 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 733 goto err; 734 } 735 } 736 #endif /* NATA_DMA */ 737 738 /* if we had an error, end */ 739 if (drv_err == WDC_ATA_ERR) 740 goto err; 741 742 /* If this was a read and not using DMA, fetch the data. */ 743 if ((ata_bio->flags & ATA_READ) != 0) { 744 if ((ATACH_ST(tfd) & WDCS_DRQ) != WDCS_DRQ) { 745 printf("%s:%d:%d: read intr before drq\n", 746 device_xname(atac->atac_dev), chp->ch_channel, 747 xfer->c_drive); 748 ata_bio->error = TIMEOUT; 749 goto err; 750 } 751 #if NATA_PIOBM 752 if (xfer->c_flags & C_PIOBM) { 753 /* start the busmastering PIO */ 754 (*wdc->piobm_start)(wdc->dma_arg, 755 chp->ch_channel, xfer->c_drive, 756 xfer->c_skip, ata_bio->nbytes, 757 WDC_PIOBM_XFER_IRQ); 758 chp->ch_flags |= ATACH_DMA_WAIT | ATACH_PIOBM_WAIT; 759 ata_channel_unlock(chp); 760 return 1; 761 } 762 #endif 763 wdc->datain_pio(chp, drvp->drive_flags, 764 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 765 } 766 767 #if NATA_DMA || NATA_PIOBM 768 end: 769 #endif 770 ata_bio->blkno += ata_bio->nblks; 771 ata_bio->blkdone += ata_bio->nblks; 772 xfer->c_skip += ata_bio->nbytes; 773 xfer->c_bcount -= ata_bio->nbytes; 774 775 /* See if this transfer is complete. */ 776 if (xfer->c_bcount > 0) { 777 if ((ata_bio->flags & ATA_POLL) == 0) { 778 /* Start the next operation */ 779 ata_xfer_start(xfer); 780 } else { 781 /* 782 * Let ata_xfer_start() do the loop; 783 * see wdc_ata_bio_poll(). 784 */ 785 } 786 ata_channel_unlock(chp); 787 return 1; 788 } 789 790 /* Done with this transfer */ 791 ata_bio->error = NOERROR; 792 err: ata_channel_unlock(chp); 793 wdc_ata_bio_done(chp, xfer); 794 return 1; 795 } 796 797 static void 798 wdc_ata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 799 int reason) 800 { 801 struct ata_bio *ata_bio = &xfer->c_bio; 802 int drive = xfer->c_drive; 803 bool deactivate = true; 804 805 ata_bio->flags |= ATA_ITSDONE; 806 switch (reason) { 807 case KILL_GONE_INACTIVE: 808 deactivate = false; 809 /* FALLTHROUGH */ 810 case KILL_GONE: 811 ata_bio->error = ERR_NODEV; 812 break; 813 case KILL_RESET: 814 ata_bio->error = ERR_RESET; 815 break; 816 default: 817 printf("wdc_ata_bio_kill_xfer: unknown reason %d\n", 818 reason); 819 panic("wdc_ata_bio_kill_xfer"); 820 } 821 ata_bio->r_error = WDCE_ABRT; 822 823 if (deactivate) 824 ata_deactivate_xfer(chp, xfer); 825 826 ATADEBUG_PRINT(("wdc_ata_bio_kill_xfer: drv_done\n"), DEBUG_XFERS); 827 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 828 } 829 830 static void 831 wdc_ata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 832 { 833 struct ata_bio *ata_bio = &xfer->c_bio; 834 int drive = xfer->c_drive; 835 836 ATADEBUG_PRINT(("wdc_ata_bio_done %s:%d:%d: flags 0x%x\n", 837 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 838 xfer->c_drive, (u_int)xfer->c_flags), 839 DEBUG_XFERS); 840 841 if (ata_waitdrain_xfer_check(chp, xfer)) 842 return; 843 844 /* feed back residual bcount to our caller */ 845 ata_bio->bcount = xfer->c_bcount; 846 847 /* mark controller inactive and free xfer */ 848 ata_deactivate_xfer(chp, xfer); 849 850 ata_bio->flags |= ATA_ITSDONE; 851 ATADEBUG_PRINT(("wdc_ata_done: drv_done\n"), DEBUG_XFERS); 852 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 853 ATADEBUG_PRINT(("atastart from wdc_ata_done, flags 0x%x\n", 854 chp->ch_flags), DEBUG_XFERS); 855 atastart(chp); 856 } 857 858 static int 859 wdc_ata_err(struct ata_drive_datas *drvp, struct ata_bio *ata_bio, int tfd) 860 { 861 ata_bio->error = 0; 862 if (ATACH_ST(tfd) & WDCS_BSY) { 863 ata_bio->error = TIMEOUT; 864 return WDC_ATA_ERR; 865 } 866 867 if (ATACH_ST(tfd) & WDCS_DWF) { 868 ata_bio->error = ERR_DF; 869 return WDC_ATA_ERR; 870 } 871 872 if (ATACH_ST(tfd) & WDCS_ERR) { 873 ata_bio->error = ERROR; 874 ata_bio->r_error = ATACH_ERR(tfd); 875 if (ata_bio->r_error & (WDCE_BBK | WDCE_UNC | WDCE_IDNF | 876 WDCE_ABRT | WDCE_TK0NF | WDCE_AMNF)) 877 return WDC_ATA_ERR; 878 return WDC_ATA_NOERR; 879 } 880 881 if (ATACH_ST(tfd) & WDCS_CORR) 882 ata_bio->flags |= ATA_CORR; 883 return WDC_ATA_NOERR; 884 } 885 886 static int 887 wdc_ata_addref(struct ata_drive_datas *drvp) 888 { 889 struct ata_channel *chp = drvp->chnl_softc; 890 891 return (ata_addref(chp)); 892 } 893 894 static void 895 wdc_ata_delref(struct ata_drive_datas *drvp) 896 { 897 struct ata_channel *chp = drvp->chnl_softc; 898 899 ata_delref(chp); 900 } 901
Indexes created Sat Oct 25 16:10:12 GMT 2025