ata_wdc.c revision 1.14
1 /* $NetBSD: ata_wdc.c,v 1.14 1999/02/08 15:22:28 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 */ 35 36 /*- 37 * Copyright (c) 1998 The NetBSD Foundation, Inc. 38 * All rights reserved. 39 * 40 * This code is derived from software contributed to The NetBSD Foundation 41 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by the NetBSD 54 * Foundation, Inc. and its contributors. 55 * 4. Neither the name of The NetBSD Foundation nor the names of its 56 * contributors may be used to endorse or promote products derived 57 * from this software without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 60 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 #define WDCDEBUG 73 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/kernel.h> 77 #include <sys/file.h> 78 #include <sys/stat.h> 79 #include <sys/buf.h> 80 #include <sys/malloc.h> 81 #include <sys/device.h> 82 #include <sys/disklabel.h> 83 #include <sys/syslog.h> 84 #include <sys/proc.h> 85 86 #include <machine/intr.h> 87 #include <machine/bus.h> 88 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 89 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 90 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 91 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 92 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 93 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 94 95 #include <dev/ata/atareg.h> 96 #include <dev/ata/atavar.h> 97 #include <dev/ic/wdcreg.h> 98 #include <dev/ic/wdcvar.h> 99 #include <dev/ata/wdvar.h> 100 101 #define DEBUG_INTR 0x01 102 #define DEBUG_XFERS 0x02 103 #define DEBUG_STATUS 0x04 104 #define DEBUG_FUNCS 0x08 105 #define DEBUG_PROBE 0x10 106 #ifdef WDCDEBUG 107 int wdcdebug_wd_mask = 0; 108 #define WDCDEBUG_PRINT(args, level) \ 109 if (wdcdebug_wd_mask & (level)) \ 110 printf args 111 #else 112 #define WDCDEBUG_PRINT(args, level) 113 #endif 114 115 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 116 117 void wdc_ata_bio_start __P((struct channel_softc *,struct wdc_xfer *)); 118 int wdc_ata_bio_intr __P((struct channel_softc *, struct wdc_xfer *)); 119 void wdc_ata_bio_done __P((struct channel_softc *, struct wdc_xfer *)); 120 int wdc_ata_ctrl_intr __P((struct channel_softc *, struct wdc_xfer *)); 121 int wdc_ata_err __P((struct channel_softc *, struct ata_bio *)); 122 #define WDC_ATA_NOERR 0x00 /* Drive doesn't report an error */ 123 #define WDC_ATA_RECOV 0x01 /* There was a recovered error */ 124 #define WDC_ATA_ERR 0x02 /* Drive reports an error */ 125 126 /* 127 * Handle block I/O operation. Return WDC_COMPLETE, WDC_QUEUED, or 128 * WDC_TRY_AGAIN. Must be called at splio(). 129 */ 130 int 131 wdc_ata_bio(drvp, ata_bio) 132 struct ata_drive_datas *drvp; 133 struct ata_bio *ata_bio; 134 { 135 struct wdc_xfer *xfer; 136 struct channel_softc *chp = drvp->chnl_softc; 137 138 xfer = wdc_get_xfer(WDC_NOSLEEP); 139 if (xfer == NULL) 140 return WDC_TRY_AGAIN; 141 if (ata_bio->flags & ATA_POLL) 142 xfer->c_flags |= C_POLL; 143 if ((drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) && 144 (ata_bio->flags & ATA_SINGLE) == 0) 145 xfer->c_flags |= C_DMA; 146 xfer->drive = drvp->drive; 147 xfer->cmd = ata_bio; 148 xfer->databuf = ata_bio->databuf; 149 xfer->c_bcount = ata_bio->bcount; 150 xfer->c_start = wdc_ata_bio_start; 151 xfer->c_intr = wdc_ata_bio_intr; 152 wdc_exec_xfer(chp, xfer); 153 return (ata_bio->flags & ATA_ITSDONE) ? WDC_COMPLETE : WDC_QUEUED; 154 } 155 156 void 157 wdc_ata_bio_start(chp, xfer) 158 struct channel_softc *chp; 159 struct wdc_xfer *xfer; 160 { 161 struct ata_bio *ata_bio = xfer->cmd; 162 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; 163 u_int16_t cyl; 164 u_int8_t head, sect, cmd = 0; 165 int nblks; 166 int dma_flags = 0; 167 168 WDCDEBUG_PRINT(("wdc_ata_bio_start %s:%d:%d\n", 169 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 170 DEBUG_XFERS); 171 172 /* Do control operations specially. */ 173 if (drvp->state < READY) { 174 /* 175 * Actually, we want to be careful not to mess with the control 176 * state if the device is currently busy, but we can assume 177 * that we never get to this point if that's the case. 178 */ 179 /* at this point, we should only be in RECAL state */ 180 if (drvp->state != RECAL) { 181 printf("%s:%d:%d: bad state %d in wdc_ata_bio_start\n", 182 chp->wdc->sc_dev.dv_xname, chp->channel, 183 xfer->drive, drvp->state); 184 panic("wdc_ata_bio_start: bad state"); 185 } 186 xfer->c_intr = wdc_ata_ctrl_intr; 187 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 188 WDSD_IBM | (xfer->drive << 4)); 189 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY) != 0) 190 goto timeout; 191 wdccommandshort(chp, xfer->drive, WDCC_RECAL); 192 drvp->state = RECAL_WAIT; 193 if ((ata_bio->flags & ATA_POLL) == 0) { 194 chp->ch_flags |= WDCF_IRQ_WAIT; 195 timeout(wdctimeout, chp, ATA_DELAY / 1000 * hz); 196 } else { 197 /* Wait for at last 400ns for status bit to be valid */ 198 delay(1); 199 wdc_ata_ctrl_intr(chp, xfer); 200 } 201 return; 202 } 203 204 if (xfer->c_flags & C_DMA) { 205 dma_flags = (ata_bio->flags & ATA_READ) ? WDC_DMA_READ : 0; 206 dma_flags |= (ata_bio->flags & ATA_POLL) ? WDC_DMA_POLL : 0; 207 } 208 again: 209 /* 210 * 211 * When starting a multi-sector transfer, or doing single-sector 212 * transfers... 213 */ 214 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 215 if (ata_bio->flags & ATA_SINGLE) 216 nblks = 1; 217 else 218 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 219 /* Check for bad sectors and adjust transfer, if necessary. */ 220 if ((ata_bio->lp->d_flags & D_BADSECT) != 0) { 221 long blkdiff; 222 int i; 223 for (i = 0; (blkdiff = ata_bio->badsect[i]) != -1; 224 i++) { 225 blkdiff -= ata_bio->blkno; 226 if (blkdiff < 0) 227 continue; 228 if (blkdiff == 0) { 229 /* Replace current block of transfer. */ 230 ata_bio->blkno = 231 ata_bio->lp->d_secperunit - 232 ata_bio->lp->d_nsectors - i - 1; 233 } 234 if (blkdiff < nblks) { 235 /* Bad block inside transfer. */ 236 ata_bio->flags |= ATA_SINGLE; 237 nblks = 1; 238 } 239 break; 240 } 241 /* Transfer is okay now. */ 242 } 243 if (ata_bio->flags & ATA_LBA) { 244 sect = (ata_bio->blkno >> 0) & 0xff; 245 cyl = (ata_bio->blkno >> 8) & 0xffff; 246 head = (ata_bio->blkno >> 24) & 0x0f; 247 head |= WDSD_LBA; 248 } else { 249 int blkno = ata_bio->blkno; 250 sect = blkno % ata_bio->lp->d_nsectors; 251 sect++; /* Sectors begin with 1, not 0. */ 252 blkno /= ata_bio->lp->d_nsectors; 253 head = blkno % ata_bio->lp->d_ntracks; 254 blkno /= ata_bio->lp->d_ntracks; 255 cyl = blkno; 256 head |= WDSD_CHS; 257 } 258 if (xfer->c_flags & C_DMA) { 259 ata_bio->nblks = nblks; 260 ata_bio->nbytes = xfer->c_bcount; 261 cmd = (ata_bio->flags & ATA_READ) ? 262 WDCC_READDMA : WDCC_WRITEDMA; 263 nblks = ata_bio->nblks; 264 /* Init the DMA channel. */ 265 if ((*chp->wdc->dma_init)(chp->wdc->dma_arg, 266 chp->channel, xfer->drive, 267 (char *)xfer->databuf + xfer->c_skip, 268 ata_bio->nbytes, dma_flags) != 0) { 269 ata_bio->error = ERR_DMA; 270 ata_bio->r_error = 0; 271 wdc_ata_bio_done(chp, xfer); 272 return; 273 } 274 /* Initiate command */ 275 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 276 WDSD_IBM | (xfer->drive << 4)); 277 if (wait_for_ready(chp, ATA_DELAY) < 0) 278 goto timeout; 279 wdccommand(chp, xfer->drive, cmd, cyl, 280 head, sect, nblks, 0); 281 /* start the DMA channel */ 282 (*chp->wdc->dma_start)(chp->wdc->dma_arg, 283 chp->channel, xfer->drive, dma_flags); 284 /* wait for irq */ 285 goto intr; 286 } /* else not DMA */ 287 ata_bio->nblks = min(nblks, ata_bio->multi); 288 ata_bio->nbytes = ata_bio->nblks * ata_bio->lp->d_secsize; 289 if (ata_bio->nblks > 1 && (ata_bio->flags & ATA_SINGLE) == 0) { 290 cmd = (ata_bio->flags & ATA_READ) ? 291 WDCC_READMULTI : WDCC_WRITEMULTI; 292 } else { 293 cmd = (ata_bio->flags & ATA_READ) ? 294 WDCC_READ : WDCC_WRITE; 295 } 296 /* Initiate command! */ 297 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 298 WDSD_IBM | (xfer->drive << 4)); 299 if (wait_for_ready(chp, ATA_DELAY) < 0) 300 goto timeout; 301 wdccommand(chp, xfer->drive, cmd, cyl, 302 head, sect, nblks, 303 (ata_bio->lp->d_type == DTYPE_ST506) ? 304 ata_bio->lp->d_precompcyl / 4 : 0); 305 } else if (ata_bio->nblks > 1) { 306 /* The number of blocks in the last stretch may be smaller. */ 307 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 308 if (ata_bio->nblks > nblks) { 309 ata_bio->nblks = nblks; 310 ata_bio->nbytes = xfer->c_bcount; 311 } 312 } 313 /* If this was a write and not using DMA, push the data. */ 314 if ((ata_bio->flags & ATA_READ) == 0) { 315 if (wait_for_drq(chp, ATA_DELAY) != 0) { 316 printf("%s:%d:%d: timeout waiting for DRQ, " 317 "st=0x%02x, err=0x%02x\n", 318 chp->wdc->sc_dev.dv_xname, chp->channel, 319 xfer->drive, chp->ch_status, chp->ch_error); 320 if (wdc_ata_err(chp, ata_bio) != WDC_ATA_ERR) 321 ata_bio->error = TIMEOUT; 322 wdc_ata_bio_done(chp, xfer); 323 return; 324 } 325 if (wdc_ata_err(chp, ata_bio) == WDC_ATA_ERR) { 326 wdc_ata_bio_done(chp, xfer); 327 return; 328 } 329 if ((chp->wdc->cap & WDC_CAPABILITY_ATA_NOSTREAM)) { 330 if (drvp->drive_flags & DRIVE_CAP32) { 331 bus_space_write_multi_4(chp->data32iot, 332 chp->data32ioh, 0, 333 (u_int32_t *)((char *)xfer->databuf + 334 xfer->c_skip), 335 ata_bio->nbytes >> 2); 336 } else { 337 bus_space_write_multi_2(chp->cmd_iot, 338 chp->cmd_ioh, wd_data, 339 (u_int16_t *)((char *)xfer->databuf + 340 xfer->c_skip), 341 ata_bio->nbytes >> 1); 342 } 343 } else { 344 if (drvp->drive_flags & DRIVE_CAP32) { 345 bus_space_write_multi_stream_4(chp->data32iot, 346 chp->data32ioh, 0, 347 (u_int32_t *)((char *)xfer->databuf + 348 xfer->c_skip), 349 ata_bio->nbytes >> 2); 350 } else { 351 bus_space_write_multi_stream_2(chp->cmd_iot, 352 chp->cmd_ioh, wd_data, 353 (u_int16_t *)((char *)xfer->databuf + 354 xfer->c_skip), 355 ata_bio->nbytes >> 1); 356 } 357 } 358 } 359 360 intr: /* Wait for IRQ (either real or polled) */ 361 if ((ata_bio->flags & ATA_POLL) == 0) { 362 chp->ch_flags |= WDCF_IRQ_WAIT; 363 timeout(wdctimeout, chp, ATA_DELAY / 1000 * hz); 364 } else { 365 /* Wait for at last 400ns for status bit to be valid */ 366 delay(1); 367 wdc_ata_bio_intr(chp, xfer); 368 if ((ata_bio->flags & ATA_ITSDONE) == 0) 369 goto again; 370 } 371 return; 372 timeout: 373 printf("%s:%d:%d: not ready, st=0x%02x, err=0x%02x\n", 374 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 375 chp->ch_status, chp->ch_error); 376 if (wdc_ata_err(chp, ata_bio) != WDC_ATA_ERR) 377 ata_bio->error = TIMEOUT; 378 wdc_ata_bio_done(chp, xfer); 379 return; 380 } 381 382 int 383 wdc_ata_bio_intr(chp, xfer) 384 struct channel_softc *chp; 385 struct wdc_xfer *xfer; 386 { 387 struct ata_bio *ata_bio = xfer->cmd; 388 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; 389 int drv_err; 390 int dma_flags = 0; 391 392 WDCDEBUG_PRINT(("wdc_ata_bio_intr %s:%d:%d\n", 393 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 394 DEBUG_INTR | DEBUG_XFERS); 395 396 397 /* Is it not a transfer, but a control operation? */ 398 if (drvp->state < READY) { 399 printf("%s:%d:%d: bad state %d in wdc_ata_bio_intr\n", 400 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 401 drvp->state); 402 panic("wdc_ata_bio_intr: bad state\n"); 403 } 404 405 if (xfer->c_flags & C_DMA) { 406 dma_flags = (ata_bio->flags & ATA_READ) ? WDC_DMA_READ : 0; 407 dma_flags |= (ata_bio->flags & ATA_POLL) ? WDC_DMA_POLL : 0; 408 } 409 410 /* Ack interrupt done by wait_for_unbusy */ 411 if (wait_for_unbusy(chp, ATA_DELAY) < 0) { 412 printf("%s:%d:%d: device timeout, c_bcount=%d, c_skip%d\n", 413 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 414 xfer->c_bcount, xfer->c_skip); 415 /* if we were using DMA, turn off DMA channel */ 416 if (xfer->c_flags & C_DMA) { 417 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 418 chp->channel, xfer->drive, dma_flags); 419 drvp->n_dmaerrs++; 420 } 421 ata_bio->error = TIMEOUT; 422 wdc_ata_bio_done(chp, xfer); 423 return 1; 424 } 425 426 drv_err = wdc_ata_err(chp, ata_bio); 427 428 /* If we were using DMA, Turn off the DMA channel and check for error */ 429 if (xfer->c_flags & C_DMA) { 430 if (ata_bio->flags & ATA_POLL) { 431 /* 432 * IDE drives deassert WDCS_BSY before transfer is 433 * complete when using DMA. Polling for DRQ to deassert 434 * is not enouth DRQ is not required to be 435 * asserted for DMA transfers, so poll for DRDY. 436 */ 437 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 438 ATA_DELAY) < 0) { 439 printf("%s:%d:%d: polled transfer timed out " 440 "(st=0x%x)\n", chp->wdc->sc_dev.dv_xname, 441 chp->channel, xfer->drive, chp->ch_status); 442 ata_bio->error = TIMEOUT; 443 drv_err = WDC_ATA_ERR; 444 } 445 } 446 if ((*chp->wdc->dma_finish)(chp->wdc->dma_arg, 447 chp->channel, xfer->drive, dma_flags) != 0) { 448 if (drv_err != WDC_ATA_ERR) { 449 ata_bio->error = ERR_DMA; 450 drv_err = WDC_ATA_ERR; 451 } 452 } 453 if (chp->ch_status & WDCS_DRQ) { 454 if (drv_err != WDC_ATA_ERR) { 455 printf("%s:%d:%d: intr with DRQ (st=0x%x)\n", 456 chp->wdc->sc_dev.dv_xname, chp->channel, 457 xfer->drive, chp->ch_status); 458 ata_bio->error = TIMEOUT; 459 drv_err = WDC_ATA_ERR; 460 } 461 } 462 if (drv_err != WDC_ATA_ERR) 463 goto end; 464 drvp->n_dmaerrs++; 465 } 466 467 /* if we had an error, end */ 468 if (drv_err == WDC_ATA_ERR) { 469 wdc_ata_bio_done(chp, xfer); 470 return 1; 471 } 472 473 /* If this was a read and not using DMA, fetch the data. */ 474 if ((ata_bio->flags & ATA_READ) != 0) { 475 if ((chp->ch_status & WDCS_DRQ) != WDCS_DRQ) { 476 printf("%s:%d:%d: read intr before drq\n", 477 chp->wdc->sc_dev.dv_xname, chp->channel, 478 xfer->drive); 479 ata_bio->error = TIMEOUT; 480 wdc_ata_bio_done(chp, xfer); 481 return 1; 482 } 483 if ((chp->wdc->cap & WDC_CAPABILITY_ATA_NOSTREAM)) { 484 if (drvp->drive_flags & DRIVE_CAP32) { 485 bus_space_read_multi_4(chp->data32iot, 486 chp->data32ioh, 0, 487 (u_int32_t *)((char *)xfer->databuf + 488 xfer->c_skip), 489 ata_bio->nbytes >> 2); 490 } else { 491 bus_space_read_multi_2(chp->cmd_iot, 492 chp->cmd_ioh, wd_data, 493 (u_int16_t *)((char *)xfer->databuf + 494 xfer->c_skip), 495 ata_bio->nbytes >> 1); 496 } 497 } else { 498 if (drvp->drive_flags & DRIVE_CAP32) { 499 bus_space_read_multi_stream_4(chp->data32iot, 500 chp->data32ioh, 0, 501 (u_int32_t *)((char *)xfer->databuf + 502 xfer->c_skip), 503 ata_bio->nbytes >> 2); 504 } else { 505 bus_space_read_multi_stream_2(chp->cmd_iot, 506 chp->cmd_ioh, wd_data, 507 (u_int16_t *)((char *)xfer->databuf + 508 xfer->c_skip), 509 ata_bio->nbytes >> 1); 510 } 511 } 512 } 513 514 end: 515 ata_bio->blkno += ata_bio->nblks; 516 ata_bio->blkdone += ata_bio->nblks; 517 xfer->c_skip += ata_bio->nbytes; 518 xfer->c_bcount -= ata_bio->nbytes; 519 /* See if this transfer is complete. */ 520 if (xfer->c_bcount > 0) { 521 if ((ata_bio->flags & ATA_POLL) == 0) { 522 /* Start the next operation */ 523 wdc_ata_bio_start(chp, xfer); 524 } else { 525 /* Let wdc_ata_bio_start do the loop */ 526 return 1; 527 } 528 } else { /* Done with this transfer */ 529 ata_bio->error = NOERROR; 530 wdc_ata_bio_done(chp, xfer); 531 } 532 return 1; 533 } 534 535 void 536 wdc_ata_bio_done(chp, xfer) 537 struct channel_softc *chp; 538 struct wdc_xfer *xfer; 539 { 540 struct ata_bio *ata_bio = xfer->cmd; 541 int need_done = xfer->c_flags & C_NEEDDONE; 542 int drive = xfer->drive; 543 struct ata_drive_datas *drvp = &chp->ch_drive[drive]; 544 545 WDCDEBUG_PRINT(("wdc_ata_bio_done %s:%d:%d: flags 0x%x\n", 546 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 547 (u_int)xfer->c_flags), 548 DEBUG_XFERS); 549 550 if (ata_bio->error == NOERROR) 551 drvp->n_dmaerrs = 0; 552 else if (drvp->n_dmaerrs >= NERRS_MAX) { 553 wdc_downgrade_mode(drvp); 554 } 555 556 /* feed back residual bcount to our caller */ 557 ata_bio->bcount = xfer->c_bcount; 558 559 /* remove this command from xfer queue */ 560 wdc_free_xfer(chp, xfer); 561 562 ata_bio->flags |= ATA_ITSDONE; 563 if (need_done) { 564 WDCDEBUG_PRINT(("wdc_ata_done: wddone\n"), DEBUG_XFERS); 565 wddone(chp->ch_drive[drive].drv_softc); 566 } 567 WDCDEBUG_PRINT(("wdcstart from wdc_ata_done, flags 0x%x\n", 568 chp->ch_flags), DEBUG_XFERS); 569 wdcstart(chp); 570 } 571 572 /* 573 * Implement operations needed before read/write. 574 */ 575 int 576 wdc_ata_ctrl_intr(chp, xfer) 577 struct channel_softc *chp; 578 struct wdc_xfer *xfer; 579 { 580 struct ata_bio *ata_bio = xfer->cmd; 581 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; 582 char *errstring = NULL; 583 WDCDEBUG_PRINT(("wdc_ata_ctrl_intr: state %d\n", drvp->state), 584 DEBUG_FUNCS); 585 586 again: 587 switch (drvp->state) { 588 case RECAL: /* Should not be in this state here */ 589 panic("wdc_ata_ctrl_intr: state==RECAL"); 590 break; 591 592 case RECAL_WAIT: 593 errstring = "recal"; 594 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY)) 595 goto timeout; 596 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 597 goto error; 598 /* fall through */ 599 600 case PIOMODE: 601 /* Don't try to set modes if controller can't be adjusted */ 602 if ((chp->wdc->cap & WDC_CAPABILITY_MODE) == 0) 603 goto geometry; 604 /* Also don't try if the drive didn't report its mode */ 605 if ((drvp->drive_flags & DRIVE_MODE) == 0) 606 goto geometry; 607 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 608 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 609 drvp->state = PIOMODE_WAIT; 610 break; 611 612 case PIOMODE_WAIT: 613 errstring = "piomode"; 614 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY)) 615 goto timeout; 616 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 617 goto error; 618 /* fall through */ 619 620 case DMAMODE: 621 if (drvp->drive_flags & DRIVE_UDMA) { 622 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 623 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 624 } else if (drvp->drive_flags & DRIVE_DMA) { 625 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 626 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 627 } else { 628 goto geometry; 629 } 630 drvp->state = DMAMODE_WAIT; 631 break; 632 case DMAMODE_WAIT: 633 errstring = "dmamode"; 634 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY)) 635 goto timeout; 636 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 637 goto error; 638 /* fall through */ 639 640 case GEOMETRY: 641 geometry: 642 if (ata_bio->flags & ATA_LBA) 643 goto multimode; 644 wdccommand(chp, xfer->drive, WDCC_IDP, 645 ata_bio->lp->d_ncylinders, 646 ata_bio->lp->d_ntracks - 1, 0, ata_bio->lp->d_nsectors, 647 (ata_bio->lp->d_type == DTYPE_ST506) ? 648 ata_bio->lp->d_precompcyl / 4 : 0); 649 drvp->state = GEOMETRY_WAIT; 650 break; 651 652 case GEOMETRY_WAIT: 653 errstring = "geometry"; 654 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY)) 655 goto timeout; 656 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 657 goto error; 658 /* fall through */ 659 660 case MULTIMODE: 661 multimode: 662 if (ata_bio->multi == 1) 663 goto ready; 664 wdccommand(chp, xfer->drive, WDCC_SETMULTI, 0, 0, 0, 665 ata_bio->multi, 0); 666 drvp->state = MULTIMODE_WAIT; 667 break; 668 669 case MULTIMODE_WAIT: 670 errstring = "setmulti"; 671 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY)) 672 goto timeout; 673 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 674 goto error; 675 /* fall through */ 676 677 case READY: 678 ready: 679 drvp->state = READY; 680 /* 681 * The drive is usable now 682 */ 683 xfer->c_intr = wdc_ata_bio_intr; 684 wdc_ata_bio_start(chp, xfer); 685 return 1; 686 } 687 688 if ((ata_bio->flags & ATA_POLL) == 0) { 689 chp->ch_flags |= WDCF_IRQ_WAIT; 690 timeout(wdctimeout, chp, ATA_DELAY / 1000 * hz); 691 } else { 692 goto again; 693 } 694 return 1; 695 696 timeout: 697 if ((xfer->c_flags & C_TIMEOU) == 0 ) { 698 return 0; /* IRQ was not for us */ 699 } 700 printf("%s:%d:%d: %s timed out\n", 701 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, errstring); 702 ata_bio->error = TIMEOUT; 703 drvp->state = 0; 704 wdc_ata_bio_done(chp, xfer); 705 return 0; 706 error: 707 printf("%s:%d:%d: %s ", 708 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 709 errstring); 710 if (chp->ch_status & WDCS_DWF) { 711 printf("drive fault\n"); 712 ata_bio->error = ERR_DF; 713 } else { 714 printf("error (%x)\n", chp->ch_error); 715 ata_bio->r_error = chp->ch_error; 716 ata_bio->error = ERROR; 717 } 718 drvp->state = 0; 719 wdc_ata_bio_done(chp, xfer); 720 return 1; 721 } 722 723 int 724 wdc_ata_err(chp, ata_bio) 725 struct channel_softc *chp; 726 struct ata_bio *ata_bio; 727 { 728 ata_bio->error = 0; 729 if (chp->ch_status & WDCS_BSY) { 730 ata_bio->error = TIMEOUT; 731 return WDC_ATA_ERR; 732 } 733 734 if (chp->ch_status & WDCS_DWF) { 735 ata_bio->error = ERR_DF; 736 return WDC_ATA_ERR; 737 } 738 739 if (chp->ch_status & WDCS_ERR) { 740 ata_bio->error = ERROR; 741 ata_bio->r_error = chp->ch_error; 742 if (ata_bio->r_error & (WDCE_BBK | WDCE_UNC | WDCE_IDNF | 743 WDCE_ABRT | WDCE_TK0NF | WDCE_AMNF)) 744 return WDC_ATA_ERR; 745 return WDC_ATA_NOERR; 746 } 747 748 if (chp->ch_status & WDCS_CORR) 749 ata_bio->flags |= ATA_CORR; 750 return WDC_ATA_NOERR; 751 } 752 753 int 754 wdc_ata_addref(drvp) 755 struct ata_drive_datas *drvp; 756 { 757 struct channel_softc *chp = drvp->chnl_softc; 758 759 return (wdc_addref(chp)); 760 } 761 762 void 763 wdc_ata_delref(drvp) 764 struct ata_drive_datas *drvp; 765 { 766 struct channel_softc *chp = drvp->chnl_softc; 767 768 wdc_delref(chp); 769 } 770
Indexes created Mon Sep 29 18:09:42 GMT 2025