ata_wdc.c revision 1.19.2.3
1 /* $NetBSD: ata_wdc.c,v 1.19.2.3 2000/07/07 17:33:46 he Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /*- 36 * Copyright (c) 1998 The NetBSD Foundation, Inc. 37 * All rights reserved. 38 * 39 * This code is derived from software contributed to The NetBSD Foundation 40 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by the NetBSD 53 * Foundation, Inc. and its contributors. 54 * 4. Neither the name of The NetBSD Foundation nor the names of its 55 * contributors may be used to endorse or promote products derived 56 * from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 59 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 60 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 61 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 62 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 63 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 64 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 65 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 66 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 67 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGE. 69 */ 70 71 #ifndef WDCDEBUG 72 #define WDCDEBUG 73 #endif /* WDCDEBUG */ 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/kernel.h> 78 #include <sys/file.h> 79 #include <sys/stat.h> 80 #include <sys/buf.h> 81 #include <sys/malloc.h> 82 #include <sys/device.h> 83 #include <sys/disklabel.h> 84 #include <sys/syslog.h> 85 #include <sys/proc.h> 86 87 #include <machine/intr.h> 88 #include <machine/bus.h> 89 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 90 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 91 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 92 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 93 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 94 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 95 96 #include <dev/ata/atareg.h> 97 #include <dev/ata/atavar.h> 98 #include <dev/ic/wdcreg.h> 99 #include <dev/ic/wdcvar.h> 100 #include <dev/ata/wdvar.h> 101 102 #define DEBUG_INTR 0x01 103 #define DEBUG_XFERS 0x02 104 #define DEBUG_STATUS 0x04 105 #define DEBUG_FUNCS 0x08 106 #define DEBUG_PROBE 0x10 107 #ifdef WDCDEBUG 108 int wdcdebug_wd_mask = 0; 109 #define WDCDEBUG_PRINT(args, level) \ 110 if (wdcdebug_wd_mask & (level)) \ 111 printf args 112 #else 113 #define WDCDEBUG_PRINT(args, level) 114 #endif 115 116 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 117 118 void wdc_ata_bio_start __P((struct channel_softc *,struct wdc_xfer *)); 119 void _wdc_ata_bio_start __P((struct channel_softc *,struct wdc_xfer *)); 120 int wdc_ata_bio_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 121 void wdc_ata_bio_done __P((struct channel_softc *, struct wdc_xfer *)); 122 int wdc_ata_ctrl_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 123 int wdc_ata_err __P((struct ata_drive_datas *, struct ata_bio *)); 124 #define WDC_ATA_NOERR 0x00 /* Drive doesn't report an error */ 125 #define WDC_ATA_RECOV 0x01 /* There was a recovered error */ 126 #define WDC_ATA_ERR 0x02 /* Drive reports an error */ 127 128 /* 129 * Handle block I/O operation. Return WDC_COMPLETE, WDC_QUEUED, or 130 * WDC_TRY_AGAIN. Must be called at splio(). 131 */ 132 int 133 wdc_ata_bio(drvp, ata_bio) 134 struct ata_drive_datas *drvp; 135 struct ata_bio *ata_bio; 136 { 137 struct wdc_xfer *xfer; 138 struct channel_softc *chp = drvp->chnl_softc; 139 140 xfer = wdc_get_xfer(WDC_NOSLEEP); 141 if (xfer == NULL) 142 return WDC_TRY_AGAIN; 143 if (ata_bio->flags & ATA_POLL) 144 xfer->c_flags |= C_POLL; 145 if ((drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) && 146 (ata_bio->flags & ATA_SINGLE) == 0) 147 xfer->c_flags |= C_DMA; 148 xfer->drive = drvp->drive; 149 xfer->cmd = ata_bio; 150 xfer->databuf = ata_bio->databuf; 151 xfer->c_bcount = ata_bio->bcount; 152 xfer->c_start = wdc_ata_bio_start; 153 xfer->c_intr = wdc_ata_bio_intr; 154 wdc_exec_xfer(chp, xfer); 155 return (ata_bio->flags & ATA_ITSDONE) ? WDC_COMPLETE : WDC_QUEUED; 156 } 157 158 void 159 wdc_ata_bio_start(chp, xfer) 160 struct channel_softc *chp; 161 struct wdc_xfer *xfer; 162 { 163 struct ata_bio *ata_bio = xfer->cmd; 164 WDCDEBUG_PRINT(("wdc_ata_bio_start %s:%d:%d\n", 165 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 166 DEBUG_XFERS); 167 168 /* start timeout machinery */ 169 if ((ata_bio->flags & ATA_POLL) == 0) 170 timeout(wdctimeout, chp, ATA_DELAY / 1000 * hz); 171 _wdc_ata_bio_start(chp, xfer); 172 } 173 174 void 175 _wdc_ata_bio_start(chp, xfer) 176 struct channel_softc *chp; 177 struct wdc_xfer *xfer; 178 { 179 struct ata_bio *ata_bio = xfer->cmd; 180 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; 181 u_int16_t cyl; 182 u_int8_t head, sect, cmd = 0; 183 int nblks; 184 int ata_delay; 185 int dma_flags = 0; 186 187 WDCDEBUG_PRINT(("_wdc_ata_bio_start %s:%d:%d\n", 188 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 189 DEBUG_INTR | DEBUG_XFERS); 190 /* Do control operations specially. */ 191 if (drvp->state < READY) { 192 /* 193 * Actually, we want to be careful not to mess with the control 194 * state if the device is currently busy, but we can assume 195 * that we never get to this point if that's the case. 196 */ 197 /* at this point, we should only be in RECAL state */ 198 if (drvp->state != RESET) { 199 printf("%s:%d:%d: bad state %d in _wdc_ata_bio_start\n", 200 chp->wdc->sc_dev.dv_xname, chp->channel, 201 xfer->drive, drvp->state); 202 panic("_wdc_ata_bio_start: bad state"); 203 } 204 drvp->state = RECAL; 205 xfer->c_intr = wdc_ata_ctrl_intr; 206 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 207 WDSD_IBM | (xfer->drive << 4)); 208 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY) != 0) 209 goto timeout; 210 wdccommandshort(chp, xfer->drive, WDCC_RECAL); 211 drvp->state = RECAL_WAIT; 212 if ((ata_bio->flags & ATA_POLL) == 0) { 213 chp->ch_flags |= WDCF_IRQ_WAIT; 214 } else { 215 /* Wait for at last 400ns for status bit to be valid */ 216 DELAY(1); 217 wdc_ata_ctrl_intr(chp, xfer, 0); 218 } 219 return; 220 } 221 222 if (xfer->c_flags & C_DMA) { 223 if (drvp->n_xfers <= NXFER) 224 drvp->n_xfers++; 225 dma_flags = (ata_bio->flags & ATA_READ) ? WDC_DMA_READ : 0; 226 } 227 if (ata_bio->flags & ATA_SINGLE) 228 ata_delay = ATA_DELAY; 229 else 230 ata_delay = ATA_DELAY; 231 again: 232 /* 233 * 234 * When starting a multi-sector transfer, or doing single-sector 235 * transfers... 236 */ 237 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 238 if (ata_bio->flags & ATA_SINGLE) 239 nblks = 1; 240 else 241 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 242 /* Check for bad sectors and adjust transfer, if necessary. */ 243 if ((ata_bio->lp->d_flags & D_BADSECT) != 0) { 244 long blkdiff; 245 int i; 246 for (i = 0; (blkdiff = ata_bio->badsect[i]) != -1; 247 i++) { 248 blkdiff -= ata_bio->blkno; 249 if (blkdiff < 0) 250 continue; 251 if (blkdiff == 0) { 252 /* Replace current block of transfer. */ 253 ata_bio->blkno = 254 ata_bio->lp->d_secperunit - 255 ata_bio->lp->d_nsectors - i - 1; 256 } 257 if (blkdiff < nblks) { 258 /* Bad block inside transfer. */ 259 ata_bio->flags |= ATA_SINGLE; 260 nblks = 1; 261 } 262 break; 263 } 264 /* Transfer is okay now. */ 265 } 266 if (ata_bio->flags & ATA_LBA) { 267 sect = (ata_bio->blkno >> 0) & 0xff; 268 cyl = (ata_bio->blkno >> 8) & 0xffff; 269 head = (ata_bio->blkno >> 24) & 0x0f; 270 head |= WDSD_LBA; 271 } else { 272 int blkno = ata_bio->blkno; 273 sect = blkno % ata_bio->lp->d_nsectors; 274 sect++; /* Sectors begin with 1, not 0. */ 275 blkno /= ata_bio->lp->d_nsectors; 276 head = blkno % ata_bio->lp->d_ntracks; 277 blkno /= ata_bio->lp->d_ntracks; 278 cyl = blkno; 279 head |= WDSD_CHS; 280 } 281 if (xfer->c_flags & C_DMA) { 282 ata_bio->nblks = nblks; 283 ata_bio->nbytes = xfer->c_bcount; 284 cmd = (ata_bio->flags & ATA_READ) ? 285 WDCC_READDMA : WDCC_WRITEDMA; 286 /* Init the DMA channel. */ 287 if ((*chp->wdc->dma_init)(chp->wdc->dma_arg, 288 chp->channel, xfer->drive, 289 (char *)xfer->databuf + xfer->c_skip, 290 ata_bio->nbytes, dma_flags) != 0) { 291 ata_bio->error = ERR_DMA; 292 ata_bio->r_error = 0; 293 wdc_ata_bio_done(chp, xfer); 294 return; 295 } 296 /* Initiate command */ 297 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 298 WDSD_IBM | (xfer->drive << 4)); 299 if (wait_for_ready(chp, ata_delay) < 0) 300 goto timeout; 301 wdccommand(chp, xfer->drive, cmd, cyl, 302 head, sect, nblks, 0); 303 /* start the DMA channel */ 304 (*chp->wdc->dma_start)(chp->wdc->dma_arg, 305 chp->channel, xfer->drive); 306 chp->ch_flags |= WDCF_DMA_WAIT; 307 /* wait for irq */ 308 goto intr; 309 } /* else not DMA */ 310 ata_bio->nblks = min(nblks, ata_bio->multi); 311 ata_bio->nbytes = ata_bio->nblks * ata_bio->lp->d_secsize; 312 if (ata_bio->nblks > 1 && (ata_bio->flags & ATA_SINGLE) == 0) { 313 cmd = (ata_bio->flags & ATA_READ) ? 314 WDCC_READMULTI : WDCC_WRITEMULTI; 315 } else { 316 cmd = (ata_bio->flags & ATA_READ) ? 317 WDCC_READ : WDCC_WRITE; 318 } 319 /* Initiate command! */ 320 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 321 WDSD_IBM | (xfer->drive << 4)); 322 if (wait_for_ready(chp, ata_delay) < 0) 323 goto timeout; 324 wdccommand(chp, xfer->drive, cmd, cyl, 325 head, sect, nblks, 326 (ata_bio->lp->d_type == DTYPE_ST506) ? 327 ata_bio->lp->d_precompcyl / 4 : 0); 328 } else if (ata_bio->nblks > 1) { 329 /* The number of blocks in the last stretch may be smaller. */ 330 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 331 if (ata_bio->nblks > nblks) { 332 ata_bio->nblks = nblks; 333 ata_bio->nbytes = xfer->c_bcount; 334 } 335 } 336 /* If this was a write and not using DMA, push the data. */ 337 if ((ata_bio->flags & ATA_READ) == 0) { 338 if (wait_for_drq(chp, ata_delay) != 0) { 339 printf("%s:%d:%d: timeout waiting for DRQ, " 340 "st=0x%02x, err=0x%02x\n", 341 chp->wdc->sc_dev.dv_xname, chp->channel, 342 xfer->drive, chp->ch_status, chp->ch_error); 343 if (wdc_ata_err(drvp, ata_bio) != WDC_ATA_ERR) 344 ata_bio->error = TIMEOUT; 345 wdc_ata_bio_done(chp, xfer); 346 return; 347 } 348 if (wdc_ata_err(drvp, ata_bio) == WDC_ATA_ERR) { 349 wdc_ata_bio_done(chp, xfer); 350 return; 351 } 352 if ((chp->wdc->cap & WDC_CAPABILITY_ATA_NOSTREAM)) { 353 if (drvp->drive_flags & DRIVE_CAP32) { 354 bus_space_write_multi_4(chp->data32iot, 355 chp->data32ioh, 0, 356 (u_int32_t *)((char *)xfer->databuf + 357 xfer->c_skip), 358 ata_bio->nbytes >> 2); 359 } else { 360 bus_space_write_multi_2(chp->cmd_iot, 361 chp->cmd_ioh, wd_data, 362 (u_int16_t *)((char *)xfer->databuf + 363 xfer->c_skip), 364 ata_bio->nbytes >> 1); 365 } 366 } else { 367 if (drvp->drive_flags & DRIVE_CAP32) { 368 bus_space_write_multi_stream_4(chp->data32iot, 369 chp->data32ioh, 0, 370 (u_int32_t *)((char *)xfer->databuf + 371 xfer->c_skip), 372 ata_bio->nbytes >> 2); 373 } else { 374 bus_space_write_multi_stream_2(chp->cmd_iot, 375 chp->cmd_ioh, wd_data, 376 (u_int16_t *)((char *)xfer->databuf + 377 xfer->c_skip), 378 ata_bio->nbytes >> 1); 379 } 380 } 381 } 382 383 intr: /* Wait for IRQ (either real or polled) */ 384 if ((ata_bio->flags & ATA_POLL) == 0) { 385 chp->ch_flags |= WDCF_IRQ_WAIT; 386 } else { 387 /* Wait for at last 400ns for status bit to be valid */ 388 delay(1); 389 if (chp->ch_flags & WDCF_DMA_WAIT) { 390 wdc_dmawait(chp, xfer, ATA_DELAY); 391 chp->ch_flags &= ~WDCF_DMA_WAIT; 392 } 393 wdc_ata_bio_intr(chp, xfer, 0); 394 if ((ata_bio->flags & ATA_ITSDONE) == 0) 395 goto again; 396 } 397 return; 398 timeout: 399 printf("%s:%d:%d: not ready, st=0x%02x, err=0x%02x\n", 400 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 401 chp->ch_status, chp->ch_error); 402 if (wdc_ata_err(drvp, ata_bio) != WDC_ATA_ERR) 403 ata_bio->error = TIMEOUT; 404 wdc_ata_bio_done(chp, xfer); 405 return; 406 } 407 408 int 409 wdc_ata_bio_intr(chp, xfer, irq) 410 struct channel_softc *chp; 411 struct wdc_xfer *xfer; 412 int irq; 413 { 414 struct ata_bio *ata_bio = xfer->cmd; 415 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; 416 int drv_err; 417 418 WDCDEBUG_PRINT(("wdc_ata_bio_intr %s:%d:%d\n", 419 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 420 DEBUG_INTR | DEBUG_XFERS); 421 422 423 /* Is it not a transfer, but a control operation? */ 424 if (drvp->state < READY) { 425 printf("%s:%d:%d: bad state %d in wdc_ata_bio_intr\n", 426 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 427 drvp->state); 428 panic("wdc_ata_bio_intr: bad state\n"); 429 } 430 431 /* 432 * if we missed an interrupt in a PIO transfer, reset and restart. 433 * Don't try to continue transfer, we may have missed cycles. 434 */ 435 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 436 ata_bio->error = TIMEOUT; 437 wdc_ata_bio_done(chp, xfer); 438 return 1; 439 } 440 441 /* Ack interrupt done by wait_for_unbusy */ 442 if (wait_for_unbusy(chp, 443 (irq == 0) ? ATA_DELAY : 0) < 0) { 444 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 445 return 0; /* IRQ was not for us */ 446 printf("%s:%d:%d: device timeout, c_bcount=%d, c_skip%d\n", 447 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 448 xfer->c_bcount, xfer->c_skip); 449 /* if we were using DMA, flag a DMA error */ 450 if (xfer->c_flags & C_DMA) { 451 ata_dmaerr(drvp); 452 } 453 ata_bio->error = TIMEOUT; 454 wdc_ata_bio_done(chp, xfer); 455 return 1; 456 } 457 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 458 chp->wdc->irqack(chp); 459 460 drv_err = wdc_ata_err(drvp, ata_bio); 461 462 /* If we were using DMA, Turn off the DMA channel and check for error */ 463 if (xfer->c_flags & C_DMA) { 464 if (ata_bio->flags & ATA_POLL) { 465 /* 466 * IDE drives deassert WDCS_BSY before transfer is 467 * complete when using DMA. Polling for DRQ to deassert 468 * is not enouth DRQ is not required to be 469 * asserted for DMA transfers, so poll for DRDY. 470 */ 471 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 472 ATA_DELAY) < 0) { 473 printf("%s:%d:%d: polled transfer timed out " 474 "(st=0x%x)\n", chp->wdc->sc_dev.dv_xname, 475 chp->channel, xfer->drive, chp->ch_status); 476 ata_bio->error = TIMEOUT; 477 drv_err = WDC_ATA_ERR; 478 } 479 } 480 if (chp->wdc->dma_status != 0) { 481 if (drv_err != WDC_ATA_ERR) { 482 ata_bio->error = ERR_DMA; 483 drv_err = WDC_ATA_ERR; 484 } 485 } 486 if (chp->ch_status & WDCS_DRQ) { 487 if (drv_err != WDC_ATA_ERR) { 488 printf("%s:%d:%d: intr with DRQ (st=0x%x)\n", 489 chp->wdc->sc_dev.dv_xname, chp->channel, 490 xfer->drive, chp->ch_status); 491 ata_bio->error = TIMEOUT; 492 drv_err = WDC_ATA_ERR; 493 } 494 } 495 if (drv_err != WDC_ATA_ERR) 496 goto end; 497 ata_dmaerr(drvp); 498 } 499 500 /* if we had an error, end */ 501 if (drv_err == WDC_ATA_ERR) { 502 wdc_ata_bio_done(chp, xfer); 503 return 1; 504 } 505 506 /* If this was a read and not using DMA, fetch the data. */ 507 if ((ata_bio->flags & ATA_READ) != 0) { 508 if ((chp->ch_status & WDCS_DRQ) != WDCS_DRQ) { 509 printf("%s:%d:%d: read intr before drq\n", 510 chp->wdc->sc_dev.dv_xname, chp->channel, 511 xfer->drive); 512 ata_bio->error = TIMEOUT; 513 wdc_ata_bio_done(chp, xfer); 514 return 1; 515 } 516 if ((chp->wdc->cap & WDC_CAPABILITY_ATA_NOSTREAM)) { 517 if (drvp->drive_flags & DRIVE_CAP32) { 518 bus_space_read_multi_4(chp->data32iot, 519 chp->data32ioh, 0, 520 (u_int32_t *)((char *)xfer->databuf + 521 xfer->c_skip), 522 ata_bio->nbytes >> 2); 523 } else { 524 bus_space_read_multi_2(chp->cmd_iot, 525 chp->cmd_ioh, wd_data, 526 (u_int16_t *)((char *)xfer->databuf + 527 xfer->c_skip), 528 ata_bio->nbytes >> 1); 529 } 530 } else { 531 if (drvp->drive_flags & DRIVE_CAP32) { 532 bus_space_read_multi_stream_4(chp->data32iot, 533 chp->data32ioh, 0, 534 (u_int32_t *)((char *)xfer->databuf + 535 xfer->c_skip), 536 ata_bio->nbytes >> 2); 537 } else { 538 bus_space_read_multi_stream_2(chp->cmd_iot, 539 chp->cmd_ioh, wd_data, 540 (u_int16_t *)((char *)xfer->databuf + 541 xfer->c_skip), 542 ata_bio->nbytes >> 1); 543 } 544 } 545 } 546 547 end: 548 ata_bio->blkno += ata_bio->nblks; 549 ata_bio->blkdone += ata_bio->nblks; 550 xfer->c_skip += ata_bio->nbytes; 551 xfer->c_bcount -= ata_bio->nbytes; 552 /* See if this transfer is complete. */ 553 if (xfer->c_bcount > 0) { 554 if ((ata_bio->flags & ATA_POLL) == 0) { 555 /* Start the next operation */ 556 _wdc_ata_bio_start(chp, xfer); 557 } else { 558 /* Let _wdc_ata_bio_start do the loop */ 559 return 1; 560 } 561 } else { /* Done with this transfer */ 562 ata_bio->error = NOERROR; 563 wdc_ata_bio_done(chp, xfer); 564 } 565 return 1; 566 } 567 568 void 569 wdc_ata_bio_done(chp, xfer) 570 struct channel_softc *chp; 571 struct wdc_xfer *xfer; 572 { 573 struct ata_bio *ata_bio = xfer->cmd; 574 int drive = xfer->drive; 575 576 WDCDEBUG_PRINT(("wdc_ata_bio_done %s:%d:%d: flags 0x%x\n", 577 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 578 (u_int)xfer->c_flags), 579 DEBUG_XFERS); 580 581 untimeout(wdctimeout, chp); 582 583 /* feed back residual bcount to our caller */ 584 ata_bio->bcount = xfer->c_bcount; 585 586 /* remove this command from xfer queue */ 587 wdc_free_xfer(chp, xfer); 588 589 ata_bio->flags |= ATA_ITSDONE; 590 if ((ata_bio->flags & ATA_POLL) == 0) { 591 WDCDEBUG_PRINT(("wdc_ata_done: wddone\n"), DEBUG_XFERS); 592 wddone(chp->ch_drive[drive].drv_softc); 593 } 594 WDCDEBUG_PRINT(("wdcstart from wdc_ata_done, flags 0x%x\n", 595 chp->ch_flags), DEBUG_XFERS); 596 wdcstart(chp); 597 } 598 599 /* 600 * Implement operations needed before read/write. 601 */ 602 int 603 wdc_ata_ctrl_intr(chp, xfer, irq) 604 struct channel_softc *chp; 605 struct wdc_xfer *xfer; 606 int irq; 607 { 608 struct ata_bio *ata_bio = xfer->cmd; 609 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; 610 char *errstring = NULL; 611 int delay = (irq == 0) ? ATA_DELAY : 0; 612 613 WDCDEBUG_PRINT(("wdc_ata_ctrl_intr: state %d\n", drvp->state), 614 DEBUG_FUNCS); 615 616 again: 617 switch (drvp->state) { 618 case RECAL: /* Should not be in this state here */ 619 panic("wdc_ata_ctrl_intr: state==RECAL"); 620 break; 621 622 case RECAL_WAIT: 623 errstring = "recal"; 624 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, delay)) 625 goto timeout; 626 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 627 chp->wdc->irqack(chp); 628 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 629 goto error; 630 /* fall through */ 631 632 case PIOMODE: 633 /* Don't try to set modes if controller can't be adjusted */ 634 if ((chp->wdc->cap & WDC_CAPABILITY_MODE) == 0) 635 goto geometry; 636 /* Also don't try if the drive didn't report its mode */ 637 if ((drvp->drive_flags & DRIVE_MODE) == 0) 638 goto geometry; 639 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 640 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 641 drvp->state = PIOMODE_WAIT; 642 break; 643 644 case PIOMODE_WAIT: 645 errstring = "piomode"; 646 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, delay)) 647 goto timeout; 648 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 649 chp->wdc->irqack(chp); 650 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 651 goto error; 652 /* fall through */ 653 654 case DMAMODE: 655 if (drvp->drive_flags & DRIVE_UDMA) { 656 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 657 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 658 } else if (drvp->drive_flags & DRIVE_DMA) { 659 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 660 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 661 } else { 662 goto geometry; 663 } 664 drvp->state = DMAMODE_WAIT; 665 break; 666 case DMAMODE_WAIT: 667 errstring = "dmamode"; 668 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, delay)) 669 goto timeout; 670 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 671 chp->wdc->irqack(chp); 672 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 673 goto error; 674 /* fall through */ 675 676 case GEOMETRY: 677 geometry: 678 if (ata_bio->flags & ATA_LBA) 679 goto multimode; 680 wdccommand(chp, xfer->drive, WDCC_IDP, 681 ata_bio->lp->d_ncylinders, 682 ata_bio->lp->d_ntracks - 1, 0, ata_bio->lp->d_nsectors, 683 (ata_bio->lp->d_type == DTYPE_ST506) ? 684 ata_bio->lp->d_precompcyl / 4 : 0); 685 drvp->state = GEOMETRY_WAIT; 686 break; 687 688 case GEOMETRY_WAIT: 689 errstring = "geometry"; 690 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, delay)) 691 goto timeout; 692 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 693 chp->wdc->irqack(chp); 694 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 695 goto error; 696 /* fall through */ 697 698 case MULTIMODE: 699 multimode: 700 if (ata_bio->multi == 1) 701 goto ready; 702 wdccommand(chp, xfer->drive, WDCC_SETMULTI, 0, 0, 0, 703 ata_bio->multi, 0); 704 drvp->state = MULTIMODE_WAIT; 705 break; 706 707 case MULTIMODE_WAIT: 708 errstring = "setmulti"; 709 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, delay)) 710 goto timeout; 711 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 712 chp->wdc->irqack(chp); 713 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 714 goto error; 715 /* fall through */ 716 717 case READY: 718 ready: 719 drvp->state = READY; 720 /* 721 * The drive is usable now 722 */ 723 xfer->c_intr = wdc_ata_bio_intr; 724 _wdc_ata_bio_start(chp, xfer); 725 return 1; 726 } 727 728 if ((ata_bio->flags & ATA_POLL) == 0) { 729 chp->ch_flags |= WDCF_IRQ_WAIT; 730 } else { 731 goto again; 732 } 733 return 1; 734 735 timeout: 736 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 737 return 0; /* IRQ was not for us */ 738 } 739 printf("%s:%d:%d: %s timed out\n", 740 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, errstring); 741 ata_bio->error = TIMEOUT; 742 drvp->state = 0; 743 wdc_ata_bio_done(chp, xfer); 744 return 0; 745 error: 746 printf("%s:%d:%d: %s ", 747 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 748 errstring); 749 if (chp->ch_status & WDCS_DWF) { 750 printf("drive fault\n"); 751 ata_bio->error = ERR_DF; 752 } else { 753 printf("error (%x)\n", chp->ch_error); 754 ata_bio->r_error = chp->ch_error; 755 ata_bio->error = ERROR; 756 } 757 drvp->state = 0; 758 wdc_ata_bio_done(chp, xfer); 759 return 1; 760 } 761 762 int 763 wdc_ata_err(drvp, ata_bio) 764 struct ata_drive_datas *drvp; 765 struct ata_bio *ata_bio; 766 { 767 struct channel_softc *chp = drvp->chnl_softc; 768 ata_bio->error = 0; 769 if (chp->ch_status & WDCS_BSY) { 770 ata_bio->error = TIMEOUT; 771 return WDC_ATA_ERR; 772 } 773 774 if (chp->ch_status & WDCS_DWF) { 775 ata_bio->error = ERR_DF; 776 return WDC_ATA_ERR; 777 } 778 779 if (chp->ch_status & WDCS_ERR) { 780 ata_bio->error = ERROR; 781 ata_bio->r_error = chp->ch_error; 782 if (drvp->drive_flags & DRIVE_UDMA && 783 (ata_bio->r_error & WDCE_CRC)) { 784 /* 785 * Record the CRC error, to avoid downgrading to 786 * multiword DMA 787 */ 788 drvp->drive_flags |= DRIVE_DMAERR; 789 } 790 if (ata_bio->r_error & (WDCE_BBK | WDCE_UNC | WDCE_IDNF | 791 WDCE_ABRT | WDCE_TK0NF | WDCE_AMNF)) 792 return WDC_ATA_ERR; 793 return WDC_ATA_NOERR; 794 } 795 796 if (chp->ch_status & WDCS_CORR) 797 ata_bio->flags |= ATA_CORR; 798 return WDC_ATA_NOERR; 799 } 800 801 int 802 wdc_ata_addref(drvp) 803 struct ata_drive_datas *drvp; 804 { 805 struct channel_softc *chp = drvp->chnl_softc; 806 807 return (wdc_addref(chp)); 808 } 809 810 void 811 wdc_ata_delref(drvp) 812 struct ata_drive_datas *drvp; 813 { 814 struct channel_softc *chp = drvp->chnl_softc; 815 816 wdc_delref(chp); 817 } 818
Indexes created Thu Oct 23 22:10:10 GMT 2025