ata_wdc.c revision 1.24
1 /* $NetBSD: ata_wdc.c,v 1.24 2000/03/23 07:01:27 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 */ 35 36 /*- 37 * Copyright (c) 1998 The NetBSD Foundation, Inc. 38 * All rights reserved. 39 * 40 * This code is derived from software contributed to The NetBSD Foundation 41 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by the NetBSD 54 * Foundation, Inc. and its contributors. 55 * 4. Neither the name of The NetBSD Foundation nor the names of its 56 * contributors may be used to endorse or promote products derived 57 * from this software without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 60 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 #ifndef WDCDEBUG 73 #define WDCDEBUG 74 #endif /* WDCDEBUG */ 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/file.h> 80 #include <sys/stat.h> 81 #include <sys/buf.h> 82 #include <sys/malloc.h> 83 #include <sys/device.h> 84 #include <sys/disklabel.h> 85 #include <sys/syslog.h> 86 #include <sys/proc.h> 87 88 #include <machine/intr.h> 89 #include <machine/bus.h> 90 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 91 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 92 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 93 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 94 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 95 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 96 97 #include <dev/ata/atareg.h> 98 #include <dev/ata/atavar.h> 99 #include <dev/ic/wdcreg.h> 100 #include <dev/ic/wdcvar.h> 101 #include <dev/ata/wdvar.h> 102 103 #define DEBUG_INTR 0x01 104 #define DEBUG_XFERS 0x02 105 #define DEBUG_STATUS 0x04 106 #define DEBUG_FUNCS 0x08 107 #define DEBUG_PROBE 0x10 108 #ifdef WDCDEBUG 109 int wdcdebug_wd_mask = 0; 110 #define WDCDEBUG_PRINT(args, level) \ 111 if (wdcdebug_wd_mask & (level)) \ 112 printf args 113 #else 114 #define WDCDEBUG_PRINT(args, level) 115 #endif 116 117 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 118 119 void wdc_ata_bio_start __P((struct channel_softc *,struct wdc_xfer *)); 120 void _wdc_ata_bio_start __P((struct channel_softc *,struct wdc_xfer *)); 121 int wdc_ata_bio_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 122 void wdc_ata_bio_kill_xfer __P((struct channel_softc *,struct wdc_xfer *)); 123 void wdc_ata_bio_done __P((struct channel_softc *, struct wdc_xfer *)); 124 int wdc_ata_ctrl_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 125 int wdc_ata_err __P((struct ata_drive_datas *, struct ata_bio *)); 126 #define WDC_ATA_NOERR 0x00 /* Drive doesn't report an error */ 127 #define WDC_ATA_RECOV 0x01 /* There was a recovered error */ 128 #define WDC_ATA_ERR 0x02 /* Drive reports an error */ 129 130 /* 131 * Handle block I/O operation. Return WDC_COMPLETE, WDC_QUEUED, or 132 * WDC_TRY_AGAIN. Must be called at splio(). 133 */ 134 int 135 wdc_ata_bio(drvp, ata_bio) 136 struct ata_drive_datas *drvp; 137 struct ata_bio *ata_bio; 138 { 139 struct wdc_xfer *xfer; 140 struct channel_softc *chp = drvp->chnl_softc; 141 142 xfer = wdc_get_xfer(WDC_NOSLEEP); 143 if (xfer == NULL) 144 return WDC_TRY_AGAIN; 145 if (ata_bio->flags & ATA_POLL) 146 xfer->c_flags |= C_POLL; 147 if ((drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) && 148 (ata_bio->flags & ATA_SINGLE) == 0) 149 xfer->c_flags |= C_DMA; 150 xfer->drive = drvp->drive; 151 xfer->cmd = ata_bio; 152 xfer->databuf = ata_bio->databuf; 153 xfer->c_bcount = ata_bio->bcount; 154 xfer->c_start = wdc_ata_bio_start; 155 xfer->c_intr = wdc_ata_bio_intr; 156 xfer->c_kill_xfer = wdc_ata_bio_kill_xfer; 157 wdc_exec_xfer(chp, xfer); 158 return (ata_bio->flags & ATA_ITSDONE) ? WDC_COMPLETE : WDC_QUEUED; 159 } 160 161 void 162 wdc_ata_bio_start(chp, xfer) 163 struct channel_softc *chp; 164 struct wdc_xfer *xfer; 165 { 166 struct ata_bio *ata_bio = xfer->cmd; 167 WDCDEBUG_PRINT(("wdc_ata_bio_start %s:%d:%d\n", 168 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 169 DEBUG_XFERS); 170 171 /* start timeout machinery */ 172 if ((ata_bio->flags & ATA_POLL) == 0) 173 callout_reset(&chp->ch_callout, ATA_DELAY / 1000 * hz, 174 wdctimeout, chp); 175 _wdc_ata_bio_start(chp, xfer); 176 } 177 178 void 179 _wdc_ata_bio_start(chp, xfer) 180 struct channel_softc *chp; 181 struct wdc_xfer *xfer; 182 { 183 struct ata_bio *ata_bio = xfer->cmd; 184 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; 185 u_int16_t cyl; 186 u_int8_t head, sect, cmd = 0; 187 int nblks; 188 int ata_delay; 189 int dma_flags = 0; 190 191 WDCDEBUG_PRINT(("_wdc_ata_bio_start %s:%d:%d\n", 192 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 193 DEBUG_INTR | DEBUG_XFERS); 194 /* Do control operations specially. */ 195 if (drvp->state < READY) { 196 /* 197 * Actually, we want to be careful not to mess with the control 198 * state if the device is currently busy, but we can assume 199 * that we never get to this point if that's the case. 200 */ 201 /* at this point, we should only be in RECAL state */ 202 if (drvp->state != RECAL) { 203 printf("%s:%d:%d: bad state %d in _wdc_ata_bio_start\n", 204 chp->wdc->sc_dev.dv_xname, chp->channel, 205 xfer->drive, drvp->state); 206 panic("_wdc_ata_bio_start: bad state"); 207 } 208 xfer->c_intr = wdc_ata_ctrl_intr; 209 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 210 WDSD_IBM | (xfer->drive << 4)); 211 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY) != 0) 212 goto timeout; 213 wdccommandshort(chp, xfer->drive, WDCC_RECAL); 214 drvp->state = RECAL_WAIT; 215 if ((ata_bio->flags & ATA_POLL) == 0) { 216 chp->ch_flags |= WDCF_IRQ_WAIT; 217 } else { 218 /* Wait for at last 400ns for status bit to be valid */ 219 DELAY(1); 220 wdc_ata_ctrl_intr(chp, xfer, 0); 221 } 222 return; 223 } 224 225 if (xfer->c_flags & C_DMA) { 226 if (drvp->n_xfers <= NXFER) 227 drvp->n_xfers++; 228 dma_flags = (ata_bio->flags & ATA_READ) ? WDC_DMA_READ : 0; 229 dma_flags |= (ata_bio->flags & ATA_POLL) ? WDC_DMA_POLL : 0; 230 } 231 if (ata_bio->flags & ATA_SINGLE) 232 ata_delay = ATA_DELAY; 233 else 234 ata_delay = ATA_DELAY; 235 again: 236 /* 237 * 238 * When starting a multi-sector transfer, or doing single-sector 239 * transfers... 240 */ 241 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 242 if (ata_bio->flags & ATA_SINGLE) 243 nblks = 1; 244 else 245 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 246 /* Check for bad sectors and adjust transfer, if necessary. */ 247 if ((ata_bio->lp->d_flags & D_BADSECT) != 0) { 248 long blkdiff; 249 int i; 250 for (i = 0; (blkdiff = ata_bio->badsect[i]) != -1; 251 i++) { 252 blkdiff -= ata_bio->blkno; 253 if (blkdiff < 0) 254 continue; 255 if (blkdiff == 0) { 256 /* Replace current block of transfer. */ 257 ata_bio->blkno = 258 ata_bio->lp->d_secperunit - 259 ata_bio->lp->d_nsectors - i - 1; 260 } 261 if (blkdiff < nblks) { 262 /* Bad block inside transfer. */ 263 ata_bio->flags |= ATA_SINGLE; 264 nblks = 1; 265 } 266 break; 267 } 268 /* Transfer is okay now. */ 269 } 270 if (ata_bio->flags & ATA_LBA) { 271 sect = (ata_bio->blkno >> 0) & 0xff; 272 cyl = (ata_bio->blkno >> 8) & 0xffff; 273 head = (ata_bio->blkno >> 24) & 0x0f; 274 head |= WDSD_LBA; 275 } else { 276 int blkno = ata_bio->blkno; 277 sect = blkno % ata_bio->lp->d_nsectors; 278 sect++; /* Sectors begin with 1, not 0. */ 279 blkno /= ata_bio->lp->d_nsectors; 280 head = blkno % ata_bio->lp->d_ntracks; 281 blkno /= ata_bio->lp->d_ntracks; 282 cyl = blkno; 283 head |= WDSD_CHS; 284 } 285 if (xfer->c_flags & C_DMA) { 286 ata_bio->nblks = nblks; 287 ata_bio->nbytes = xfer->c_bcount; 288 cmd = (ata_bio->flags & ATA_READ) ? 289 WDCC_READDMA : WDCC_WRITEDMA; 290 nblks = ata_bio->nblks; 291 /* Init the DMA channel. */ 292 if ((*chp->wdc->dma_init)(chp->wdc->dma_arg, 293 chp->channel, xfer->drive, 294 (char *)xfer->databuf + xfer->c_skip, 295 ata_bio->nbytes, dma_flags) != 0) { 296 ata_bio->error = ERR_DMA; 297 ata_bio->r_error = 0; 298 wdc_ata_bio_done(chp, xfer); 299 return; 300 } 301 /* Initiate command */ 302 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 303 WDSD_IBM | (xfer->drive << 4)); 304 if (wait_for_ready(chp, ata_delay) < 0) 305 goto timeout; 306 wdccommand(chp, xfer->drive, cmd, cyl, 307 head, sect, nblks, 0); 308 /* start the DMA channel */ 309 (*chp->wdc->dma_start)(chp->wdc->dma_arg, 310 chp->channel, xfer->drive, dma_flags); 311 /* wait for irq */ 312 goto intr; 313 } /* else not DMA */ 314 ata_bio->nblks = min(nblks, ata_bio->multi); 315 ata_bio->nbytes = ata_bio->nblks * ata_bio->lp->d_secsize; 316 if (ata_bio->nblks > 1 && (ata_bio->flags & ATA_SINGLE) == 0) { 317 cmd = (ata_bio->flags & ATA_READ) ? 318 WDCC_READMULTI : WDCC_WRITEMULTI; 319 } else { 320 cmd = (ata_bio->flags & ATA_READ) ? 321 WDCC_READ : WDCC_WRITE; 322 } 323 /* Initiate command! */ 324 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 325 WDSD_IBM | (xfer->drive << 4)); 326 if (wait_for_ready(chp, ata_delay) < 0) 327 goto timeout; 328 wdccommand(chp, xfer->drive, cmd, cyl, 329 head, sect, nblks, 330 (ata_bio->lp->d_type == DTYPE_ST506) ? 331 ata_bio->lp->d_precompcyl / 4 : 0); 332 } else if (ata_bio->nblks > 1) { 333 /* The number of blocks in the last stretch may be smaller. */ 334 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 335 if (ata_bio->nblks > nblks) { 336 ata_bio->nblks = nblks; 337 ata_bio->nbytes = xfer->c_bcount; 338 } 339 } 340 /* If this was a write and not using DMA, push the data. */ 341 if ((ata_bio->flags & ATA_READ) == 0) { 342 if (wait_for_drq(chp, ata_delay) != 0) { 343 printf("%s:%d:%d: timeout waiting for DRQ, " 344 "st=0x%02x, err=0x%02x\n", 345 chp->wdc->sc_dev.dv_xname, chp->channel, 346 xfer->drive, chp->ch_status, chp->ch_error); 347 if (wdc_ata_err(drvp, ata_bio) != WDC_ATA_ERR) 348 ata_bio->error = TIMEOUT; 349 wdc_ata_bio_done(chp, xfer); 350 return; 351 } 352 if (wdc_ata_err(drvp, ata_bio) == WDC_ATA_ERR) { 353 wdc_ata_bio_done(chp, xfer); 354 return; 355 } 356 if ((chp->wdc->cap & WDC_CAPABILITY_ATA_NOSTREAM)) { 357 if (drvp->drive_flags & DRIVE_CAP32) { 358 bus_space_write_multi_4(chp->data32iot, 359 chp->data32ioh, 0, 360 (u_int32_t *)((char *)xfer->databuf + 361 xfer->c_skip), 362 ata_bio->nbytes >> 2); 363 } else { 364 bus_space_write_multi_2(chp->cmd_iot, 365 chp->cmd_ioh, wd_data, 366 (u_int16_t *)((char *)xfer->databuf + 367 xfer->c_skip), 368 ata_bio->nbytes >> 1); 369 } 370 } else { 371 if (drvp->drive_flags & DRIVE_CAP32) { 372 bus_space_write_multi_stream_4(chp->data32iot, 373 chp->data32ioh, 0, 374 (u_int32_t *)((char *)xfer->databuf + 375 xfer->c_skip), 376 ata_bio->nbytes >> 2); 377 } else { 378 bus_space_write_multi_stream_2(chp->cmd_iot, 379 chp->cmd_ioh, wd_data, 380 (u_int16_t *)((char *)xfer->databuf + 381 xfer->c_skip), 382 ata_bio->nbytes >> 1); 383 } 384 } 385 } 386 387 intr: /* Wait for IRQ (either real or polled) */ 388 if ((ata_bio->flags & ATA_POLL) == 0) { 389 chp->ch_flags |= WDCF_IRQ_WAIT; 390 } else { 391 /* Wait for at last 400ns for status bit to be valid */ 392 delay(1); 393 wdc_ata_bio_intr(chp, xfer, 0); 394 if ((ata_bio->flags & ATA_ITSDONE) == 0) 395 goto again; 396 } 397 return; 398 timeout: 399 printf("%s:%d:%d: not ready, st=0x%02x, err=0x%02x\n", 400 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 401 chp->ch_status, chp->ch_error); 402 if (wdc_ata_err(drvp, ata_bio) != WDC_ATA_ERR) 403 ata_bio->error = TIMEOUT; 404 wdc_ata_bio_done(chp, xfer); 405 return; 406 } 407 408 int 409 wdc_ata_bio_intr(chp, xfer, irq) 410 struct channel_softc *chp; 411 struct wdc_xfer *xfer; 412 int irq; 413 { 414 struct ata_bio *ata_bio = xfer->cmd; 415 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; 416 int drv_err; 417 int dma_flags = 0; 418 419 WDCDEBUG_PRINT(("wdc_ata_bio_intr %s:%d:%d\n", 420 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 421 DEBUG_INTR | DEBUG_XFERS); 422 423 424 /* Is it not a transfer, but a control operation? */ 425 if (drvp->state < READY) { 426 printf("%s:%d:%d: bad state %d in wdc_ata_bio_intr\n", 427 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 428 drvp->state); 429 panic("wdc_ata_bio_intr: bad state\n"); 430 } 431 432 if (xfer->c_flags & C_DMA) { 433 dma_flags = (ata_bio->flags & ATA_READ) ? WDC_DMA_READ : 0; 434 dma_flags |= (ata_bio->flags & ATA_POLL) ? WDC_DMA_POLL : 0; 435 } 436 437 /* 438 * if we missed an interrupt in a PIO transfer, reset and restart. 439 * Don't try to continue transfer, we may have missed cycles. 440 */ 441 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 442 ata_bio->error = TIMEOUT; 443 wdc_ata_bio_done(chp, xfer); 444 return 1; 445 } 446 447 /* Ack interrupt done by wait_for_unbusy */ 448 if (wait_for_unbusy(chp, 449 (irq == 0) ? ATA_DELAY : 0) < 0) { 450 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 451 return 0; /* IRQ was not for us */ 452 printf("%s:%d:%d: device timeout, c_bcount=%d, c_skip%d\n", 453 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 454 xfer->c_bcount, xfer->c_skip); 455 /* if we were using DMA, turn off DMA channel */ 456 if (xfer->c_flags & C_DMA) { 457 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 458 chp->channel, xfer->drive, dma_flags); 459 ata_dmaerr(drvp); 460 } 461 ata_bio->error = TIMEOUT; 462 wdc_ata_bio_done(chp, xfer); 463 return 1; 464 } 465 466 drv_err = wdc_ata_err(drvp, ata_bio); 467 468 /* If we were using DMA, Turn off the DMA channel and check for error */ 469 if (xfer->c_flags & C_DMA) { 470 if (ata_bio->flags & ATA_POLL) { 471 /* 472 * IDE drives deassert WDCS_BSY before transfer is 473 * complete when using DMA. Polling for DRQ to deassert 474 * is not enouth DRQ is not required to be 475 * asserted for DMA transfers, so poll for DRDY. 476 */ 477 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 478 ATA_DELAY) < 0) { 479 printf("%s:%d:%d: polled transfer timed out " 480 "(st=0x%x)\n", chp->wdc->sc_dev.dv_xname, 481 chp->channel, xfer->drive, chp->ch_status); 482 ata_bio->error = TIMEOUT; 483 drv_err = WDC_ATA_ERR; 484 } 485 } 486 if ((*chp->wdc->dma_finish)(chp->wdc->dma_arg, 487 chp->channel, xfer->drive, dma_flags) != 0) { 488 if (drv_err != WDC_ATA_ERR) { 489 ata_bio->error = ERR_DMA; 490 drv_err = WDC_ATA_ERR; 491 } 492 } 493 if (chp->ch_status & WDCS_DRQ) { 494 if (drv_err != WDC_ATA_ERR) { 495 printf("%s:%d:%d: intr with DRQ (st=0x%x)\n", 496 chp->wdc->sc_dev.dv_xname, chp->channel, 497 xfer->drive, chp->ch_status); 498 ata_bio->error = TIMEOUT; 499 drv_err = WDC_ATA_ERR; 500 } 501 } 502 if (drv_err != WDC_ATA_ERR) 503 goto end; 504 ata_dmaerr(drvp); 505 } 506 507 /* if we had an error, end */ 508 if (drv_err == WDC_ATA_ERR) { 509 wdc_ata_bio_done(chp, xfer); 510 return 1; 511 } 512 513 /* If this was a read and not using DMA, fetch the data. */ 514 if ((ata_bio->flags & ATA_READ) != 0) { 515 if ((chp->ch_status & WDCS_DRQ) != WDCS_DRQ) { 516 printf("%s:%d:%d: read intr before drq\n", 517 chp->wdc->sc_dev.dv_xname, chp->channel, 518 xfer->drive); 519 ata_bio->error = TIMEOUT; 520 wdc_ata_bio_done(chp, xfer); 521 return 1; 522 } 523 if ((chp->wdc->cap & WDC_CAPABILITY_ATA_NOSTREAM)) { 524 if (drvp->drive_flags & DRIVE_CAP32) { 525 bus_space_read_multi_4(chp->data32iot, 526 chp->data32ioh, 0, 527 (u_int32_t *)((char *)xfer->databuf + 528 xfer->c_skip), 529 ata_bio->nbytes >> 2); 530 } else { 531 bus_space_read_multi_2(chp->cmd_iot, 532 chp->cmd_ioh, wd_data, 533 (u_int16_t *)((char *)xfer->databuf + 534 xfer->c_skip), 535 ata_bio->nbytes >> 1); 536 } 537 } else { 538 if (drvp->drive_flags & DRIVE_CAP32) { 539 bus_space_read_multi_stream_4(chp->data32iot, 540 chp->data32ioh, 0, 541 (u_int32_t *)((char *)xfer->databuf + 542 xfer->c_skip), 543 ata_bio->nbytes >> 2); 544 } else { 545 bus_space_read_multi_stream_2(chp->cmd_iot, 546 chp->cmd_ioh, wd_data, 547 (u_int16_t *)((char *)xfer->databuf + 548 xfer->c_skip), 549 ata_bio->nbytes >> 1); 550 } 551 } 552 } 553 554 end: 555 ata_bio->blkno += ata_bio->nblks; 556 ata_bio->blkdone += ata_bio->nblks; 557 xfer->c_skip += ata_bio->nbytes; 558 xfer->c_bcount -= ata_bio->nbytes; 559 /* See if this transfer is complete. */ 560 if (xfer->c_bcount > 0) { 561 if ((ata_bio->flags & ATA_POLL) == 0) { 562 /* Start the next operation */ 563 _wdc_ata_bio_start(chp, xfer); 564 } else { 565 /* Let _wdc_ata_bio_start do the loop */ 566 return 1; 567 } 568 } else { /* Done with this transfer */ 569 ata_bio->error = NOERROR; 570 wdc_ata_bio_done(chp, xfer); 571 } 572 return 1; 573 } 574 575 void 576 wdc_ata_kill_pending(drvp) 577 struct ata_drive_datas *drvp; 578 { 579 struct channel_softc *chp = drvp->chnl_softc; 580 581 wdc_kill_pending(chp); 582 } 583 584 void 585 wdc_ata_bio_kill_xfer(chp, xfer) 586 struct channel_softc *chp; 587 struct wdc_xfer *xfer; 588 { 589 struct ata_bio *ata_bio = xfer->cmd; 590 int drive = xfer->drive; 591 592 callout_stop(&chp->ch_callout); 593 /* remove this command from xfer queue */ 594 wdc_free_xfer(chp, xfer); 595 596 ata_bio->flags |= ATA_ITSDONE; 597 ata_bio->error = ERR_NODEV; 598 ata_bio->r_error = WDCE_ABRT; 599 if ((ata_bio->flags & ATA_POLL) == 0) { 600 WDCDEBUG_PRINT(("wdc_ata_done: wddone\n"), DEBUG_XFERS); 601 wddone(chp->ch_drive[drive].drv_softc); 602 } 603 } 604 605 void 606 wdc_ata_bio_done(chp, xfer) 607 struct channel_softc *chp; 608 struct wdc_xfer *xfer; 609 { 610 struct ata_bio *ata_bio = xfer->cmd; 611 int drive = xfer->drive; 612 613 WDCDEBUG_PRINT(("wdc_ata_bio_done %s:%d:%d: flags 0x%x\n", 614 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 615 (u_int)xfer->c_flags), 616 DEBUG_XFERS); 617 618 callout_stop(&chp->ch_callout); 619 620 /* feed back residual bcount to our caller */ 621 ata_bio->bcount = xfer->c_bcount; 622 623 /* remove this command from xfer queue */ 624 wdc_free_xfer(chp, xfer); 625 626 ata_bio->flags |= ATA_ITSDONE; 627 if ((ata_bio->flags & ATA_POLL) == 0) { 628 WDCDEBUG_PRINT(("wdc_ata_done: wddone\n"), DEBUG_XFERS); 629 wddone(chp->ch_drive[drive].drv_softc); 630 } 631 WDCDEBUG_PRINT(("wdcstart from wdc_ata_done, flags 0x%x\n", 632 chp->ch_flags), DEBUG_XFERS); 633 wdcstart(chp); 634 } 635 636 /* 637 * Implement operations needed before read/write. 638 */ 639 int 640 wdc_ata_ctrl_intr(chp, xfer, irq) 641 struct channel_softc *chp; 642 struct wdc_xfer *xfer; 643 int irq; 644 { 645 struct ata_bio *ata_bio = xfer->cmd; 646 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; 647 char *errstring = NULL; 648 int delay = (irq == 0) ? ATA_DELAY : 0; 649 650 WDCDEBUG_PRINT(("wdc_ata_ctrl_intr: state %d\n", drvp->state), 651 DEBUG_FUNCS); 652 653 again: 654 switch (drvp->state) { 655 case RECAL: /* Should not be in this state here */ 656 panic("wdc_ata_ctrl_intr: state==RECAL"); 657 break; 658 659 case RECAL_WAIT: 660 errstring = "recal"; 661 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, delay)) 662 goto timeout; 663 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 664 goto error; 665 /* fall through */ 666 667 case PIOMODE: 668 /* Don't try to set modes if controller can't be adjusted */ 669 if ((chp->wdc->cap & WDC_CAPABILITY_MODE) == 0) 670 goto geometry; 671 /* Also don't try if the drive didn't report its mode */ 672 if ((drvp->drive_flags & DRIVE_MODE) == 0) 673 goto geometry; 674 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 675 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 676 drvp->state = PIOMODE_WAIT; 677 break; 678 679 case PIOMODE_WAIT: 680 errstring = "piomode"; 681 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, delay)) 682 goto timeout; 683 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 684 goto error; 685 /* fall through */ 686 687 case DMAMODE: 688 if (drvp->drive_flags & DRIVE_UDMA) { 689 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 690 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 691 } else if (drvp->drive_flags & DRIVE_DMA) { 692 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 693 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 694 } else { 695 goto geometry; 696 } 697 drvp->state = DMAMODE_WAIT; 698 break; 699 case DMAMODE_WAIT: 700 errstring = "dmamode"; 701 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, delay)) 702 goto timeout; 703 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 704 goto error; 705 /* fall through */ 706 707 case GEOMETRY: 708 geometry: 709 if (ata_bio->flags & ATA_LBA) 710 goto multimode; 711 wdccommand(chp, xfer->drive, WDCC_IDP, 712 ata_bio->lp->d_ncylinders, 713 ata_bio->lp->d_ntracks - 1, 0, ata_bio->lp->d_nsectors, 714 (ata_bio->lp->d_type == DTYPE_ST506) ? 715 ata_bio->lp->d_precompcyl / 4 : 0); 716 drvp->state = GEOMETRY_WAIT; 717 break; 718 719 case GEOMETRY_WAIT: 720 errstring = "geometry"; 721 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, delay)) 722 goto timeout; 723 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 724 goto error; 725 /* fall through */ 726 727 case MULTIMODE: 728 multimode: 729 if (ata_bio->multi == 1) 730 goto ready; 731 wdccommand(chp, xfer->drive, WDCC_SETMULTI, 0, 0, 0, 732 ata_bio->multi, 0); 733 drvp->state = MULTIMODE_WAIT; 734 break; 735 736 case MULTIMODE_WAIT: 737 errstring = "setmulti"; 738 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, delay)) 739 goto timeout; 740 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 741 goto error; 742 /* fall through */ 743 744 case READY: 745 ready: 746 drvp->state = READY; 747 /* 748 * The drive is usable now 749 */ 750 xfer->c_intr = wdc_ata_bio_intr; 751 _wdc_ata_bio_start(chp, xfer); 752 return 1; 753 } 754 755 if ((ata_bio->flags & ATA_POLL) == 0) { 756 chp->ch_flags |= WDCF_IRQ_WAIT; 757 } else { 758 goto again; 759 } 760 return 1; 761 762 timeout: 763 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 764 return 0; /* IRQ was not for us */ 765 } 766 printf("%s:%d:%d: %s timed out\n", 767 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, errstring); 768 ata_bio->error = TIMEOUT; 769 drvp->state = 0; 770 wdc_ata_bio_done(chp, xfer); 771 return 0; 772 error: 773 printf("%s:%d:%d: %s ", 774 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 775 errstring); 776 if (chp->ch_status & WDCS_DWF) { 777 printf("drive fault\n"); 778 ata_bio->error = ERR_DF; 779 } else { 780 printf("error (%x)\n", chp->ch_error); 781 ata_bio->r_error = chp->ch_error; 782 ata_bio->error = ERROR; 783 } 784 drvp->state = 0; 785 wdc_ata_bio_done(chp, xfer); 786 return 1; 787 } 788 789 int 790 wdc_ata_err(drvp, ata_bio) 791 struct ata_drive_datas *drvp; 792 struct ata_bio *ata_bio; 793 { 794 struct channel_softc *chp = drvp->chnl_softc; 795 ata_bio->error = 0; 796 if (chp->ch_status & WDCS_BSY) { 797 ata_bio->error = TIMEOUT; 798 return WDC_ATA_ERR; 799 } 800 801 if (chp->ch_status & WDCS_DWF) { 802 ata_bio->error = ERR_DF; 803 return WDC_ATA_ERR; 804 } 805 806 if (chp->ch_status & WDCS_ERR) { 807 ata_bio->error = ERROR; 808 ata_bio->r_error = chp->ch_error; 809 if (drvp->drive_flags & DRIVE_UDMA && 810 (ata_bio->r_error & WDCE_CRC)) { 811 /* 812 * Record the CRC error, to avoid downgrading to 813 * multiword DMA 814 */ 815 drvp->drive_flags |= DRIVE_DMAERR; 816 } 817 if (ata_bio->r_error & (WDCE_BBK | WDCE_UNC | WDCE_IDNF | 818 WDCE_ABRT | WDCE_TK0NF | WDCE_AMNF)) 819 return WDC_ATA_ERR; 820 return WDC_ATA_NOERR; 821 } 822 823 if (chp->ch_status & WDCS_CORR) 824 ata_bio->flags |= ATA_CORR; 825 return WDC_ATA_NOERR; 826 } 827 828 int 829 wdc_ata_addref(drvp) 830 struct ata_drive_datas *drvp; 831 { 832 struct channel_softc *chp = drvp->chnl_softc; 833 834 return (wdc_addref(chp)); 835 } 836 837 void 838 wdc_ata_delref(drvp) 839 struct ata_drive_datas *drvp; 840 { 841 struct channel_softc *chp = drvp->chnl_softc; 842 843 wdc_delref(chp); 844 } 845
Indexes created Mon Sep 29 21:09:56 GMT 2025