ata_wdc.c revision 1.55
1 /* $NetBSD: ata_wdc.c,v 1.55 2004/06/01 19:32:30 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: ata_wdc.c,v 1.55 2004/06/01 19:32:30 mycroft Exp $"); 70 71 #ifndef WDCDEBUG 72 #define WDCDEBUG 73 #endif /* WDCDEBUG */ 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/kernel.h> 78 #include <sys/file.h> 79 #include <sys/stat.h> 80 #include <sys/buf.h> 81 #include <sys/malloc.h> 82 #include <sys/device.h> 83 #include <sys/disklabel.h> 84 #include <sys/syslog.h> 85 #include <sys/proc.h> 86 87 #include <machine/intr.h> 88 #include <machine/bus.h> 89 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 90 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 91 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 92 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 93 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 94 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 95 96 #include <dev/ata/atareg.h> 97 #include <dev/ata/atavar.h> 98 #include <dev/ic/wdcreg.h> 99 #include <dev/ic/wdcvar.h> 100 101 #define DEBUG_INTR 0x01 102 #define DEBUG_XFERS 0x02 103 #define DEBUG_STATUS 0x04 104 #define DEBUG_FUNCS 0x08 105 #define DEBUG_PROBE 0x10 106 #ifdef WDCDEBUG 107 extern int wdcdebug_wd_mask; /* inited in wd.c */ 108 #define WDCDEBUG_PRINT(args, level) \ 109 if (wdcdebug_wd_mask & (level)) \ 110 printf args 111 #else 112 #define WDCDEBUG_PRINT(args, level) 113 #endif 114 115 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 116 117 static int wdc_ata_bio(struct ata_drive_datas*, struct ata_bio*); 118 static void wdc_ata_bio_start(struct wdc_channel *,struct ata_xfer *); 119 static void _wdc_ata_bio_start(struct wdc_channel *,struct ata_xfer *); 120 static int wdc_ata_bio_intr(struct wdc_channel *, struct ata_xfer *, 121 int); 122 static void wdc_ata_bio_kill_xfer(struct wdc_channel *,struct ata_xfer *); 123 static void wdc_ata_bio_done(struct wdc_channel *, struct ata_xfer *); 124 static int wdc_ata_err(struct ata_drive_datas *, struct ata_bio *); 125 #define WDC_ATA_NOERR 0x00 /* Drive doesn't report an error */ 126 #define WDC_ATA_RECOV 0x01 /* There was a recovered error */ 127 #define WDC_ATA_ERR 0x02 /* Drive reports an error */ 128 static int wdc_ata_addref(struct ata_drive_datas *); 129 static void wdc_ata_delref(struct ata_drive_datas *); 130 static void wdc_ata_kill_pending(struct ata_drive_datas *); 131 132 const struct ata_bustype wdc_ata_bustype = { 133 SCSIPI_BUSTYPE_ATA, 134 wdc_ata_bio, 135 wdc_reset_channel, 136 wdc_exec_command, 137 ata_get_params, 138 wdc_ata_addref, 139 wdc_ata_delref, 140 wdc_ata_kill_pending, 141 }; 142 143 /* 144 * Convert a 32 bit command to a 48 bit command. 145 */ 146 static __inline 147 int to48(int cmd32) 148 { 149 switch (cmd32) { 150 case WDCC_READ: 151 return WDCC_READ_EXT; 152 case WDCC_WRITE: 153 return WDCC_WRITE_EXT; 154 case WDCC_READMULTI: 155 return WDCC_READMULTI_EXT; 156 case WDCC_WRITEMULTI: 157 return WDCC_WRITEMULTI_EXT; 158 case WDCC_READDMA: 159 return WDCC_READDMA_EXT; 160 case WDCC_WRITEDMA: 161 return WDCC_WRITEDMA_EXT; 162 default: 163 panic("ata_wdc: illegal 32 bit command %d", cmd32); 164 /*NOTREACHED*/ 165 } 166 } 167 168 /* 169 * Handle block I/O operation. Return WDC_COMPLETE, WDC_QUEUED, or 170 * WDC_TRY_AGAIN. Must be called at splbio(). 171 */ 172 static int 173 wdc_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 174 { 175 struct ata_xfer *xfer; 176 struct wdc_channel *chp = drvp->chnl_softc; 177 struct wdc_softc *wdc = chp->ch_wdc; 178 179 xfer = wdc_get_xfer(WDC_NOSLEEP); 180 if (xfer == NULL) 181 return WDC_TRY_AGAIN; 182 if (wdc->cap & WDC_CAPABILITY_NOIRQ) 183 ata_bio->flags |= ATA_POLL; 184 if (ata_bio->flags & ATA_POLL) 185 xfer->c_flags |= C_POLL; 186 if ((drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) && 187 (ata_bio->flags & ATA_SINGLE) == 0) 188 xfer->c_flags |= C_DMA; 189 xfer->c_drive = drvp->drive; 190 xfer->c_cmd = ata_bio; 191 xfer->c_databuf = ata_bio->databuf; 192 xfer->c_bcount = ata_bio->bcount; 193 xfer->c_start = wdc_ata_bio_start; 194 xfer->c_intr = wdc_ata_bio_intr; 195 xfer->c_kill_xfer = wdc_ata_bio_kill_xfer; 196 wdc_exec_xfer(chp, xfer); 197 return (ata_bio->flags & ATA_ITSDONE) ? WDC_COMPLETE : WDC_QUEUED; 198 } 199 200 static void 201 wdc_ata_bio_start(struct wdc_channel *chp, struct ata_xfer *xfer) 202 { 203 struct wdc_softc *wdc = chp->ch_wdc; 204 struct ata_bio *ata_bio = xfer->c_cmd; 205 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 206 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 207 char *errstring; 208 209 WDCDEBUG_PRINT(("wdc_ata_bio_start %s:%d:%d\n", 210 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 211 DEBUG_XFERS); 212 213 /* Do control operations specially. */ 214 if (__predict_false(drvp->state < READY)) { 215 /* 216 * Actually, we want to be careful not to mess with the control 217 * state if the device is currently busy, but we can assume 218 * that we never get to this point if that's the case. 219 */ 220 /* If it's not a polled command, we need the kenrel thread */ 221 if ((xfer->c_flags & C_POLL) == 0 && 222 (chp->ch_flags & WDCF_TH_RUN) == 0) { 223 chp->ch_queue->queue_freeze++; 224 wakeup(&chp->ch_thread); 225 return; 226 } 227 /* 228 * disable interrupts, all commands here should be quick 229 * enouth to be able to poll, and we don't go here that often 230 */ 231 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 232 WDCTL_4BIT | WDCTL_IDS); 233 if (wdc->cap & WDC_CAPABILITY_SELECT) 234 wdc->select(chp, xfer->c_drive); 235 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 236 WDSD_IBM | (xfer->c_drive << 4)); 237 DELAY(10); 238 errstring = "wait"; 239 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 240 goto ctrltimeout; 241 wdccommandshort(chp, xfer->c_drive, WDCC_RECAL); 242 /* Wait for at last 400ns for status bit to be valid */ 243 DELAY(1); 244 errstring = "recal"; 245 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 246 goto ctrltimeout; 247 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 248 goto ctrlerror; 249 /* Don't try to set modes if controller can't be adjusted */ 250 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0) 251 goto geometry; 252 /* Also don't try if the drive didn't report its mode */ 253 if ((drvp->drive_flags & DRIVE_MODE) == 0) 254 goto geometry; 255 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 256 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 257 errstring = "piomode"; 258 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 259 goto ctrltimeout; 260 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 261 goto ctrlerror; 262 if (drvp->drive_flags & DRIVE_UDMA) { 263 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 264 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 265 } else if (drvp->drive_flags & DRIVE_DMA) { 266 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 267 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 268 } else { 269 goto geometry; 270 } 271 errstring = "dmamode"; 272 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 273 goto ctrltimeout; 274 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 275 goto ctrlerror; 276 geometry: 277 if (ata_bio->flags & ATA_LBA) 278 goto multimode; 279 wdccommand(chp, xfer->c_drive, WDCC_IDP, 280 ata_bio->lp->d_ncylinders, 281 ata_bio->lp->d_ntracks - 1, 0, ata_bio->lp->d_nsectors, 282 (ata_bio->lp->d_type == DTYPE_ST506) ? 283 ata_bio->lp->d_precompcyl / 4 : 0); 284 errstring = "geometry"; 285 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 286 goto ctrltimeout; 287 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 288 goto ctrlerror; 289 multimode: 290 if (ata_bio->multi == 1) 291 goto ready; 292 wdccommand(chp, xfer->c_drive, WDCC_SETMULTI, 0, 0, 0, 293 ata_bio->multi, 0); 294 errstring = "setmulti"; 295 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 296 goto ctrltimeout; 297 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 298 goto ctrlerror; 299 ready: 300 drvp->state = READY; 301 /* 302 * The drive is usable now 303 */ 304 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 305 WDCTL_4BIT); 306 delay(10); /* some drives need a little delay here */ 307 } 308 309 _wdc_ata_bio_start(chp, xfer); 310 return; 311 ctrltimeout: 312 printf("%s:%d:%d: %s timed out\n", 313 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive, 314 errstring); 315 ata_bio->error = TIMEOUT; 316 goto ctrldone; 317 ctrlerror: 318 printf("%s:%d:%d: %s ", 319 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive, 320 errstring); 321 if (chp->ch_status & WDCS_DWF) { 322 printf("drive fault\n"); 323 ata_bio->error = ERR_DF; 324 } else { 325 printf("error (%x)\n", chp->ch_error); 326 ata_bio->r_error = chp->ch_error; 327 ata_bio->error = ERROR; 328 } 329 ctrldone: 330 drvp->state = 0; 331 wdc_ata_bio_done(chp, xfer); 332 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 333 return; 334 } 335 336 static void 337 _wdc_ata_bio_start(struct wdc_channel *chp, struct ata_xfer *xfer) 338 { 339 struct wdc_softc *wdc = chp->ch_wdc; 340 struct ata_bio *ata_bio = xfer->c_cmd; 341 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 342 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 343 u_int16_t cyl; 344 u_int8_t head, sect, cmd = 0; 345 int nblks; 346 int dma_flags = 0; 347 348 WDCDEBUG_PRINT(("_wdc_ata_bio_start %s:%d:%d\n", 349 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 350 DEBUG_INTR | DEBUG_XFERS); 351 352 if (xfer->c_flags & C_DMA) { 353 if (drvp->n_xfers <= NXFER) 354 drvp->n_xfers++; 355 dma_flags = (ata_bio->flags & ATA_READ) ? WDC_DMA_READ : 0; 356 if (ata_bio->flags & ATA_LBA48) 357 dma_flags |= WDC_DMA_LBA48; 358 } 359 again: 360 /* 361 * 362 * When starting a multi-sector transfer, or doing single-sector 363 * transfers... 364 */ 365 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 366 if (ata_bio->flags & ATA_SINGLE) 367 nblks = 1; 368 else 369 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 370 /* Check for bad sectors and adjust transfer, if necessary. */ 371 if ((ata_bio->lp->d_flags & D_BADSECT) != 0) { 372 long blkdiff; 373 int i; 374 for (i = 0; (blkdiff = ata_bio->badsect[i]) != -1; 375 i++) { 376 blkdiff -= ata_bio->blkno; 377 if (blkdiff < 0) 378 continue; 379 if (blkdiff == 0) { 380 /* Replace current block of transfer. */ 381 ata_bio->blkno = 382 ata_bio->lp->d_secperunit - 383 ata_bio->lp->d_nsectors - i - 1; 384 } 385 if (blkdiff < nblks) { 386 /* Bad block inside transfer. */ 387 ata_bio->flags |= ATA_SINGLE; 388 nblks = 1; 389 } 390 break; 391 } 392 /* Transfer is okay now. */ 393 } 394 if (ata_bio->flags & ATA_LBA48) { 395 sect = 0; 396 cyl = 0; 397 head = 0; 398 } else if (ata_bio->flags & ATA_LBA) { 399 sect = (ata_bio->blkno >> 0) & 0xff; 400 cyl = (ata_bio->blkno >> 8) & 0xffff; 401 head = (ata_bio->blkno >> 24) & 0x0f; 402 head |= WDSD_LBA; 403 } else { 404 int blkno = ata_bio->blkno; 405 sect = blkno % ata_bio->lp->d_nsectors; 406 sect++; /* Sectors begin with 1, not 0. */ 407 blkno /= ata_bio->lp->d_nsectors; 408 head = blkno % ata_bio->lp->d_ntracks; 409 blkno /= ata_bio->lp->d_ntracks; 410 cyl = blkno; 411 head |= WDSD_CHS; 412 } 413 if (xfer->c_flags & C_DMA) { 414 ata_bio->nblks = nblks; 415 ata_bio->nbytes = xfer->c_bcount; 416 cmd = (ata_bio->flags & ATA_READ) ? 417 WDCC_READDMA : WDCC_WRITEDMA; 418 /* Init the DMA channel. */ 419 if ((*wdc->dma_init)(wdc->dma_arg, 420 chp->ch_channel, xfer->c_drive, 421 (char *)xfer->c_databuf + xfer->c_skip, 422 ata_bio->nbytes, dma_flags) != 0) { 423 ata_bio->error = ERR_DMA; 424 ata_bio->r_error = 0; 425 wdc_ata_bio_done(chp, xfer); 426 return; 427 } 428 /* Initiate command */ 429 if (wdc->cap & WDC_CAPABILITY_SELECT) 430 wdc->select(chp, xfer->c_drive); 431 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 432 0, WDSD_IBM | (xfer->c_drive << 4)); 433 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags)) { 434 case WDCWAIT_OK: 435 break; 436 case WDCWAIT_TOUT: 437 goto timeout; 438 case WDCWAIT_THR: 439 return; 440 } 441 if (ata_bio->flags & ATA_LBA48) { 442 wdccommandext(chp, xfer->c_drive, to48(cmd), 443 (u_int64_t)ata_bio->blkno, nblks); 444 } else { 445 wdccommand(chp, xfer->c_drive, cmd, cyl, 446 head, sect, nblks, 0); 447 } 448 /* start the DMA channel */ 449 (*wdc->dma_start)(wdc->dma_arg, 450 chp->ch_channel, xfer->c_drive); 451 chp->ch_flags |= WDCF_DMA_WAIT; 452 /* start timeout machinery */ 453 if ((xfer->c_flags & C_POLL) == 0) 454 callout_reset(&chp->ch_callout, 455 ATA_DELAY / 1000 * hz, wdctimeout, chp); 456 /* wait for irq */ 457 goto intr; 458 } /* else not DMA */ 459 ata_bio->nblks = min(nblks, ata_bio->multi); 460 ata_bio->nbytes = ata_bio->nblks * ata_bio->lp->d_secsize; 461 if (ata_bio->nblks > 1 && (ata_bio->flags & ATA_SINGLE) == 0) { 462 cmd = (ata_bio->flags & ATA_READ) ? 463 WDCC_READMULTI : WDCC_WRITEMULTI; 464 } else { 465 cmd = (ata_bio->flags & ATA_READ) ? 466 WDCC_READ : WDCC_WRITE; 467 } 468 /* Initiate command! */ 469 if (wdc->cap & WDC_CAPABILITY_SELECT) 470 wdc->select(chp, xfer->c_drive); 471 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 472 WDSD_IBM | (xfer->c_drive << 4)); 473 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags)) { 474 case WDCWAIT_OK: 475 break; 476 case WDCWAIT_TOUT: 477 goto timeout; 478 case WDCWAIT_THR: 479 return; 480 } 481 if (ata_bio->flags & ATA_LBA48) { 482 wdccommandext(chp, xfer->c_drive, to48(cmd), 483 (u_int64_t) ata_bio->blkno, nblks); 484 } else { 485 wdccommand(chp, xfer->c_drive, cmd, cyl, 486 head, sect, nblks, 487 (ata_bio->lp->d_type == DTYPE_ST506) ? 488 ata_bio->lp->d_precompcyl / 4 : 0); 489 } 490 /* start timeout machinery */ 491 if ((xfer->c_flags & C_POLL) == 0) 492 callout_reset(&chp->ch_callout, 493 ATA_DELAY / 1000 * hz, wdctimeout, chp); 494 } else if (ata_bio->nblks > 1) { 495 /* The number of blocks in the last stretch may be smaller. */ 496 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 497 if (ata_bio->nblks > nblks) { 498 ata_bio->nblks = nblks; 499 ata_bio->nbytes = xfer->c_bcount; 500 } 501 } 502 /* If this was a write and not using DMA, push the data. */ 503 if ((ata_bio->flags & ATA_READ) == 0) { 504 /* 505 * we have to busy-wait here, we can't rely on running in 506 * thread context. 507 */ 508 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL) != 0) { 509 printf("%s:%d:%d: timeout waiting for DRQ, " 510 "st=0x%02x, err=0x%02x\n", 511 wdc->sc_dev.dv_xname, chp->ch_channel, 512 xfer->c_drive, chp->ch_status, chp->ch_error); 513 if (wdc_ata_err(drvp, ata_bio) != WDC_ATA_ERR) 514 ata_bio->error = TIMEOUT; 515 wdc_ata_bio_done(chp, xfer); 516 return; 517 } 518 if (wdc_ata_err(drvp, ata_bio) == WDC_ATA_ERR) { 519 wdc_ata_bio_done(chp, xfer); 520 return; 521 } 522 if ((wdc->cap & WDC_CAPABILITY_ATA_NOSTREAM)) { 523 if (drvp->drive_flags & DRIVE_CAP32) { 524 bus_space_write_multi_4(chp->data32iot, 525 chp->data32ioh, 0, 526 (u_int32_t *)((char *)xfer->c_databuf + 527 xfer->c_skip), 528 ata_bio->nbytes >> 2); 529 } else { 530 bus_space_write_multi_2(chp->cmd_iot, 531 chp->cmd_iohs[wd_data], 0, 532 (u_int16_t *)((char *)xfer->c_databuf + 533 xfer->c_skip), 534 ata_bio->nbytes >> 1); 535 } 536 } else { 537 if (drvp->drive_flags & DRIVE_CAP32) { 538 bus_space_write_multi_stream_4(chp->data32iot, 539 chp->data32ioh, 0, 540 (u_int32_t *)((char *)xfer->c_databuf + 541 xfer->c_skip), 542 ata_bio->nbytes >> 2); 543 } else { 544 bus_space_write_multi_stream_2(chp->cmd_iot, 545 chp->cmd_iohs[wd_data], 0, 546 (u_int16_t *)((char *)xfer->c_databuf + 547 xfer->c_skip), 548 ata_bio->nbytes >> 1); 549 } 550 } 551 } 552 553 intr: /* Wait for IRQ (either real or polled) */ 554 if ((ata_bio->flags & ATA_POLL) == 0) { 555 chp->ch_flags |= WDCF_IRQ_WAIT; 556 } else { 557 /* Wait for at last 400ns for status bit to be valid */ 558 delay(1); 559 if (chp->ch_flags & WDCF_DMA_WAIT) { 560 wdc_dmawait(chp, xfer, ATA_DELAY); 561 chp->ch_flags &= ~WDCF_DMA_WAIT; 562 } 563 wdc_ata_bio_intr(chp, xfer, 0); 564 if ((ata_bio->flags & ATA_ITSDONE) == 0) 565 goto again; 566 } 567 return; 568 timeout: 569 printf("%s:%d:%d: not ready, st=0x%02x, err=0x%02x\n", 570 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive, 571 chp->ch_status, chp->ch_error); 572 if (wdc_ata_err(drvp, ata_bio) != WDC_ATA_ERR) 573 ata_bio->error = TIMEOUT; 574 wdc_ata_bio_done(chp, xfer); 575 return; 576 } 577 578 static int 579 wdc_ata_bio_intr(struct wdc_channel *chp, struct ata_xfer *xfer, int irq) 580 { 581 struct wdc_softc *wdc = chp->ch_wdc; 582 struct ata_bio *ata_bio = xfer->c_cmd; 583 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 584 int drv_err; 585 586 WDCDEBUG_PRINT(("wdc_ata_bio_intr %s:%d:%d\n", 587 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 588 DEBUG_INTR | DEBUG_XFERS); 589 590 591 /* Is it not a transfer, but a control operation? */ 592 if (drvp->state < READY) { 593 printf("%s:%d:%d: bad state %d in wdc_ata_bio_intr\n", 594 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive, 595 drvp->state); 596 panic("wdc_ata_bio_intr: bad state"); 597 } 598 599 /* 600 * if we missed an interrupt in a PIO transfer, reset and restart. 601 * Don't try to continue transfer, we may have missed cycles. 602 */ 603 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 604 ata_bio->error = TIMEOUT; 605 wdc_ata_bio_done(chp, xfer); 606 return 1; 607 } 608 609 /* Ack interrupt done by wdc_wait_for_unbusy */ 610 if (wdc_wait_for_unbusy(chp, (irq == 0) ? ATA_DELAY : 0, AT_POLL) < 0) { 611 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 612 return 0; /* IRQ was not for us */ 613 printf("%s:%d:%d: device timeout, c_bcount=%d, c_skip%d\n", 614 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive, 615 xfer->c_bcount, xfer->c_skip); 616 ata_bio->error = TIMEOUT; 617 wdc_ata_bio_done(chp, xfer); 618 return 1; 619 } 620 if (wdc->cap & WDC_CAPABILITY_IRQACK) 621 wdc->irqack(chp); 622 623 drv_err = wdc_ata_err(drvp, ata_bio); 624 625 /* If we were using DMA, Turn off the DMA channel and check for error */ 626 if (xfer->c_flags & C_DMA) { 627 if (ata_bio->flags & ATA_POLL) { 628 /* 629 * IDE drives deassert WDCS_BSY before transfer is 630 * complete when using DMA. Polling for DRQ to deassert 631 * is not enough DRQ is not required to be 632 * asserted for DMA transfers, so poll for DRDY. 633 */ 634 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 635 ATA_DELAY, ATA_POLL) == WDCWAIT_TOUT) { 636 printf("%s:%d:%d: polled transfer timed out " 637 "(st=0x%x)\n", wdc->sc_dev.dv_xname, 638 chp->ch_channel, xfer->c_drive, 639 chp->ch_status); 640 ata_bio->error = TIMEOUT; 641 drv_err = WDC_ATA_ERR; 642 } 643 } 644 if (wdc->dma_status != 0) { 645 if (drv_err != WDC_ATA_ERR) { 646 ata_bio->error = ERR_DMA; 647 drv_err = WDC_ATA_ERR; 648 } 649 } 650 if (chp->ch_status & WDCS_DRQ) { 651 if (drv_err != WDC_ATA_ERR) { 652 printf("%s:%d:%d: intr with DRQ (st=0x%x)\n", 653 wdc->sc_dev.dv_xname, chp->ch_channel, 654 xfer->c_drive, chp->ch_status); 655 ata_bio->error = TIMEOUT; 656 drv_err = WDC_ATA_ERR; 657 } 658 } 659 if (ata_bio->r_error & WDCE_CRC) 660 ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0); 661 if (drv_err != WDC_ATA_ERR) 662 goto end; 663 } 664 665 /* if we had an error, end */ 666 if (drv_err == WDC_ATA_ERR) { 667 wdc_ata_bio_done(chp, xfer); 668 return 1; 669 } 670 671 /* If this was a read and not using DMA, fetch the data. */ 672 if ((ata_bio->flags & ATA_READ) != 0) { 673 if ((chp->ch_status & WDCS_DRQ) != WDCS_DRQ) { 674 printf("%s:%d:%d: read intr before drq\n", 675 wdc->sc_dev.dv_xname, chp->ch_channel, 676 xfer->c_drive); 677 ata_bio->error = TIMEOUT; 678 wdc_ata_bio_done(chp, xfer); 679 return 1; 680 } 681 if ((wdc->cap & WDC_CAPABILITY_ATA_NOSTREAM)) { 682 if (drvp->drive_flags & DRIVE_CAP32) { 683 bus_space_read_multi_4(chp->data32iot, 684 chp->data32ioh, 0, 685 (u_int32_t *)((char *)xfer->c_databuf + 686 xfer->c_skip), 687 ata_bio->nbytes >> 2); 688 } else { 689 bus_space_read_multi_2(chp->cmd_iot, 690 chp->cmd_iohs[wd_data], 0, 691 (u_int16_t *)((char *)xfer->c_databuf + 692 xfer->c_skip), 693 ata_bio->nbytes >> 1); 694 } 695 } else { 696 if (drvp->drive_flags & DRIVE_CAP32) { 697 bus_space_read_multi_stream_4(chp->data32iot, 698 chp->data32ioh, 0, 699 (u_int32_t *)((char *)xfer->c_databuf + 700 xfer->c_skip), 701 ata_bio->nbytes >> 2); 702 } else { 703 bus_space_read_multi_stream_2(chp->cmd_iot, 704 chp->cmd_iohs[wd_data], 0, 705 (u_int16_t *)((char *)xfer->c_databuf + 706 xfer->c_skip), 707 ata_bio->nbytes >> 1); 708 } 709 } 710 } 711 712 end: 713 ata_bio->blkno += ata_bio->nblks; 714 ata_bio->blkdone += ata_bio->nblks; 715 xfer->c_skip += ata_bio->nbytes; 716 xfer->c_bcount -= ata_bio->nbytes; 717 /* See if this transfer is complete. */ 718 if (xfer->c_bcount > 0) { 719 if ((ata_bio->flags & ATA_POLL) == 0) { 720 /* Start the next operation */ 721 _wdc_ata_bio_start(chp, xfer); 722 } else { 723 /* Let _wdc_ata_bio_start do the loop */ 724 return 1; 725 } 726 } else { /* Done with this transfer */ 727 ata_bio->error = NOERROR; 728 wdc_ata_bio_done(chp, xfer); 729 } 730 return 1; 731 } 732 733 static void 734 wdc_ata_kill_pending(struct ata_drive_datas *drvp) 735 { 736 struct wdc_channel *chp = drvp->chnl_softc; 737 738 wdc_kill_pending(chp); 739 } 740 741 static void 742 wdc_ata_bio_kill_xfer(struct wdc_channel *chp, struct ata_xfer *xfer) 743 { 744 struct ata_bio *ata_bio = xfer->c_cmd; 745 int drive = xfer->c_drive; 746 747 callout_stop(&chp->ch_callout); 748 /* remove this command from xfer queue */ 749 wdc_free_xfer(chp, xfer); 750 751 ata_bio->flags |= ATA_ITSDONE; 752 ata_bio->error = ERR_NODEV; 753 ata_bio->r_error = WDCE_ABRT; 754 WDCDEBUG_PRINT(("wdc_ata_done: drv_done\n"), DEBUG_XFERS); 755 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 756 } 757 758 static void 759 wdc_ata_bio_done(struct wdc_channel *chp, struct ata_xfer *xfer) 760 { 761 struct wdc_softc *wdc = chp->ch_wdc; 762 struct ata_bio *ata_bio = xfer->c_cmd; 763 int drive = xfer->c_drive; 764 765 WDCDEBUG_PRINT(("wdc_ata_bio_done %s:%d:%d: flags 0x%x\n", 766 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive, 767 (u_int)xfer->c_flags), 768 DEBUG_XFERS); 769 770 callout_stop(&chp->ch_callout); 771 772 /* feed back residual bcount to our caller */ 773 ata_bio->bcount = xfer->c_bcount; 774 775 /* remove this command from xfer queue */ 776 wdc_free_xfer(chp, xfer); 777 778 ata_bio->flags |= ATA_ITSDONE; 779 WDCDEBUG_PRINT(("wdc_ata_done: drv_done\n"), DEBUG_XFERS); 780 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 781 WDCDEBUG_PRINT(("wdcstart from wdc_ata_done, flags 0x%x\n", 782 chp->ch_flags), DEBUG_XFERS); 783 wdcstart(chp); 784 } 785 786 static int 787 wdc_ata_err(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 788 { 789 struct wdc_channel *chp = drvp->chnl_softc; 790 ata_bio->error = 0; 791 if (chp->ch_status & WDCS_BSY) { 792 ata_bio->error = TIMEOUT; 793 return WDC_ATA_ERR; 794 } 795 796 if (chp->ch_status & WDCS_DWF) { 797 ata_bio->error = ERR_DF; 798 return WDC_ATA_ERR; 799 } 800 801 if (chp->ch_status & WDCS_ERR) { 802 ata_bio->error = ERROR; 803 ata_bio->r_error = chp->ch_error; 804 if (ata_bio->r_error & (WDCE_BBK | WDCE_UNC | WDCE_IDNF | 805 WDCE_ABRT | WDCE_TK0NF | WDCE_AMNF)) 806 return WDC_ATA_ERR; 807 return WDC_ATA_NOERR; 808 } 809 810 if (chp->ch_status & WDCS_CORR) 811 ata_bio->flags |= ATA_CORR; 812 return WDC_ATA_NOERR; 813 } 814 815 static int 816 wdc_ata_addref(struct ata_drive_datas *drvp) 817 { 818 struct wdc_channel *chp = drvp->chnl_softc; 819 820 return (wdc_addref(chp)); 821 } 822 823 static void 824 wdc_ata_delref(struct ata_drive_datas *drvp) 825 { 826 struct wdc_channel *chp = drvp->chnl_softc; 827 828 wdc_delref(chp); 829 } 830
Indexes created Mon Sep 29 21:09:56 GMT 2025