ata_wdc.c revision 1.85
1 /* $NetBSD: ata_wdc.c,v 1.85 2006/09/30 15:56:18 itohy Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2004 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: ata_wdc.c,v 1.85 2006/09/30 15:56:18 itohy Exp $"); 70 71 #ifndef ATADEBUG 72 #define ATADEBUG 73 #endif /* ATADEBUG */ 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/kernel.h> 78 #include <sys/file.h> 79 #include <sys/stat.h> 80 #include <sys/buf.h> 81 #include <sys/bufq.h> 82 #include <sys/malloc.h> 83 #include <sys/device.h> 84 #include <sys/disklabel.h> 85 #include <sys/syslog.h> 86 #include <sys/proc.h> 87 88 #include <machine/intr.h> 89 #include <machine/bus.h> 90 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 91 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 92 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 93 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 94 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 95 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 96 97 #include <dev/ata/ataconf.h> 98 #include <dev/ata/atareg.h> 99 #include <dev/ata/atavar.h> 100 #include <dev/ic/wdcreg.h> 101 #include <dev/ic/wdcvar.h> 102 103 #define DEBUG_INTR 0x01 104 #define DEBUG_XFERS 0x02 105 #define DEBUG_STATUS 0x04 106 #define DEBUG_FUNCS 0x08 107 #define DEBUG_PROBE 0x10 108 #ifdef ATADEBUG 109 extern int wdcdebug_wd_mask; /* inited in wd.c */ 110 #define ATADEBUG_PRINT(args, level) \ 111 if (wdcdebug_wd_mask & (level)) \ 112 printf args 113 #else 114 #define ATADEBUG_PRINT(args, level) 115 #endif 116 117 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 118 119 static int wdc_ata_bio(struct ata_drive_datas*, struct ata_bio*); 120 static void wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 121 static void _wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 122 static int wdc_ata_bio_intr(struct ata_channel *, struct ata_xfer *, 123 int); 124 static void wdc_ata_bio_kill_xfer(struct ata_channel *, 125 struct ata_xfer *, int); 126 static void wdc_ata_bio_done(struct ata_channel *, struct ata_xfer *); 127 static int wdc_ata_err(struct ata_drive_datas *, struct ata_bio *); 128 #define WDC_ATA_NOERR 0x00 /* Drive doesn't report an error */ 129 #define WDC_ATA_RECOV 0x01 /* There was a recovered error */ 130 #define WDC_ATA_ERR 0x02 /* Drive reports an error */ 131 static int wdc_ata_addref(struct ata_drive_datas *); 132 static void wdc_ata_delref(struct ata_drive_datas *); 133 134 const struct ata_bustype wdc_ata_bustype = { 135 SCSIPI_BUSTYPE_ATA, 136 wdc_ata_bio, 137 wdc_reset_drive, 138 wdc_reset_channel, 139 wdc_exec_command, 140 ata_get_params, 141 wdc_ata_addref, 142 wdc_ata_delref, 143 ata_kill_pending, 144 }; 145 146 /* 147 * Handle block I/O operation. Return ATACMD_COMPLETE, ATACMD_QUEUED, or 148 * ATACMD_TRY_AGAIN. Must be called at splbio(). 149 */ 150 static int 151 wdc_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 152 { 153 struct ata_xfer *xfer; 154 struct ata_channel *chp = drvp->chnl_softc; 155 struct atac_softc *atac = chp->ch_atac; 156 157 xfer = ata_get_xfer(ATAXF_NOSLEEP); 158 if (xfer == NULL) 159 return ATACMD_TRY_AGAIN; 160 if (atac->atac_cap & ATAC_CAP_NOIRQ) 161 ata_bio->flags |= ATA_POLL; 162 if (ata_bio->flags & ATA_POLL) 163 xfer->c_flags |= C_POLL; 164 #if NATA_DMA 165 if ((drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) && 166 (ata_bio->flags & ATA_SINGLE) == 0) 167 xfer->c_flags |= C_DMA; 168 #endif 169 #if NATA_DMA && NATA_PIOBM 170 else 171 #endif 172 #if NATA_PIOBM 173 if (atac->atac_cap & ATAC_CAP_PIOBM) 174 xfer->c_flags |= C_PIOBM; 175 #endif 176 xfer->c_drive = drvp->drive; 177 xfer->c_cmd = ata_bio; 178 xfer->c_databuf = ata_bio->databuf; 179 xfer->c_bcount = ata_bio->bcount; 180 xfer->c_start = wdc_ata_bio_start; 181 xfer->c_intr = wdc_ata_bio_intr; 182 xfer->c_kill_xfer = wdc_ata_bio_kill_xfer; 183 ata_exec_xfer(chp, xfer); 184 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 185 } 186 187 static void 188 wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 189 { 190 struct atac_softc *atac = chp->ch_atac; 191 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 192 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 193 struct ata_bio *ata_bio = xfer->c_cmd; 194 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 195 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 196 const char *errstring; 197 198 ATADEBUG_PRINT(("wdc_ata_bio_start %s:%d:%d\n", 199 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 200 DEBUG_XFERS); 201 202 /* Do control operations specially. */ 203 if (__predict_false(drvp->state < READY)) { 204 /* 205 * Actually, we want to be careful not to mess with the control 206 * state if the device is currently busy, but we can assume 207 * that we never get to this point if that's the case. 208 */ 209 /* If it's not a polled command, we need the kernel thread */ 210 if ((xfer->c_flags & C_POLL) == 0 && 211 (chp->ch_flags & ATACH_TH_RUN) == 0) { 212 chp->ch_queue->queue_freeze++; 213 wakeup(&chp->ch_thread); 214 return; 215 } 216 /* 217 * disable interrupts, all commands here should be quick 218 * enouth to be able to poll, and we don't go here that often 219 */ 220 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 221 WDCTL_4BIT | WDCTL_IDS); 222 if (wdc->select) 223 wdc->select(chp, xfer->c_drive); 224 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 225 WDSD_IBM | (xfer->c_drive << 4)); 226 DELAY(10); 227 errstring = "wait"; 228 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 229 goto ctrltimeout; 230 wdccommandshort(chp, xfer->c_drive, WDCC_RECAL); 231 /* Wait for at last 400ns for status bit to be valid */ 232 DELAY(1); 233 errstring = "recal"; 234 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 235 goto ctrltimeout; 236 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 237 goto ctrlerror; 238 /* Don't try to set modes if controller can't be adjusted */ 239 if (atac->atac_set_modes == NULL) 240 goto geometry; 241 /* Also don't try if the drive didn't report its mode */ 242 if ((drvp->drive_flags & DRIVE_MODE) == 0) 243 goto geometry; 244 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 245 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 246 errstring = "piomode"; 247 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 248 goto ctrltimeout; 249 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 250 goto ctrlerror; 251 #if NATA_DMA 252 #if NATA_UDMA 253 if (drvp->drive_flags & DRIVE_UDMA) { 254 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 255 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 256 } else 257 #endif 258 if (drvp->drive_flags & DRIVE_DMA) { 259 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 260 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 261 } else { 262 goto geometry; 263 } 264 errstring = "dmamode"; 265 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 266 goto ctrltimeout; 267 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 268 goto ctrlerror; 269 #endif /* NATA_DMA */ 270 geometry: 271 if (ata_bio->flags & ATA_LBA) 272 goto multimode; 273 wdccommand(chp, xfer->c_drive, WDCC_IDP, 274 ata_bio->lp->d_ncylinders, 275 ata_bio->lp->d_ntracks - 1, 0, ata_bio->lp->d_nsectors, 276 (ata_bio->lp->d_type == DTYPE_ST506) ? 277 ata_bio->lp->d_precompcyl / 4 : 0); 278 errstring = "geometry"; 279 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 280 goto ctrltimeout; 281 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 282 goto ctrlerror; 283 multimode: 284 if (ata_bio->multi == 1) 285 goto ready; 286 wdccommand(chp, xfer->c_drive, WDCC_SETMULTI, 0, 0, 0, 287 ata_bio->multi, 0); 288 errstring = "setmulti"; 289 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 290 goto ctrltimeout; 291 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 292 goto ctrlerror; 293 ready: 294 drvp->state = READY; 295 /* 296 * The drive is usable now 297 */ 298 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 299 WDCTL_4BIT); 300 delay(10); /* some drives need a little delay here */ 301 } 302 303 _wdc_ata_bio_start(chp, xfer); 304 return; 305 ctrltimeout: 306 printf("%s:%d:%d: %s timed out\n", 307 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive, 308 errstring); 309 ata_bio->error = TIMEOUT; 310 goto ctrldone; 311 ctrlerror: 312 printf("%s:%d:%d: %s ", 313 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive, 314 errstring); 315 if (chp->ch_status & WDCS_DWF) { 316 printf("drive fault\n"); 317 ata_bio->error = ERR_DF; 318 } else { 319 printf("error (%x)\n", chp->ch_error); 320 ata_bio->r_error = chp->ch_error; 321 ata_bio->error = ERROR; 322 } 323 ctrldone: 324 drvp->state = 0; 325 wdc_ata_bio_done(chp, xfer); 326 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 327 return; 328 } 329 330 static void 331 _wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 332 { 333 struct atac_softc *atac = chp->ch_atac; 334 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 335 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 336 struct ata_bio *ata_bio = xfer->c_cmd; 337 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 338 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 339 u_int16_t cyl; 340 u_int8_t head, sect, cmd = 0; 341 int nblks; 342 #if NATA_DMA || NATA_PIOBM 343 int error, dma_flags = 0; 344 #endif 345 346 ATADEBUG_PRINT(("_wdc_ata_bio_start %s:%d:%d\n", 347 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 348 DEBUG_INTR | DEBUG_XFERS); 349 350 #if NATA_DMA || NATA_PIOBM 351 if (xfer->c_flags & (C_DMA | C_PIOBM)) { 352 #if NATA_DMA 353 if (drvp->n_xfers <= NXFER) 354 drvp->n_xfers++; 355 #endif 356 dma_flags = (ata_bio->flags & ATA_READ) ? WDC_DMA_READ : 0; 357 if (ata_bio->flags & ATA_LBA48) 358 dma_flags |= WDC_DMA_LBA48; 359 } 360 #endif 361 again: 362 /* 363 * 364 * When starting a multi-sector transfer, or doing single-sector 365 * transfers... 366 */ 367 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 368 if (ata_bio->flags & ATA_SINGLE) 369 nblks = 1; 370 else 371 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 372 /* Check for bad sectors and adjust transfer, if necessary. */ 373 if ((ata_bio->lp->d_flags & D_BADSECT) != 0) { 374 long blkdiff; 375 int i; 376 for (i = 0; (blkdiff = ata_bio->badsect[i]) != -1; 377 i++) { 378 blkdiff -= ata_bio->blkno; 379 if (blkdiff < 0) 380 continue; 381 if (blkdiff == 0) { 382 /* Replace current block of transfer. */ 383 ata_bio->blkno = 384 ata_bio->lp->d_secperunit - 385 ata_bio->lp->d_nsectors - i - 1; 386 } 387 if (blkdiff < nblks) { 388 /* Bad block inside transfer. */ 389 ata_bio->flags |= ATA_SINGLE; 390 nblks = 1; 391 } 392 break; 393 } 394 /* Transfer is okay now. */ 395 } 396 if (ata_bio->flags & ATA_LBA48) { 397 sect = 0; 398 cyl = 0; 399 head = 0; 400 } else if (ata_bio->flags & ATA_LBA) { 401 sect = (ata_bio->blkno >> 0) & 0xff; 402 cyl = (ata_bio->blkno >> 8) & 0xffff; 403 head = (ata_bio->blkno >> 24) & 0x0f; 404 head |= WDSD_LBA; 405 } else { 406 int blkno = ata_bio->blkno; 407 sect = blkno % ata_bio->lp->d_nsectors; 408 sect++; /* Sectors begin with 1, not 0. */ 409 blkno /= ata_bio->lp->d_nsectors; 410 head = blkno % ata_bio->lp->d_ntracks; 411 blkno /= ata_bio->lp->d_ntracks; 412 cyl = blkno; 413 head |= WDSD_CHS; 414 } 415 #if NATA_DMA 416 if (xfer->c_flags & C_DMA) { 417 ata_bio->nblks = nblks; 418 ata_bio->nbytes = xfer->c_bcount; 419 cmd = (ata_bio->flags & ATA_READ) ? 420 WDCC_READDMA : WDCC_WRITEDMA; 421 /* Init the DMA channel. */ 422 error = (*wdc->dma_init)(wdc->dma_arg, 423 chp->ch_channel, xfer->c_drive, 424 (char *)xfer->c_databuf + xfer->c_skip, 425 ata_bio->nbytes, dma_flags); 426 if (error) { 427 if (error == EINVAL) { 428 /* 429 * We can't do DMA on this transfer 430 * for some reason. Fall back to 431 * PIO. 432 */ 433 xfer->c_flags &= ~C_DMA; 434 error = 0; 435 goto do_pio; 436 } 437 ata_bio->error = ERR_DMA; 438 ata_bio->r_error = 0; 439 wdc_ata_bio_done(chp, xfer); 440 return; 441 } 442 /* Initiate command */ 443 if (wdc->select) 444 wdc->select(chp, xfer->c_drive); 445 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 446 0, WDSD_IBM | (xfer->c_drive << 4)); 447 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags)) { 448 case WDCWAIT_OK: 449 break; 450 case WDCWAIT_TOUT: 451 goto timeout; 452 case WDCWAIT_THR: 453 return; 454 } 455 if (ata_bio->flags & ATA_LBA48) { 456 wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd), 457 (u_int64_t)ata_bio->blkno, nblks); 458 } else { 459 wdccommand(chp, xfer->c_drive, cmd, cyl, 460 head, sect, nblks, 0); 461 } 462 /* start the DMA channel */ 463 (*wdc->dma_start)(wdc->dma_arg, 464 chp->ch_channel, xfer->c_drive); 465 chp->ch_flags |= ATACH_DMA_WAIT; 466 /* start timeout machinery */ 467 if ((xfer->c_flags & C_POLL) == 0) 468 callout_reset(&chp->ch_callout, 469 ATA_DELAY / 1000 * hz, wdctimeout, chp); 470 /* wait for irq */ 471 goto intr; 472 } /* else not DMA */ 473 do_pio: 474 #endif /* NATA_DMA */ 475 #if NATA_PIOBM 476 if ((xfer->c_flags & C_PIOBM) && xfer->c_skip == 0) { 477 if (ata_bio->flags & ATA_POLL) { 478 /* XXX not supported yet --- fall back to PIO */ 479 xfer->c_flags &= ~C_PIOBM; 480 } else { 481 /* Init the DMA channel. */ 482 error = (*wdc->dma_init)(wdc->dma_arg, 483 chp->ch_channel, xfer->c_drive, 484 (char *)xfer->c_databuf + xfer->c_skip, 485 xfer->c_bcount, 486 dma_flags | WDC_DMA_PIOBM_ATA); 487 if (error) { 488 if (error == EINVAL) { 489 /* 490 * We can't do DMA on this 491 * transfer for some reason. 492 * Fall back to PIO. 493 */ 494 xfer->c_flags &= ~C_PIOBM; 495 error = 0; 496 } else { 497 ata_bio->error = ERR_DMA; 498 ata_bio->r_error = 0; 499 wdc_ata_bio_done(chp, xfer); 500 return; 501 } 502 } 503 } 504 } 505 #endif 506 ata_bio->nblks = min(nblks, ata_bio->multi); 507 ata_bio->nbytes = ata_bio->nblks * ata_bio->lp->d_secsize; 508 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 509 if (ata_bio->nblks > 1) { 510 cmd = (ata_bio->flags & ATA_READ) ? 511 WDCC_READMULTI : WDCC_WRITEMULTI; 512 } else { 513 cmd = (ata_bio->flags & ATA_READ) ? 514 WDCC_READ : WDCC_WRITE; 515 } 516 /* Initiate command! */ 517 if (wdc->select) 518 wdc->select(chp, xfer->c_drive); 519 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 520 WDSD_IBM | (xfer->c_drive << 4)); 521 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags)) { 522 case WDCWAIT_OK: 523 break; 524 case WDCWAIT_TOUT: 525 goto timeout; 526 case WDCWAIT_THR: 527 return; 528 } 529 if (ata_bio->flags & ATA_LBA48) { 530 wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd), 531 (u_int64_t) ata_bio->blkno, nblks); 532 } else { 533 wdccommand(chp, xfer->c_drive, cmd, cyl, 534 head, sect, nblks, 535 (ata_bio->lp->d_type == DTYPE_ST506) ? 536 ata_bio->lp->d_precompcyl / 4 : 0); 537 } 538 /* start timeout machinery */ 539 if ((xfer->c_flags & C_POLL) == 0) 540 callout_reset(&chp->ch_callout, 541 ATA_DELAY / 1000 * hz, wdctimeout, chp); 542 } else if (ata_bio->nblks > 1) { 543 /* The number of blocks in the last stretch may be smaller. */ 544 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 545 if (ata_bio->nblks > nblks) { 546 ata_bio->nblks = nblks; 547 ata_bio->nbytes = xfer->c_bcount; 548 } 549 } 550 /* If this was a write and not using DMA, push the data. */ 551 if ((ata_bio->flags & ATA_READ) == 0) { 552 /* 553 * we have to busy-wait here, we can't rely on running in 554 * thread context. 555 */ 556 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL) != 0) { 557 printf("%s:%d:%d: timeout waiting for DRQ, " 558 "st=0x%02x, err=0x%02x\n", 559 atac->atac_dev.dv_xname, chp->ch_channel, 560 xfer->c_drive, chp->ch_status, chp->ch_error); 561 if (wdc_ata_err(drvp, ata_bio) != WDC_ATA_ERR) 562 ata_bio->error = TIMEOUT; 563 wdc_ata_bio_done(chp, xfer); 564 return; 565 } 566 if (wdc_ata_err(drvp, ata_bio) == WDC_ATA_ERR) { 567 wdc_ata_bio_done(chp, xfer); 568 return; 569 } 570 #if NATA_PIOBM 571 if (xfer->c_flags & C_PIOBM) { 572 /* start the busmastering PIO */ 573 (*wdc->piobm_start)(wdc->dma_arg, 574 chp->ch_channel, xfer->c_drive, 575 xfer->c_skip, ata_bio->nbytes, 0); 576 chp->ch_flags |= ATACH_DMA_WAIT; 577 } else 578 #endif 579 580 wdc->dataout_pio(chp, drvp->drive_flags, 581 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 582 } 583 584 #if NATA_DMA 585 intr: 586 #endif 587 /* Wait for IRQ (either real or polled) */ 588 if ((ata_bio->flags & ATA_POLL) == 0) { 589 chp->ch_flags |= ATACH_IRQ_WAIT; 590 } else { 591 /* Wait for at last 400ns for status bit to be valid */ 592 delay(1); 593 #if NATA_DMA 594 if (chp->ch_flags & ATACH_DMA_WAIT) { 595 wdc_dmawait(chp, xfer, ATA_DELAY); 596 chp->ch_flags &= ~ATACH_DMA_WAIT; 597 } 598 #endif 599 wdc_ata_bio_intr(chp, xfer, 0); 600 if ((ata_bio->flags & ATA_ITSDONE) == 0) 601 goto again; 602 } 603 return; 604 timeout: 605 printf("%s:%d:%d: not ready, st=0x%02x, err=0x%02x\n", 606 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive, 607 chp->ch_status, chp->ch_error); 608 if (wdc_ata_err(drvp, ata_bio) != WDC_ATA_ERR) 609 ata_bio->error = TIMEOUT; 610 wdc_ata_bio_done(chp, xfer); 611 return; 612 } 613 614 static int 615 wdc_ata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 616 { 617 struct atac_softc *atac = chp->ch_atac; 618 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 619 struct ata_bio *ata_bio = xfer->c_cmd; 620 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 621 int drv_err; 622 623 ATADEBUG_PRINT(("wdc_ata_bio_intr %s:%d:%d\n", 624 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive), 625 DEBUG_INTR | DEBUG_XFERS); 626 627 628 /* Is it not a transfer, but a control operation? */ 629 if (drvp->state < READY) { 630 printf("%s:%d:%d: bad state %d in wdc_ata_bio_intr\n", 631 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive, 632 drvp->state); 633 panic("wdc_ata_bio_intr: bad state"); 634 } 635 636 /* 637 * if we missed an interrupt in a PIO transfer, reset and restart. 638 * Don't try to continue transfer, we may have missed cycles. 639 */ 640 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 641 ata_bio->error = TIMEOUT; 642 wdc_ata_bio_done(chp, xfer); 643 return 1; 644 } 645 646 #if NATA_PIOBM 647 /* Transfer-done interrupt for busmastering PIO read */ 648 if ((xfer->c_flags & C_PIOBM) && (chp->ch_flags & ATACH_PIOBM_WAIT)) { 649 chp->ch_flags &= ~ATACH_PIOBM_WAIT; 650 goto end; 651 } 652 #endif 653 654 /* Ack interrupt done by wdc_wait_for_unbusy */ 655 if (wdc_wait_for_unbusy(chp, (irq == 0) ? ATA_DELAY : 0, AT_POLL) < 0) { 656 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 657 return 0; /* IRQ was not for us */ 658 printf("%s:%d:%d: device timeout, c_bcount=%d, c_skip%d\n", 659 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive, 660 xfer->c_bcount, xfer->c_skip); 661 ata_bio->error = TIMEOUT; 662 wdc_ata_bio_done(chp, xfer); 663 return 1; 664 } 665 if (wdc->irqack) 666 wdc->irqack(chp); 667 668 drv_err = wdc_ata_err(drvp, ata_bio); 669 670 #if NATA_DMA 671 /* If we were using DMA, Turn off the DMA channel and check for error */ 672 if (xfer->c_flags & C_DMA) { 673 if (ata_bio->flags & ATA_POLL) { 674 /* 675 * IDE drives deassert WDCS_BSY before transfer is 676 * complete when using DMA. Polling for DRQ to deassert 677 * is not enough DRQ is not required to be 678 * asserted for DMA transfers, so poll for DRDY. 679 */ 680 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 681 ATA_DELAY, ATA_POLL) == WDCWAIT_TOUT) { 682 printf("%s:%d:%d: polled transfer timed out " 683 "(st=0x%x)\n", atac->atac_dev.dv_xname, 684 chp->ch_channel, xfer->c_drive, 685 chp->ch_status); 686 ata_bio->error = TIMEOUT; 687 drv_err = WDC_ATA_ERR; 688 } 689 } 690 if (wdc->dma_status != 0) { 691 if (drv_err != WDC_ATA_ERR) { 692 ata_bio->error = ERR_DMA; 693 drv_err = WDC_ATA_ERR; 694 } 695 } 696 if (chp->ch_status & WDCS_DRQ) { 697 if (drv_err != WDC_ATA_ERR) { 698 printf("%s:%d:%d: intr with DRQ (st=0x%x)\n", 699 atac->atac_dev.dv_xname, chp->ch_channel, 700 xfer->c_drive, chp->ch_status); 701 ata_bio->error = TIMEOUT; 702 drv_err = WDC_ATA_ERR; 703 } 704 } 705 if (drv_err != WDC_ATA_ERR) 706 goto end; 707 if (ata_bio->r_error & WDCE_CRC || ata_bio->error == ERR_DMA) 708 ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0); 709 } 710 #endif /* NATA_DMA */ 711 712 /* if we had an error, end */ 713 if (drv_err == WDC_ATA_ERR) { 714 wdc_ata_bio_done(chp, xfer); 715 return 1; 716 } 717 718 /* If this was a read and not using DMA, fetch the data. */ 719 if ((ata_bio->flags & ATA_READ) != 0) { 720 if ((chp->ch_status & WDCS_DRQ) != WDCS_DRQ) { 721 printf("%s:%d:%d: read intr before drq\n", 722 atac->atac_dev.dv_xname, chp->ch_channel, 723 xfer->c_drive); 724 ata_bio->error = TIMEOUT; 725 wdc_ata_bio_done(chp, xfer); 726 return 1; 727 } 728 #if NATA_PIOBM 729 if (xfer->c_flags & C_PIOBM) { 730 /* start the busmastering PIO */ 731 (*wdc->piobm_start)(wdc->dma_arg, 732 chp->ch_channel, xfer->c_drive, 733 xfer->c_skip, ata_bio->nbytes, 734 WDC_PIOBM_XFER_IRQ); 735 chp->ch_flags |= ATACH_DMA_WAIT | ATACH_PIOBM_WAIT | ATACH_IRQ_WAIT; 736 return 1; 737 } else 738 #endif 739 wdc->datain_pio(chp, drvp->drive_flags, 740 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 741 } 742 743 #if NATA_DMA || NATA_PIOBM 744 end: 745 #endif 746 ata_bio->blkno += ata_bio->nblks; 747 ata_bio->blkdone += ata_bio->nblks; 748 xfer->c_skip += ata_bio->nbytes; 749 xfer->c_bcount -= ata_bio->nbytes; 750 /* See if this transfer is complete. */ 751 if (xfer->c_bcount > 0) { 752 if ((ata_bio->flags & ATA_POLL) == 0) { 753 /* Start the next operation */ 754 _wdc_ata_bio_start(chp, xfer); 755 } else { 756 /* Let _wdc_ata_bio_start do the loop */ 757 return 1; 758 } 759 } else { /* Done with this transfer */ 760 ata_bio->error = NOERROR; 761 wdc_ata_bio_done(chp, xfer); 762 } 763 return 1; 764 } 765 766 static void 767 wdc_ata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 768 int reason) 769 { 770 struct ata_bio *ata_bio = xfer->c_cmd; 771 int drive = xfer->c_drive; 772 773 ata_free_xfer(chp, xfer); 774 775 ata_bio->flags |= ATA_ITSDONE; 776 switch (reason) { 777 case KILL_GONE: 778 ata_bio->error = ERR_NODEV; 779 break; 780 case KILL_RESET: 781 ata_bio->error = ERR_RESET; 782 break; 783 default: 784 printf("wdc_ata_bio_kill_xfer: unknown reason %d\n", 785 reason); 786 panic("wdc_ata_bio_kill_xfer"); 787 } 788 ata_bio->r_error = WDCE_ABRT; 789 ATADEBUG_PRINT(("wdc_ata_done: drv_done\n"), DEBUG_XFERS); 790 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 791 } 792 793 static void 794 wdc_ata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 795 { 796 struct atac_softc *atac = chp->ch_atac; 797 struct ata_bio *ata_bio = xfer->c_cmd; 798 int drive = xfer->c_drive; 799 800 ATADEBUG_PRINT(("wdc_ata_bio_done %s:%d:%d: flags 0x%x\n", 801 atac->atac_dev.dv_xname, chp->ch_channel, xfer->c_drive, 802 (u_int)xfer->c_flags), 803 DEBUG_XFERS); 804 805 callout_stop(&chp->ch_callout); 806 807 /* feed back residual bcount to our caller */ 808 ata_bio->bcount = xfer->c_bcount; 809 810 /* mark controller inactive and free xfer */ 811 chp->ch_queue->active_xfer = NULL; 812 ata_free_xfer(chp, xfer); 813 814 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 815 ata_bio->error = ERR_NODEV; 816 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 817 wakeup(&chp->ch_queue->active_xfer); 818 } 819 ata_bio->flags |= ATA_ITSDONE; 820 ATADEBUG_PRINT(("wdc_ata_done: drv_done\n"), DEBUG_XFERS); 821 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 822 ATADEBUG_PRINT(("atastart from wdc_ata_done, flags 0x%x\n", 823 chp->ch_flags), DEBUG_XFERS); 824 atastart(chp); 825 } 826 827 static int 828 wdc_ata_err(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 829 { 830 struct ata_channel *chp = drvp->chnl_softc; 831 ata_bio->error = 0; 832 if (chp->ch_status & WDCS_BSY) { 833 ata_bio->error = TIMEOUT; 834 return WDC_ATA_ERR; 835 } 836 837 if (chp->ch_status & WDCS_DWF) { 838 ata_bio->error = ERR_DF; 839 return WDC_ATA_ERR; 840 } 841 842 if (chp->ch_status & WDCS_ERR) { 843 ata_bio->error = ERROR; 844 ata_bio->r_error = chp->ch_error; 845 if (ata_bio->r_error & (WDCE_BBK | WDCE_UNC | WDCE_IDNF | 846 WDCE_ABRT | WDCE_TK0NF | WDCE_AMNF)) 847 return WDC_ATA_ERR; 848 return WDC_ATA_NOERR; 849 } 850 851 if (chp->ch_status & WDCS_CORR) 852 ata_bio->flags |= ATA_CORR; 853 return WDC_ATA_NOERR; 854 } 855 856 static int 857 wdc_ata_addref(struct ata_drive_datas *drvp) 858 { 859 struct ata_channel *chp = drvp->chnl_softc; 860 861 return (ata_addref(chp)); 862 } 863 864 static void 865 wdc_ata_delref(struct ata_drive_datas *drvp) 866 { 867 struct ata_channel *chp = drvp->chnl_softc; 868 869 ata_delref(chp); 870 } 871
Indexes created Tue Sep 30 11:09:46 GMT 2025