ata_wdc.c revision 1.88.4.2
1 /* $NetBSD: ata_wdc.c,v 1.88.4.2 2010/03/11 15:03:24 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: ata_wdc.c,v 1.88.4.2 2010/03/11 15:03:24 yamt Exp $"); 58 59 #include "opt_ata.h" 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/kernel.h> 64 #include <sys/file.h> 65 #include <sys/stat.h> 66 #include <sys/buf.h> 67 #include <sys/bufq.h> 68 #include <sys/malloc.h> 69 #include <sys/device.h> 70 #include <sys/disklabel.h> 71 #include <sys/syslog.h> 72 #include <sys/proc.h> 73 74 #include <sys/intr.h> 75 #include <sys/bus.h> 76 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 77 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 78 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 79 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 80 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 81 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 82 83 #include <dev/ata/ataconf.h> 84 #include <dev/ata/atareg.h> 85 #include <dev/ata/atavar.h> 86 #include <dev/ic/wdcreg.h> 87 #include <dev/ic/wdcvar.h> 88 89 #define DEBUG_INTR 0x01 90 #define DEBUG_XFERS 0x02 91 #define DEBUG_STATUS 0x04 92 #define DEBUG_FUNCS 0x08 93 #define DEBUG_PROBE 0x10 94 #ifdef ATADEBUG 95 extern int wdcdebug_wd_mask; /* inited in wd.c */ 96 #define ATADEBUG_PRINT(args, level) \ 97 if (wdcdebug_wd_mask & (level)) \ 98 printf args 99 #else 100 #define ATADEBUG_PRINT(args, level) 101 #endif 102 103 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 104 105 static int wdc_ata_bio(struct ata_drive_datas*, struct ata_bio*); 106 static void wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 107 static void _wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 108 static int wdc_ata_bio_intr(struct ata_channel *, struct ata_xfer *, 109 int); 110 static void wdc_ata_bio_kill_xfer(struct ata_channel *, 111 struct ata_xfer *, int); 112 static void wdc_ata_bio_done(struct ata_channel *, struct ata_xfer *); 113 static int wdc_ata_err(struct ata_drive_datas *, struct ata_bio *); 114 #define WDC_ATA_NOERR 0x00 /* Drive doesn't report an error */ 115 #define WDC_ATA_RECOV 0x01 /* There was a recovered error */ 116 #define WDC_ATA_ERR 0x02 /* Drive reports an error */ 117 static int wdc_ata_addref(struct ata_drive_datas *); 118 static void wdc_ata_delref(struct ata_drive_datas *); 119 120 const struct ata_bustype wdc_ata_bustype = { 121 SCSIPI_BUSTYPE_ATA, 122 wdc_ata_bio, 123 wdc_reset_drive, 124 wdc_reset_channel, 125 wdc_exec_command, 126 ata_get_params, 127 wdc_ata_addref, 128 wdc_ata_delref, 129 ata_kill_pending, 130 }; 131 132 /* 133 * Handle block I/O operation. Return ATACMD_COMPLETE, ATACMD_QUEUED, or 134 * ATACMD_TRY_AGAIN. Must be called at splbio(). 135 */ 136 static int 137 wdc_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 138 { 139 struct ata_xfer *xfer; 140 struct ata_channel *chp = drvp->chnl_softc; 141 struct atac_softc *atac = chp->ch_atac; 142 143 xfer = ata_get_xfer(ATAXF_NOSLEEP); 144 if (xfer == NULL) 145 return ATACMD_TRY_AGAIN; 146 if (atac->atac_cap & ATAC_CAP_NOIRQ) 147 ata_bio->flags |= ATA_POLL; 148 if (ata_bio->flags & ATA_POLL) 149 xfer->c_flags |= C_POLL; 150 #if NATA_DMA 151 if ((drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) && 152 (ata_bio->flags & ATA_SINGLE) == 0) 153 xfer->c_flags |= C_DMA; 154 #endif 155 #if NATA_DMA && NATA_PIOBM 156 else 157 #endif 158 #if NATA_PIOBM 159 if (atac->atac_cap & ATAC_CAP_PIOBM) 160 xfer->c_flags |= C_PIOBM; 161 #endif 162 xfer->c_drive = drvp->drive; 163 xfer->c_cmd = ata_bio; 164 xfer->c_databuf = ata_bio->databuf; 165 xfer->c_bcount = ata_bio->bcount; 166 xfer->c_start = wdc_ata_bio_start; 167 xfer->c_intr = wdc_ata_bio_intr; 168 xfer->c_kill_xfer = wdc_ata_bio_kill_xfer; 169 ata_exec_xfer(chp, xfer); 170 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 171 } 172 173 static void 174 wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 175 { 176 struct atac_softc *atac = chp->ch_atac; 177 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 178 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 179 struct ata_bio *ata_bio = xfer->c_cmd; 180 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 181 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 182 const char *errstring; 183 184 ATADEBUG_PRINT(("wdc_ata_bio_start %s:%d:%d\n", 185 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 186 DEBUG_XFERS); 187 188 /* Do control operations specially. */ 189 if (__predict_false(drvp->state < READY)) { 190 /* 191 * Actually, we want to be careful not to mess with the control 192 * state if the device is currently busy, but we can assume 193 * that we never get to this point if that's the case. 194 */ 195 /* If it's not a polled command, we need the kernel thread */ 196 if ((xfer->c_flags & C_POLL) == 0 && 197 (chp->ch_flags & ATACH_TH_RUN) == 0) { 198 chp->ch_queue->queue_freeze++; 199 wakeup(&chp->ch_thread); 200 return; 201 } 202 /* 203 * disable interrupts, all commands here should be quick 204 * enouth to be able to poll, and we don't go here that often 205 */ 206 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 207 WDCTL_4BIT | WDCTL_IDS); 208 if (wdc->select) 209 wdc->select(chp, xfer->c_drive); 210 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 211 WDSD_IBM | (xfer->c_drive << 4)); 212 DELAY(10); 213 errstring = "wait"; 214 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 215 goto ctrltimeout; 216 wdccommandshort(chp, xfer->c_drive, WDCC_RECAL); 217 /* Wait for at last 400ns for status bit to be valid */ 218 DELAY(1); 219 errstring = "recal"; 220 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 221 goto ctrltimeout; 222 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 223 goto ctrlerror; 224 /* Don't try to set modes if controller can't be adjusted */ 225 if (atac->atac_set_modes == NULL) 226 goto geometry; 227 /* Also don't try if the drive didn't report its mode */ 228 if ((drvp->drive_flags & DRIVE_MODE) == 0) 229 goto geometry; 230 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 231 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 232 errstring = "piomode"; 233 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 234 goto ctrltimeout; 235 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 236 goto ctrlerror; 237 #if NATA_DMA 238 #if NATA_UDMA 239 if (drvp->drive_flags & DRIVE_UDMA) { 240 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 241 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 242 } else 243 #endif 244 if (drvp->drive_flags & DRIVE_DMA) { 245 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 246 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 247 } else { 248 goto geometry; 249 } 250 errstring = "dmamode"; 251 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 252 goto ctrltimeout; 253 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 254 goto ctrlerror; 255 #endif /* NATA_DMA */ 256 geometry: 257 if (ata_bio->flags & ATA_LBA) 258 goto multimode; 259 wdccommand(chp, xfer->c_drive, WDCC_IDP, 260 ata_bio->lp->d_ncylinders, 261 ata_bio->lp->d_ntracks - 1, 0, ata_bio->lp->d_nsectors, 262 (ata_bio->lp->d_type == DTYPE_ST506) ? 263 ata_bio->lp->d_precompcyl / 4 : 0); 264 errstring = "geometry"; 265 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 266 goto ctrltimeout; 267 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 268 goto ctrlerror; 269 multimode: 270 if (ata_bio->multi == 1) 271 goto ready; 272 wdccommand(chp, xfer->c_drive, WDCC_SETMULTI, 0, 0, 0, 273 ata_bio->multi, 0); 274 errstring = "setmulti"; 275 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 276 goto ctrltimeout; 277 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 278 goto ctrlerror; 279 ready: 280 drvp->state = READY; 281 /* 282 * The drive is usable now 283 */ 284 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 285 WDCTL_4BIT); 286 delay(10); /* some drives need a little delay here */ 287 } 288 289 _wdc_ata_bio_start(chp, xfer); 290 return; 291 ctrltimeout: 292 printf("%s:%d:%d: %s timed out\n", 293 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 294 errstring); 295 ata_bio->error = TIMEOUT; 296 goto ctrldone; 297 ctrlerror: 298 printf("%s:%d:%d: %s ", 299 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 300 errstring); 301 if (chp->ch_status & WDCS_DWF) { 302 printf("drive fault\n"); 303 ata_bio->error = ERR_DF; 304 } else { 305 printf("error (%x)\n", chp->ch_error); 306 ata_bio->r_error = chp->ch_error; 307 ata_bio->error = ERROR; 308 } 309 ctrldone: 310 drvp->state = 0; 311 wdc_ata_bio_done(chp, xfer); 312 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 313 return; 314 } 315 316 static void 317 _wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 318 { 319 struct atac_softc *atac = chp->ch_atac; 320 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 321 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 322 struct ata_bio *ata_bio = xfer->c_cmd; 323 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 324 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 325 u_int16_t cyl; 326 u_int8_t head, sect, cmd = 0; 327 int nblks; 328 #if NATA_DMA || NATA_PIOBM 329 int error, dma_flags = 0; 330 #endif 331 332 ATADEBUG_PRINT(("_wdc_ata_bio_start %s:%d:%d\n", 333 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 334 DEBUG_INTR | DEBUG_XFERS); 335 336 #if NATA_DMA || NATA_PIOBM 337 if (xfer->c_flags & (C_DMA | C_PIOBM)) { 338 #if NATA_DMA 339 if (drvp->n_xfers <= NXFER) 340 drvp->n_xfers++; 341 #endif 342 dma_flags = (ata_bio->flags & ATA_READ) ? WDC_DMA_READ : 0; 343 if (ata_bio->flags & ATA_LBA48) 344 dma_flags |= WDC_DMA_LBA48; 345 } 346 #endif 347 again: 348 /* 349 * 350 * When starting a multi-sector transfer, or doing single-sector 351 * transfers... 352 */ 353 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 354 if (ata_bio->flags & ATA_SINGLE) 355 nblks = 1; 356 else 357 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 358 /* Check for bad sectors and adjust transfer, if necessary. */ 359 if ((ata_bio->lp->d_flags & D_BADSECT) != 0) { 360 long blkdiff; 361 int i; 362 for (i = 0; (blkdiff = ata_bio->badsect[i]) != -1; 363 i++) { 364 blkdiff -= ata_bio->blkno; 365 if (blkdiff < 0) 366 continue; 367 if (blkdiff == 0) { 368 /* Replace current block of transfer. */ 369 ata_bio->blkno = 370 ata_bio->lp->d_secperunit - 371 ata_bio->lp->d_nsectors - i - 1; 372 } 373 if (blkdiff < nblks) { 374 /* Bad block inside transfer. */ 375 ata_bio->flags |= ATA_SINGLE; 376 nblks = 1; 377 } 378 break; 379 } 380 /* Transfer is okay now. */ 381 } 382 if (ata_bio->flags & ATA_LBA48) { 383 sect = 0; 384 cyl = 0; 385 head = 0; 386 } else if (ata_bio->flags & ATA_LBA) { 387 sect = (ata_bio->blkno >> 0) & 0xff; 388 cyl = (ata_bio->blkno >> 8) & 0xffff; 389 head = (ata_bio->blkno >> 24) & 0x0f; 390 head |= WDSD_LBA; 391 } else { 392 int blkno = ata_bio->blkno; 393 sect = blkno % ata_bio->lp->d_nsectors; 394 sect++; /* Sectors begin with 1, not 0. */ 395 blkno /= ata_bio->lp->d_nsectors; 396 head = blkno % ata_bio->lp->d_ntracks; 397 blkno /= ata_bio->lp->d_ntracks; 398 cyl = blkno; 399 head |= WDSD_CHS; 400 } 401 #if NATA_DMA 402 if (xfer->c_flags & C_DMA) { 403 ata_bio->nblks = nblks; 404 ata_bio->nbytes = xfer->c_bcount; 405 cmd = (ata_bio->flags & ATA_READ) ? 406 WDCC_READDMA : WDCC_WRITEDMA; 407 /* Init the DMA channel. */ 408 error = (*wdc->dma_init)(wdc->dma_arg, 409 chp->ch_channel, xfer->c_drive, 410 (char *)xfer->c_databuf + xfer->c_skip, 411 ata_bio->nbytes, dma_flags); 412 if (error) { 413 if (error == EINVAL) { 414 /* 415 * We can't do DMA on this transfer 416 * for some reason. Fall back to 417 * PIO. 418 */ 419 xfer->c_flags &= ~C_DMA; 420 error = 0; 421 goto do_pio; 422 } 423 ata_bio->error = ERR_DMA; 424 ata_bio->r_error = 0; 425 wdc_ata_bio_done(chp, xfer); 426 return; 427 } 428 /* Initiate command */ 429 if (wdc->select) 430 wdc->select(chp, xfer->c_drive); 431 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 432 0, WDSD_IBM | (xfer->c_drive << 4)); 433 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags)) { 434 case WDCWAIT_OK: 435 break; 436 case WDCWAIT_TOUT: 437 goto timeout; 438 case WDCWAIT_THR: 439 return; 440 } 441 if (ata_bio->flags & ATA_LBA48) { 442 wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd), 443 (u_int64_t)ata_bio->blkno, nblks); 444 } else { 445 wdccommand(chp, xfer->c_drive, cmd, cyl, 446 head, sect, nblks, 0); 447 } 448 /* start the DMA channel */ 449 (*wdc->dma_start)(wdc->dma_arg, 450 chp->ch_channel, xfer->c_drive); 451 chp->ch_flags |= ATACH_DMA_WAIT; 452 /* start timeout machinery */ 453 if ((xfer->c_flags & C_POLL) == 0) 454 callout_reset(&chp->ch_callout, 455 ATA_DELAY / 1000 * hz, wdctimeout, chp); 456 /* wait for irq */ 457 goto intr; 458 } /* else not DMA */ 459 do_pio: 460 #endif /* NATA_DMA */ 461 #if NATA_PIOBM 462 if ((xfer->c_flags & C_PIOBM) && xfer->c_skip == 0) { 463 if (ata_bio->flags & ATA_POLL) { 464 /* XXX not supported yet --- fall back to PIO */ 465 xfer->c_flags &= ~C_PIOBM; 466 } else { 467 /* Init the DMA channel. */ 468 error = (*wdc->dma_init)(wdc->dma_arg, 469 chp->ch_channel, xfer->c_drive, 470 (char *)xfer->c_databuf + xfer->c_skip, 471 xfer->c_bcount, 472 dma_flags | WDC_DMA_PIOBM_ATA); 473 if (error) { 474 if (error == EINVAL) { 475 /* 476 * We can't do DMA on this 477 * transfer for some reason. 478 * Fall back to PIO. 479 */ 480 xfer->c_flags &= ~C_PIOBM; 481 error = 0; 482 } else { 483 ata_bio->error = ERR_DMA; 484 ata_bio->r_error = 0; 485 wdc_ata_bio_done(chp, xfer); 486 return; 487 } 488 } 489 } 490 } 491 #endif 492 ata_bio->nblks = min(nblks, ata_bio->multi); 493 ata_bio->nbytes = ata_bio->nblks * ata_bio->lp->d_secsize; 494 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 495 if (ata_bio->nblks > 1) { 496 cmd = (ata_bio->flags & ATA_READ) ? 497 WDCC_READMULTI : WDCC_WRITEMULTI; 498 } else { 499 cmd = (ata_bio->flags & ATA_READ) ? 500 WDCC_READ : WDCC_WRITE; 501 } 502 /* Initiate command! */ 503 if (wdc->select) 504 wdc->select(chp, xfer->c_drive); 505 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 506 WDSD_IBM | (xfer->c_drive << 4)); 507 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags)) { 508 case WDCWAIT_OK: 509 break; 510 case WDCWAIT_TOUT: 511 goto timeout; 512 case WDCWAIT_THR: 513 return; 514 } 515 if (ata_bio->flags & ATA_LBA48) { 516 wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd), 517 (u_int64_t) ata_bio->blkno, nblks); 518 } else { 519 wdccommand(chp, xfer->c_drive, cmd, cyl, 520 head, sect, nblks, 521 (ata_bio->lp->d_type == DTYPE_ST506) ? 522 ata_bio->lp->d_precompcyl / 4 : 0); 523 } 524 /* start timeout machinery */ 525 if ((xfer->c_flags & C_POLL) == 0) 526 callout_reset(&chp->ch_callout, 527 ATA_DELAY / 1000 * hz, wdctimeout, chp); 528 } else if (ata_bio->nblks > 1) { 529 /* The number of blocks in the last stretch may be smaller. */ 530 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 531 if (ata_bio->nblks > nblks) { 532 ata_bio->nblks = nblks; 533 ata_bio->nbytes = xfer->c_bcount; 534 } 535 } 536 /* If this was a write and not using DMA, push the data. */ 537 if ((ata_bio->flags & ATA_READ) == 0) { 538 /* 539 * we have to busy-wait here, we can't rely on running in 540 * thread context. 541 */ 542 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL) != 0) { 543 printf("%s:%d:%d: timeout waiting for DRQ, " 544 "st=0x%02x, err=0x%02x\n", 545 device_xname(atac->atac_dev), chp->ch_channel, 546 xfer->c_drive, chp->ch_status, chp->ch_error); 547 if (wdc_ata_err(drvp, ata_bio) != WDC_ATA_ERR) 548 ata_bio->error = TIMEOUT; 549 wdc_ata_bio_done(chp, xfer); 550 return; 551 } 552 if (wdc_ata_err(drvp, ata_bio) == WDC_ATA_ERR) { 553 wdc_ata_bio_done(chp, xfer); 554 return; 555 } 556 #if NATA_PIOBM 557 if (xfer->c_flags & C_PIOBM) { 558 /* start the busmastering PIO */ 559 (*wdc->piobm_start)(wdc->dma_arg, 560 chp->ch_channel, xfer->c_drive, 561 xfer->c_skip, ata_bio->nbytes, 0); 562 chp->ch_flags |= ATACH_DMA_WAIT; 563 } else 564 #endif 565 566 wdc->dataout_pio(chp, drvp->drive_flags, 567 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 568 } 569 570 #if NATA_DMA 571 intr: 572 #endif 573 /* Wait for IRQ (either real or polled) */ 574 if ((ata_bio->flags & ATA_POLL) == 0) { 575 chp->ch_flags |= ATACH_IRQ_WAIT; 576 } else { 577 /* Wait for at last 400ns for status bit to be valid */ 578 delay(1); 579 #if NATA_DMA 580 if (chp->ch_flags & ATACH_DMA_WAIT) { 581 wdc_dmawait(chp, xfer, ATA_DELAY); 582 chp->ch_flags &= ~ATACH_DMA_WAIT; 583 } 584 #endif 585 wdc_ata_bio_intr(chp, xfer, 0); 586 if ((ata_bio->flags & ATA_ITSDONE) == 0) 587 goto again; 588 } 589 return; 590 timeout: 591 printf("%s:%d:%d: not ready, st=0x%02x, err=0x%02x\n", 592 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 593 chp->ch_status, chp->ch_error); 594 if (wdc_ata_err(drvp, ata_bio) != WDC_ATA_ERR) 595 ata_bio->error = TIMEOUT; 596 wdc_ata_bio_done(chp, xfer); 597 return; 598 } 599 600 static int 601 wdc_ata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 602 { 603 struct atac_softc *atac = chp->ch_atac; 604 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 605 struct ata_bio *ata_bio = xfer->c_cmd; 606 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 607 int drv_err; 608 609 ATADEBUG_PRINT(("wdc_ata_bio_intr %s:%d:%d\n", 610 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 611 DEBUG_INTR | DEBUG_XFERS); 612 613 614 /* Is it not a transfer, but a control operation? */ 615 if (drvp->state < READY) { 616 printf("%s:%d:%d: bad state %d in wdc_ata_bio_intr\n", 617 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 618 drvp->state); 619 panic("wdc_ata_bio_intr: bad state"); 620 } 621 622 /* 623 * if we missed an interrupt in a PIO transfer, reset and restart. 624 * Don't try to continue transfer, we may have missed cycles. 625 */ 626 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 627 ata_bio->error = TIMEOUT; 628 wdc_ata_bio_done(chp, xfer); 629 return 1; 630 } 631 632 #if NATA_PIOBM 633 /* Transfer-done interrupt for busmastering PIO read */ 634 if ((xfer->c_flags & C_PIOBM) && (chp->ch_flags & ATACH_PIOBM_WAIT)) { 635 chp->ch_flags &= ~ATACH_PIOBM_WAIT; 636 goto end; 637 } 638 #endif 639 640 /* Ack interrupt done by wdc_wait_for_unbusy */ 641 if (wdc_wait_for_unbusy(chp, (irq == 0) ? ATA_DELAY : 0, AT_POLL) < 0) { 642 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 643 return 0; /* IRQ was not for us */ 644 printf("%s:%d:%d: device timeout, c_bcount=%d, c_skip%d\n", 645 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 646 xfer->c_bcount, xfer->c_skip); 647 ata_bio->error = TIMEOUT; 648 wdc_ata_bio_done(chp, xfer); 649 return 1; 650 } 651 if (wdc->irqack) 652 wdc->irqack(chp); 653 654 drv_err = wdc_ata_err(drvp, ata_bio); 655 656 #if NATA_DMA 657 /* If we were using DMA, Turn off the DMA channel and check for error */ 658 if (xfer->c_flags & C_DMA) { 659 if (ata_bio->flags & ATA_POLL) { 660 /* 661 * IDE drives deassert WDCS_BSY before transfer is 662 * complete when using DMA. Polling for DRQ to deassert 663 * is not enough DRQ is not required to be 664 * asserted for DMA transfers, so poll for DRDY. 665 */ 666 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 667 ATA_DELAY, ATA_POLL) == WDCWAIT_TOUT) { 668 printf("%s:%d:%d: polled transfer timed out " 669 "(st=0x%x)\n", 670 device_xname(atac->atac_dev), 671 chp->ch_channel, xfer->c_drive, 672 chp->ch_status); 673 ata_bio->error = TIMEOUT; 674 drv_err = WDC_ATA_ERR; 675 } 676 } 677 if (wdc->dma_status != 0) { 678 if (drv_err != WDC_ATA_ERR) { 679 ata_bio->error = ERR_DMA; 680 drv_err = WDC_ATA_ERR; 681 } 682 } 683 if (chp->ch_status & WDCS_DRQ) { 684 if (drv_err != WDC_ATA_ERR) { 685 printf("%s:%d:%d: intr with DRQ (st=0x%x)\n", 686 device_xname(atac->atac_dev), 687 chp->ch_channel, 688 xfer->c_drive, chp->ch_status); 689 ata_bio->error = TIMEOUT; 690 drv_err = WDC_ATA_ERR; 691 } 692 } 693 if (drv_err != WDC_ATA_ERR) 694 goto end; 695 if (ata_bio->r_error & WDCE_CRC || ata_bio->error == ERR_DMA) 696 ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0); 697 } 698 #endif /* NATA_DMA */ 699 700 /* if we had an error, end */ 701 if (drv_err == WDC_ATA_ERR) { 702 wdc_ata_bio_done(chp, xfer); 703 return 1; 704 } 705 706 /* If this was a read and not using DMA, fetch the data. */ 707 if ((ata_bio->flags & ATA_READ) != 0) { 708 if ((chp->ch_status & WDCS_DRQ) != WDCS_DRQ) { 709 printf("%s:%d:%d: read intr before drq\n", 710 device_xname(atac->atac_dev), chp->ch_channel, 711 xfer->c_drive); 712 ata_bio->error = TIMEOUT; 713 wdc_ata_bio_done(chp, xfer); 714 return 1; 715 } 716 #if NATA_PIOBM 717 if (xfer->c_flags & C_PIOBM) { 718 /* start the busmastering PIO */ 719 (*wdc->piobm_start)(wdc->dma_arg, 720 chp->ch_channel, xfer->c_drive, 721 xfer->c_skip, ata_bio->nbytes, 722 WDC_PIOBM_XFER_IRQ); 723 chp->ch_flags |= ATACH_DMA_WAIT | ATACH_PIOBM_WAIT | ATACH_IRQ_WAIT; 724 return 1; 725 } else 726 #endif 727 wdc->datain_pio(chp, drvp->drive_flags, 728 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 729 } 730 731 #if NATA_DMA || NATA_PIOBM 732 end: 733 #endif 734 ata_bio->blkno += ata_bio->nblks; 735 ata_bio->blkdone += ata_bio->nblks; 736 xfer->c_skip += ata_bio->nbytes; 737 xfer->c_bcount -= ata_bio->nbytes; 738 /* See if this transfer is complete. */ 739 if (xfer->c_bcount > 0) { 740 if ((ata_bio->flags & ATA_POLL) == 0) { 741 /* Start the next operation */ 742 _wdc_ata_bio_start(chp, xfer); 743 } else { 744 /* Let _wdc_ata_bio_start do the loop */ 745 return 1; 746 } 747 } else { /* Done with this transfer */ 748 ata_bio->error = NOERROR; 749 wdc_ata_bio_done(chp, xfer); 750 } 751 return 1; 752 } 753 754 static void 755 wdc_ata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 756 int reason) 757 { 758 struct ata_bio *ata_bio = xfer->c_cmd; 759 int drive = xfer->c_drive; 760 761 ata_free_xfer(chp, xfer); 762 763 ata_bio->flags |= ATA_ITSDONE; 764 switch (reason) { 765 case KILL_GONE: 766 ata_bio->error = ERR_NODEV; 767 break; 768 case KILL_RESET: 769 ata_bio->error = ERR_RESET; 770 break; 771 default: 772 printf("wdc_ata_bio_kill_xfer: unknown reason %d\n", 773 reason); 774 panic("wdc_ata_bio_kill_xfer"); 775 } 776 ata_bio->r_error = WDCE_ABRT; 777 ATADEBUG_PRINT(("wdc_ata_done: drv_done\n"), DEBUG_XFERS); 778 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 779 } 780 781 static void 782 wdc_ata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 783 { 784 struct ata_bio *ata_bio = xfer->c_cmd; 785 int drive = xfer->c_drive; 786 787 ATADEBUG_PRINT(("wdc_ata_bio_done %s:%d:%d: flags 0x%x\n", 788 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 789 xfer->c_drive, (u_int)xfer->c_flags), 790 DEBUG_XFERS); 791 792 callout_stop(&chp->ch_callout); 793 794 /* feed back residual bcount to our caller */ 795 ata_bio->bcount = xfer->c_bcount; 796 797 /* mark controller inactive and free xfer */ 798 chp->ch_queue->active_xfer = NULL; 799 ata_free_xfer(chp, xfer); 800 801 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 802 ata_bio->error = ERR_NODEV; 803 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 804 wakeup(&chp->ch_queue->active_xfer); 805 } 806 ata_bio->flags |= ATA_ITSDONE; 807 ATADEBUG_PRINT(("wdc_ata_done: drv_done\n"), DEBUG_XFERS); 808 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 809 ATADEBUG_PRINT(("atastart from wdc_ata_done, flags 0x%x\n", 810 chp->ch_flags), DEBUG_XFERS); 811 atastart(chp); 812 } 813 814 static int 815 wdc_ata_err(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 816 { 817 struct ata_channel *chp = drvp->chnl_softc; 818 ata_bio->error = 0; 819 if (chp->ch_status & WDCS_BSY) { 820 ata_bio->error = TIMEOUT; 821 return WDC_ATA_ERR; 822 } 823 824 if (chp->ch_status & WDCS_DWF) { 825 ata_bio->error = ERR_DF; 826 return WDC_ATA_ERR; 827 } 828 829 if (chp->ch_status & WDCS_ERR) { 830 ata_bio->error = ERROR; 831 ata_bio->r_error = chp->ch_error; 832 if (ata_bio->r_error & (WDCE_BBK | WDCE_UNC | WDCE_IDNF | 833 WDCE_ABRT | WDCE_TK0NF | WDCE_AMNF)) 834 return WDC_ATA_ERR; 835 return WDC_ATA_NOERR; 836 } 837 838 if (chp->ch_status & WDCS_CORR) 839 ata_bio->flags |= ATA_CORR; 840 return WDC_ATA_NOERR; 841 } 842 843 static int 844 wdc_ata_addref(struct ata_drive_datas *drvp) 845 { 846 struct ata_channel *chp = drvp->chnl_softc; 847 848 return (ata_addref(chp)); 849 } 850 851 static void 852 wdc_ata_delref(struct ata_drive_datas *drvp) 853 { 854 struct ata_channel *chp = drvp->chnl_softc; 855 856 ata_delref(chp); 857 } 858
Indexes created Thu Oct 23 22:10:10 GMT 2025