ata_wdc.c revision 1.95.2.4
1 /* $NetBSD: ata_wdc.c,v 1.95.2.4 2014/05/22 11:40:20 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: ata_wdc.c,v 1.95.2.4 2014/05/22 11:40:20 yamt Exp $"); 58 59 #include "opt_ata.h" 60 #include "opt_wdc.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/file.h> 66 #include <sys/stat.h> 67 #include <sys/buf.h> 68 #include <sys/bufq.h> 69 #include <sys/malloc.h> 70 #include <sys/device.h> 71 #include <sys/disklabel.h> 72 #include <sys/syslog.h> 73 #include <sys/proc.h> 74 75 #include <sys/intr.h> 76 #include <sys/bus.h> 77 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 78 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 79 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 80 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 81 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 82 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 83 84 #include <dev/ata/ataconf.h> 85 #include <dev/ata/atareg.h> 86 #include <dev/ata/atavar.h> 87 #include <dev/ic/wdcreg.h> 88 #include <dev/ic/wdcvar.h> 89 90 #define DEBUG_INTR 0x01 91 #define DEBUG_XFERS 0x02 92 #define DEBUG_STATUS 0x04 93 #define DEBUG_FUNCS 0x08 94 #define DEBUG_PROBE 0x10 95 #ifdef ATADEBUG 96 extern int wdcdebug_wd_mask; /* inited in wd.c */ 97 #define ATADEBUG_PRINT(args, level) \ 98 if (wdcdebug_wd_mask & (level)) \ 99 printf args 100 #else 101 #define ATADEBUG_PRINT(args, level) 102 #endif 103 104 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 105 106 static int wdc_ata_bio(struct ata_drive_datas*, struct ata_bio*); 107 static void wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 108 static void _wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 109 static int wdc_ata_bio_intr(struct ata_channel *, struct ata_xfer *, 110 int); 111 static void wdc_ata_bio_kill_xfer(struct ata_channel *, 112 struct ata_xfer *, int); 113 static void wdc_ata_bio_done(struct ata_channel *, struct ata_xfer *); 114 static int wdc_ata_err(struct ata_drive_datas *, struct ata_bio *); 115 #define WDC_ATA_NOERR 0x00 /* Drive doesn't report an error */ 116 #define WDC_ATA_RECOV 0x01 /* There was a recovered error */ 117 #define WDC_ATA_ERR 0x02 /* Drive reports an error */ 118 static int wdc_ata_addref(struct ata_drive_datas *); 119 static void wdc_ata_delref(struct ata_drive_datas *); 120 121 const struct ata_bustype wdc_ata_bustype = { 122 SCSIPI_BUSTYPE_ATA, 123 wdc_ata_bio, 124 wdc_reset_drive, 125 wdc_reset_channel, 126 wdc_exec_command, 127 ata_get_params, 128 wdc_ata_addref, 129 wdc_ata_delref, 130 ata_kill_pending, 131 }; 132 133 /* 134 * Handle block I/O operation. Return ATACMD_COMPLETE, ATACMD_QUEUED, or 135 * ATACMD_TRY_AGAIN. Must be called at splbio(). 136 */ 137 static int 138 wdc_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 139 { 140 struct ata_xfer *xfer; 141 struct ata_channel *chp = drvp->chnl_softc; 142 struct atac_softc *atac = chp->ch_atac; 143 144 xfer = ata_get_xfer(ATAXF_NOSLEEP); 145 if (xfer == NULL) 146 return ATACMD_TRY_AGAIN; 147 if (atac->atac_cap & ATAC_CAP_NOIRQ) 148 ata_bio->flags |= ATA_POLL; 149 if (ata_bio->flags & ATA_POLL) 150 xfer->c_flags |= C_POLL; 151 #if NATA_DMA 152 if ((drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) && 153 (ata_bio->flags & ATA_SINGLE) == 0) 154 xfer->c_flags |= C_DMA; 155 #endif 156 #if NATA_DMA && NATA_PIOBM 157 else 158 #endif 159 #if NATA_PIOBM 160 if (atac->atac_cap & ATAC_CAP_PIOBM) 161 xfer->c_flags |= C_PIOBM; 162 #endif 163 xfer->c_drive = drvp->drive; 164 xfer->c_cmd = ata_bio; 165 xfer->c_databuf = ata_bio->databuf; 166 xfer->c_bcount = ata_bio->bcount; 167 xfer->c_start = wdc_ata_bio_start; 168 xfer->c_intr = wdc_ata_bio_intr; 169 xfer->c_kill_xfer = wdc_ata_bio_kill_xfer; 170 ata_exec_xfer(chp, xfer); 171 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 172 } 173 174 static void 175 wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 176 { 177 struct atac_softc *atac = chp->ch_atac; 178 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 179 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 180 struct ata_bio *ata_bio = xfer->c_cmd; 181 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 182 int wait_flags; 183 const char *errstring; 184 #ifdef WDC_NO_IDS 185 wait_flags = AT_POLL; 186 #else 187 wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 188 #endif 189 190 ATADEBUG_PRINT(("wdc_ata_bio_start %s:%d:%d state %d drive_flags 0x%x " 191 "c_flags 0x%x ch_flags 0x%x\n", 192 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 193 drvp->state, drvp->drive_flags, xfer->c_flags, chp->ch_flags), 194 DEBUG_XFERS); 195 196 /* Do control operations specially. */ 197 if (__predict_false(drvp->state < READY)) { 198 /* 199 * Actually, we want to be careful not to mess with the control 200 * state if the device is currently busy, but we can assume 201 * that we never get to this point if that's the case. 202 */ 203 /* If it's not a polled command, we need the kernel thread */ 204 if ((xfer->c_flags & C_POLL) == 0 && 205 (chp->ch_flags & ATACH_TH_RUN) == 0) { 206 chp->ch_queue->queue_freeze++; 207 wakeup(&chp->ch_thread); 208 return; 209 } 210 /* 211 * disable interrupts, all commands here should be quick 212 * enough to be able to poll, and we don't go here that often 213 */ 214 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 215 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 216 wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS); 217 if (wdc->select) 218 wdc->select(chp, xfer->c_drive); 219 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 220 WDSD_IBM | (xfer->c_drive << 4)); 221 DELAY(10); 222 errstring = "wait"; 223 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 224 goto ctrltimeout; 225 wdccommandshort(chp, xfer->c_drive, WDCC_RECAL); 226 /* Wait for at last 400ns for status bit to be valid */ 227 DELAY(1); 228 errstring = "recal"; 229 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 230 goto ctrltimeout; 231 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 232 goto ctrlerror; 233 /* Don't try to set modes if controller can't be adjusted */ 234 if (atac->atac_set_modes == NULL) 235 goto geometry; 236 /* Also don't try if the drive didn't report its mode */ 237 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 238 goto geometry; 239 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 240 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 241 errstring = "piomode"; 242 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 243 goto ctrltimeout; 244 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 245 goto ctrlerror; 246 #if NATA_DMA 247 #if NATA_UDMA 248 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 249 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 250 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 251 } else 252 #endif 253 if (drvp->drive_flags & ATA_DRIVE_DMA) { 254 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 255 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 256 } else { 257 goto geometry; 258 } 259 errstring = "dmamode"; 260 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 261 goto ctrltimeout; 262 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 263 goto ctrlerror; 264 #endif /* NATA_DMA */ 265 geometry: 266 if (ata_bio->flags & ATA_LBA) 267 goto multimode; 268 wdccommand(chp, xfer->c_drive, WDCC_IDP, 269 ata_bio->lp->d_ncylinders, 270 ata_bio->lp->d_ntracks - 1, 0, ata_bio->lp->d_nsectors, 271 (ata_bio->lp->d_type == DTYPE_ST506) ? 272 ata_bio->lp->d_precompcyl / 4 : 0); 273 errstring = "geometry"; 274 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 275 goto ctrltimeout; 276 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 277 goto ctrlerror; 278 multimode: 279 if (ata_bio->multi == 1) 280 goto ready; 281 wdccommand(chp, xfer->c_drive, WDCC_SETMULTI, 0, 0, 0, 282 ata_bio->multi, 0); 283 errstring = "setmulti"; 284 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags)) 285 goto ctrltimeout; 286 if (chp->ch_status & (WDCS_ERR | WDCS_DWF)) 287 goto ctrlerror; 288 ready: 289 drvp->state = READY; 290 /* 291 * The drive is usable now 292 */ 293 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 294 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 295 wd_aux_ctlr, WDCTL_4BIT); 296 delay(10); /* some drives need a little delay here */ 297 } 298 299 _wdc_ata_bio_start(chp, xfer); 300 return; 301 ctrltimeout: 302 printf("%s:%d:%d: %s timed out\n", 303 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 304 errstring); 305 ata_bio->error = TIMEOUT; 306 goto ctrldone; 307 ctrlerror: 308 printf("%s:%d:%d: %s ", 309 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 310 errstring); 311 if (chp->ch_status & WDCS_DWF) { 312 printf("drive fault\n"); 313 ata_bio->error = ERR_DF; 314 } else { 315 printf("error (%x)\n", chp->ch_error); 316 ata_bio->r_error = chp->ch_error; 317 ata_bio->error = ERROR; 318 } 319 ctrldone: 320 drvp->state = 0; 321 wdc_ata_bio_done(chp, xfer); 322 323 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 324 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 325 WDCTL_4BIT); 326 return; 327 } 328 329 static void 330 _wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 331 { 332 struct atac_softc *atac = chp->ch_atac; 333 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 334 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 335 struct ata_bio *ata_bio = xfer->c_cmd; 336 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 337 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 338 u_int16_t cyl; 339 u_int8_t head, sect, cmd = 0; 340 int nblks; 341 #if NATA_DMA || NATA_PIOBM 342 int error, dma_flags = 0; 343 #endif 344 345 ATADEBUG_PRINT(("_wdc_ata_bio_start %s:%d:%d\n", 346 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 347 DEBUG_INTR | DEBUG_XFERS); 348 349 #if NATA_DMA || NATA_PIOBM 350 if (xfer->c_flags & (C_DMA | C_PIOBM)) { 351 #if NATA_DMA 352 if (drvp->n_xfers <= NXFER) 353 drvp->n_xfers++; 354 #endif 355 dma_flags = (ata_bio->flags & ATA_READ) ? WDC_DMA_READ : 0; 356 if (ata_bio->flags & ATA_LBA48) 357 dma_flags |= WDC_DMA_LBA48; 358 } 359 #endif 360 again: 361 /* 362 * 363 * When starting a multi-sector transfer, or doing single-sector 364 * transfers... 365 */ 366 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 367 if (ata_bio->flags & ATA_SINGLE) 368 nblks = 1; 369 else 370 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 371 /* Check for bad sectors and adjust transfer, if necessary. */ 372 if ((ata_bio->lp->d_flags & D_BADSECT) != 0) { 373 long blkdiff; 374 int i; 375 for (i = 0; (blkdiff = ata_bio->badsect[i]) != -1; 376 i++) { 377 blkdiff -= ata_bio->blkno; 378 if (blkdiff < 0) 379 continue; 380 if (blkdiff == 0) { 381 /* Replace current block of transfer. */ 382 ata_bio->blkno = 383 ata_bio->lp->d_secperunit - 384 ata_bio->lp->d_nsectors - i - 1; 385 } 386 if (blkdiff < nblks) { 387 /* Bad block inside transfer. */ 388 ata_bio->flags |= ATA_SINGLE; 389 nblks = 1; 390 } 391 break; 392 } 393 /* Transfer is okay now. */ 394 } 395 if (ata_bio->flags & ATA_LBA48) { 396 sect = 0; 397 cyl = 0; 398 head = 0; 399 } else if (ata_bio->flags & ATA_LBA) { 400 sect = (ata_bio->blkno >> 0) & 0xff; 401 cyl = (ata_bio->blkno >> 8) & 0xffff; 402 head = (ata_bio->blkno >> 24) & 0x0f; 403 head |= WDSD_LBA; 404 } else { 405 int blkno = ata_bio->blkno; 406 sect = blkno % ata_bio->lp->d_nsectors; 407 sect++; /* Sectors begin with 1, not 0. */ 408 blkno /= ata_bio->lp->d_nsectors; 409 head = blkno % ata_bio->lp->d_ntracks; 410 blkno /= ata_bio->lp->d_ntracks; 411 cyl = blkno; 412 head |= WDSD_CHS; 413 } 414 #if NATA_DMA 415 if (xfer->c_flags & C_DMA) { 416 ata_bio->nblks = nblks; 417 ata_bio->nbytes = xfer->c_bcount; 418 cmd = (ata_bio->flags & ATA_READ) ? 419 WDCC_READDMA : WDCC_WRITEDMA; 420 /* Init the DMA channel. */ 421 error = (*wdc->dma_init)(wdc->dma_arg, 422 chp->ch_channel, xfer->c_drive, 423 (char *)xfer->c_databuf + xfer->c_skip, 424 ata_bio->nbytes, dma_flags); 425 if (error) { 426 if (error == EINVAL) { 427 /* 428 * We can't do DMA on this transfer 429 * for some reason. Fall back to 430 * PIO. 431 */ 432 xfer->c_flags &= ~C_DMA; 433 error = 0; 434 goto do_pio; 435 } 436 ata_bio->error = ERR_DMA; 437 ata_bio->r_error = 0; 438 wdc_ata_bio_done(chp, xfer); 439 return; 440 } 441 /* Initiate command */ 442 if (wdc->select) 443 wdc->select(chp, xfer->c_drive); 444 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 445 0, WDSD_IBM | (xfer->c_drive << 4)); 446 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags)) { 447 case WDCWAIT_OK: 448 break; 449 case WDCWAIT_TOUT: 450 goto timeout; 451 case WDCWAIT_THR: 452 return; 453 } 454 if (ata_bio->flags & ATA_LBA48) { 455 wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd), 456 ata_bio->blkno, nblks, 0, WDSD_LBA); 457 } else { 458 wdccommand(chp, xfer->c_drive, cmd, cyl, 459 head, sect, nblks, 0); 460 } 461 /* start the DMA channel */ 462 (*wdc->dma_start)(wdc->dma_arg, 463 chp->ch_channel, xfer->c_drive); 464 chp->ch_flags |= ATACH_DMA_WAIT; 465 /* start timeout machinery */ 466 if ((xfer->c_flags & C_POLL) == 0) 467 callout_reset(&chp->ch_callout, 468 ATA_DELAY / 1000 * hz, wdctimeout, chp); 469 /* wait for irq */ 470 goto intr; 471 } /* else not DMA */ 472 do_pio: 473 #endif /* NATA_DMA */ 474 #if NATA_PIOBM 475 if ((xfer->c_flags & C_PIOBM) && xfer->c_skip == 0) { 476 if (ata_bio->flags & ATA_POLL) { 477 /* XXX not supported yet --- fall back to PIO */ 478 xfer->c_flags &= ~C_PIOBM; 479 } else { 480 /* Init the DMA channel. */ 481 error = (*wdc->dma_init)(wdc->dma_arg, 482 chp->ch_channel, xfer->c_drive, 483 (char *)xfer->c_databuf + xfer->c_skip, 484 xfer->c_bcount, 485 dma_flags | WDC_DMA_PIOBM_ATA); 486 if (error) { 487 if (error == EINVAL) { 488 /* 489 * We can't do DMA on this 490 * transfer for some reason. 491 * Fall back to PIO. 492 */ 493 xfer->c_flags &= ~C_PIOBM; 494 error = 0; 495 } else { 496 ata_bio->error = ERR_DMA; 497 ata_bio->r_error = 0; 498 wdc_ata_bio_done(chp, xfer); 499 return; 500 } 501 } 502 } 503 } 504 #endif 505 ata_bio->nblks = min(nblks, ata_bio->multi); 506 ata_bio->nbytes = ata_bio->nblks * ata_bio->lp->d_secsize; 507 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 508 if (ata_bio->nblks > 1) { 509 cmd = (ata_bio->flags & ATA_READ) ? 510 WDCC_READMULTI : WDCC_WRITEMULTI; 511 } else { 512 cmd = (ata_bio->flags & ATA_READ) ? 513 WDCC_READ : WDCC_WRITE; 514 } 515 /* Initiate command! */ 516 if (wdc->select) 517 wdc->select(chp, xfer->c_drive); 518 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 519 WDSD_IBM | (xfer->c_drive << 4)); 520 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags)) { 521 case WDCWAIT_OK: 522 break; 523 case WDCWAIT_TOUT: 524 goto timeout; 525 case WDCWAIT_THR: 526 return; 527 } 528 if (ata_bio->flags & ATA_LBA48) { 529 wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd), 530 ata_bio->blkno, nblks, 0, WDSD_LBA); 531 } else { 532 wdccommand(chp, xfer->c_drive, cmd, cyl, 533 head, sect, nblks, 534 (ata_bio->lp->d_type == DTYPE_ST506) ? 535 ata_bio->lp->d_precompcyl / 4 : 0); 536 } 537 /* start timeout machinery */ 538 if ((xfer->c_flags & C_POLL) == 0) 539 callout_reset(&chp->ch_callout, 540 ATA_DELAY / 1000 * hz, wdctimeout, chp); 541 } else if (ata_bio->nblks > 1) { 542 /* The number of blocks in the last stretch may be smaller. */ 543 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 544 if (ata_bio->nblks > nblks) { 545 ata_bio->nblks = nblks; 546 ata_bio->nbytes = xfer->c_bcount; 547 } 548 } 549 /* If this was a write and not using DMA, push the data. */ 550 if ((ata_bio->flags & ATA_READ) == 0) { 551 /* 552 * we have to busy-wait here, we can't rely on running in 553 * thread context. 554 */ 555 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL) != 0) { 556 printf("%s:%d:%d: timeout waiting for DRQ, " 557 "st=0x%02x, err=0x%02x\n", 558 device_xname(atac->atac_dev), chp->ch_channel, 559 xfer->c_drive, chp->ch_status, chp->ch_error); 560 if (wdc_ata_err(drvp, ata_bio) != WDC_ATA_ERR) 561 ata_bio->error = TIMEOUT; 562 wdc_ata_bio_done(chp, xfer); 563 return; 564 } 565 if (wdc_ata_err(drvp, ata_bio) == WDC_ATA_ERR) { 566 wdc_ata_bio_done(chp, xfer); 567 return; 568 } 569 #if NATA_PIOBM 570 if (xfer->c_flags & C_PIOBM) { 571 /* start the busmastering PIO */ 572 (*wdc->piobm_start)(wdc->dma_arg, 573 chp->ch_channel, xfer->c_drive, 574 xfer->c_skip, ata_bio->nbytes, 0); 575 chp->ch_flags |= ATACH_DMA_WAIT; 576 } else 577 #endif 578 579 wdc->dataout_pio(chp, drvp->drive_flags, 580 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 581 } 582 583 #if NATA_DMA 584 intr: 585 #endif 586 /* Wait for IRQ (either real or polled) */ 587 if ((ata_bio->flags & ATA_POLL) == 0) { 588 chp->ch_flags |= ATACH_IRQ_WAIT; 589 } else { 590 /* Wait for at last 400ns for status bit to be valid */ 591 delay(1); 592 #if NATA_DMA 593 if (chp->ch_flags & ATACH_DMA_WAIT) { 594 wdc_dmawait(chp, xfer, ATA_DELAY); 595 chp->ch_flags &= ~ATACH_DMA_WAIT; 596 } 597 #endif 598 wdc_ata_bio_intr(chp, xfer, 0); 599 if ((ata_bio->flags & ATA_ITSDONE) == 0) 600 goto again; 601 } 602 return; 603 timeout: 604 printf("%s:%d:%d: not ready, st=0x%02x, err=0x%02x\n", 605 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 606 chp->ch_status, chp->ch_error); 607 if (wdc_ata_err(drvp, ata_bio) != WDC_ATA_ERR) 608 ata_bio->error = TIMEOUT; 609 wdc_ata_bio_done(chp, xfer); 610 return; 611 } 612 613 static int 614 wdc_ata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 615 { 616 struct atac_softc *atac = chp->ch_atac; 617 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 618 struct ata_bio *ata_bio = xfer->c_cmd; 619 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 620 int drv_err; 621 622 ATADEBUG_PRINT(("wdc_ata_bio_intr %s:%d:%d\n", 623 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 624 DEBUG_INTR | DEBUG_XFERS); 625 626 627 /* Is it not a transfer, but a control operation? */ 628 if (drvp->state < READY) { 629 printf("%s:%d:%d: bad state %d in wdc_ata_bio_intr\n", 630 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 631 drvp->state); 632 panic("wdc_ata_bio_intr: bad state"); 633 } 634 635 /* 636 * if we missed an interrupt in a PIO transfer, reset and restart. 637 * Don't try to continue transfer, we may have missed cycles. 638 */ 639 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 640 ata_bio->error = TIMEOUT; 641 wdc_ata_bio_done(chp, xfer); 642 return 1; 643 } 644 645 #if NATA_PIOBM 646 /* Transfer-done interrupt for busmastering PIO read */ 647 if ((xfer->c_flags & C_PIOBM) && (chp->ch_flags & ATACH_PIOBM_WAIT)) { 648 chp->ch_flags &= ~ATACH_PIOBM_WAIT; 649 goto end; 650 } 651 #endif 652 653 /* Ack interrupt done by wdc_wait_for_unbusy */ 654 if (wdc_wait_for_unbusy(chp, (irq == 0) ? ATA_DELAY : 0, AT_POLL) < 0) { 655 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 656 return 0; /* IRQ was not for us */ 657 printf("%s:%d:%d: device timeout, c_bcount=%d, c_skip%d\n", 658 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 659 xfer->c_bcount, xfer->c_skip); 660 ata_bio->error = TIMEOUT; 661 wdc_ata_bio_done(chp, xfer); 662 return 1; 663 } 664 if (wdc->irqack) 665 wdc->irqack(chp); 666 667 drv_err = wdc_ata_err(drvp, ata_bio); 668 669 #if NATA_DMA 670 /* If we were using DMA, Turn off the DMA channel and check for error */ 671 if (xfer->c_flags & C_DMA) { 672 if (ata_bio->flags & ATA_POLL) { 673 /* 674 * IDE drives deassert WDCS_BSY before transfer is 675 * complete when using DMA. Polling for DRQ to deassert 676 * is not enough DRQ is not required to be 677 * asserted for DMA transfers, so poll for DRDY. 678 */ 679 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 680 ATA_DELAY, ATA_POLL) == WDCWAIT_TOUT) { 681 printf("%s:%d:%d: polled transfer timed out " 682 "(st=0x%x)\n", 683 device_xname(atac->atac_dev), 684 chp->ch_channel, xfer->c_drive, 685 chp->ch_status); 686 ata_bio->error = TIMEOUT; 687 drv_err = WDC_ATA_ERR; 688 } 689 } 690 if (wdc->dma_status != 0) { 691 if (drv_err != WDC_ATA_ERR) { 692 ata_bio->error = ERR_DMA; 693 drv_err = WDC_ATA_ERR; 694 } 695 } 696 if (chp->ch_status & WDCS_DRQ) { 697 if (drv_err != WDC_ATA_ERR) { 698 printf("%s:%d:%d: intr with DRQ (st=0x%x)\n", 699 device_xname(atac->atac_dev), 700 chp->ch_channel, 701 xfer->c_drive, chp->ch_status); 702 ata_bio->error = TIMEOUT; 703 drv_err = WDC_ATA_ERR; 704 } 705 } 706 if (drv_err != WDC_ATA_ERR) 707 goto end; 708 if (ata_bio->r_error & WDCE_CRC || ata_bio->error == ERR_DMA) 709 ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0); 710 } 711 #endif /* NATA_DMA */ 712 713 /* if we had an error, end */ 714 if (drv_err == WDC_ATA_ERR) { 715 wdc_ata_bio_done(chp, xfer); 716 return 1; 717 } 718 719 /* If this was a read and not using DMA, fetch the data. */ 720 if ((ata_bio->flags & ATA_READ) != 0) { 721 if ((chp->ch_status & WDCS_DRQ) != WDCS_DRQ) { 722 printf("%s:%d:%d: read intr before drq\n", 723 device_xname(atac->atac_dev), chp->ch_channel, 724 xfer->c_drive); 725 ata_bio->error = TIMEOUT; 726 wdc_ata_bio_done(chp, xfer); 727 return 1; 728 } 729 #if NATA_PIOBM 730 if (xfer->c_flags & C_PIOBM) { 731 /* start the busmastering PIO */ 732 (*wdc->piobm_start)(wdc->dma_arg, 733 chp->ch_channel, xfer->c_drive, 734 xfer->c_skip, ata_bio->nbytes, 735 WDC_PIOBM_XFER_IRQ); 736 chp->ch_flags |= ATACH_DMA_WAIT | ATACH_PIOBM_WAIT | ATACH_IRQ_WAIT; 737 return 1; 738 } else 739 #endif 740 wdc->datain_pio(chp, drvp->drive_flags, 741 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 742 } 743 744 #if NATA_DMA || NATA_PIOBM 745 end: 746 #endif 747 ata_bio->blkno += ata_bio->nblks; 748 ata_bio->blkdone += ata_bio->nblks; 749 xfer->c_skip += ata_bio->nbytes; 750 xfer->c_bcount -= ata_bio->nbytes; 751 /* See if this transfer is complete. */ 752 if (xfer->c_bcount > 0) { 753 if ((ata_bio->flags & ATA_POLL) == 0) { 754 /* Start the next operation */ 755 _wdc_ata_bio_start(chp, xfer); 756 } else { 757 /* Let _wdc_ata_bio_start do the loop */ 758 return 1; 759 } 760 } else { /* Done with this transfer */ 761 ata_bio->error = NOERROR; 762 wdc_ata_bio_done(chp, xfer); 763 } 764 return 1; 765 } 766 767 static void 768 wdc_ata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 769 int reason) 770 { 771 struct ata_bio *ata_bio = xfer->c_cmd; 772 int drive = xfer->c_drive; 773 774 ata_free_xfer(chp, xfer); 775 776 ata_bio->flags |= ATA_ITSDONE; 777 switch (reason) { 778 case KILL_GONE: 779 ata_bio->error = ERR_NODEV; 780 break; 781 case KILL_RESET: 782 ata_bio->error = ERR_RESET; 783 break; 784 default: 785 printf("wdc_ata_bio_kill_xfer: unknown reason %d\n", 786 reason); 787 panic("wdc_ata_bio_kill_xfer"); 788 } 789 ata_bio->r_error = WDCE_ABRT; 790 ATADEBUG_PRINT(("wdc_ata_bio_kill_xfer: drv_done\n"), DEBUG_XFERS); 791 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 792 } 793 794 static void 795 wdc_ata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 796 { 797 struct ata_bio *ata_bio = xfer->c_cmd; 798 int drive = xfer->c_drive; 799 800 ATADEBUG_PRINT(("wdc_ata_bio_done %s:%d:%d: flags 0x%x\n", 801 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 802 xfer->c_drive, (u_int)xfer->c_flags), 803 DEBUG_XFERS); 804 805 callout_stop(&chp->ch_callout); 806 807 /* feed back residual bcount to our caller */ 808 ata_bio->bcount = xfer->c_bcount; 809 810 /* mark controller inactive and free xfer */ 811 chp->ch_queue->active_xfer = NULL; 812 ata_free_xfer(chp, xfer); 813 814 if (chp->ch_drive[drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 815 ata_bio->error = ERR_NODEV; 816 chp->ch_drive[drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 817 wakeup(&chp->ch_queue->active_xfer); 818 } 819 ata_bio->flags |= ATA_ITSDONE; 820 ATADEBUG_PRINT(("wdc_ata_done: drv_done\n"), DEBUG_XFERS); 821 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 822 ATADEBUG_PRINT(("atastart from wdc_ata_done, flags 0x%x\n", 823 chp->ch_flags), DEBUG_XFERS); 824 atastart(chp); 825 } 826 827 static int 828 wdc_ata_err(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 829 { 830 struct ata_channel *chp = drvp->chnl_softc; 831 ata_bio->error = 0; 832 if (chp->ch_status & WDCS_BSY) { 833 ata_bio->error = TIMEOUT; 834 return WDC_ATA_ERR; 835 } 836 837 if (chp->ch_status & WDCS_DWF) { 838 ata_bio->error = ERR_DF; 839 return WDC_ATA_ERR; 840 } 841 842 if (chp->ch_status & WDCS_ERR) { 843 ata_bio->error = ERROR; 844 ata_bio->r_error = chp->ch_error; 845 if (ata_bio->r_error & (WDCE_BBK | WDCE_UNC | WDCE_IDNF | 846 WDCE_ABRT | WDCE_TK0NF | WDCE_AMNF)) 847 return WDC_ATA_ERR; 848 return WDC_ATA_NOERR; 849 } 850 851 if (chp->ch_status & WDCS_CORR) 852 ata_bio->flags |= ATA_CORR; 853 return WDC_ATA_NOERR; 854 } 855 856 static int 857 wdc_ata_addref(struct ata_drive_datas *drvp) 858 { 859 struct ata_channel *chp = drvp->chnl_softc; 860 861 return (ata_addref(chp)); 862 } 863 864 static void 865 wdc_ata_delref(struct ata_drive_datas *drvp) 866 { 867 struct ata_channel *chp = drvp->chnl_softc; 868 869 ata_delref(chp); 870 } 871
Indexes created Thu Oct 23 22:10:10 GMT 2025