atareg.h revision 1.15
1 /* $NetBSD: atareg.h,v 1.15 2003/12/30 19:12:24 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _DEV_ATA_ATAREG_H_ 33 #define _DEV_ATA_ATAREG_H_ 34 35 /* 36 * Drive parameter structure for ATA/ATAPI. 37 * Bit fields: WDC_* : common to ATA/ATAPI 38 * ATA_* : ATA only 39 * ATAPI_* : ATAPI only. 40 */ 41 struct ataparams { 42 /* drive info */ 43 u_int16_t atap_config; /* 0: general configuration */ 44 #define WDC_CFG_ATAPI_MASK 0xc000 45 #define WDC_CFG_ATAPI 0x8000 46 #define ATA_CFG_REMOVABLE 0x0080 47 #define ATA_CFG_FIXED 0x0040 48 #define ATAPI_CFG_TYPE_MASK 0x1f00 49 #define ATAPI_CFG_TYPE(x) (((x) & ATAPI_CFG_TYPE_MASK) >> 8) 50 #define ATAPI_CFG_REMOV 0x0080 51 #define ATAPI_CFG_DRQ_MASK 0x0060 52 #define ATAPI_CFG_STD_DRQ 0x0000 53 #define ATAPI_CFG_IRQ_DRQ 0x0020 54 #define ATAPI_CFG_ACCEL_DRQ 0x0040 55 #define ATAPI_CFG_CMD_MASK 0x0003 56 #define ATAPI_CFG_CMD_12 0x0000 57 #define ATAPI_CFG_CMD_16 0x0001 58 /* words 1-9 are ATA only */ 59 u_int16_t atap_cylinders; /* 1: # of non-removable cylinders */ 60 u_int16_t __reserved1; 61 u_int16_t atap_heads; /* 3: # of heads */ 62 u_int16_t __retired1[2]; /* 4-5: # of unform. bytes/track */ 63 u_int16_t atap_sectors; /* 6: # of sectors */ 64 u_int16_t __retired2[3]; 65 66 u_int8_t atap_serial[20]; /* 10-19: serial number */ 67 u_int16_t __retired3[2]; 68 u_int16_t __obsolete1; 69 u_int8_t atap_revision[8]; /* 23-26: firmware revision */ 70 u_int8_t atap_model[40]; /* 27-46: model number */ 71 u_int16_t atap_multi; /* 47: maximum sectors per irq (ATA) */ 72 u_int16_t __reserved2; 73 u_int16_t atap_capabilities1; /* 49: capability flags */ 74 #define WDC_CAP_IORDY 0x0800 75 #define WDC_CAP_IORDY_DSBL 0x0400 76 #define WDC_CAP_LBA 0x0200 77 #define WDC_CAP_DMA 0x0100 78 #define ATA_CAP_STBY 0x2000 79 #define ATAPI_CAP_INTERL_DMA 0x8000 80 #define ATAPI_CAP_CMD_QUEUE 0x4000 81 #define ATAPI_CAP_OVERLP 0X2000 82 #define ATAPI_CAP_ATA_RST 0x1000 83 u_int16_t atap_capabilities2; /* 50: capability flags (ATA) */ 84 #if BYTE_ORDER == LITTLE_ENDIAN 85 u_int8_t __junk2; 86 u_int8_t atap_oldpiotiming; /* 51: old PIO timing mode */ 87 u_int8_t __junk3; 88 u_int8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */ 89 #else 90 u_int8_t atap_oldpiotiming; /* 51: old PIO timing mode */ 91 u_int8_t __junk2; 92 u_int8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */ 93 u_int8_t __junk3; 94 #endif 95 u_int16_t atap_extensions; /* 53: extensions supported */ 96 #define WDC_EXT_UDMA_MODES 0x0004 97 #define WDC_EXT_MODES 0x0002 98 #define WDC_EXT_GEOM 0x0001 99 /* words 54-62 are ATA only */ 100 u_int16_t atap_curcylinders; /* 54: current logical cylinders */ 101 u_int16_t atap_curheads; /* 55: current logical heads */ 102 u_int16_t atap_cursectors; /* 56: current logical sectors/tracks */ 103 u_int16_t atap_curcapacity[2]; /* 57-58: current capacity */ 104 u_int16_t atap_curmulti; /* 59: current multi-sector setting */ 105 #define WDC_MULTI_VALID 0x0100 106 #define WDC_MULTI_MASK 0x00ff 107 u_int16_t atap_capacity[2]; /* 60-61: total capacity (LBA only) */ 108 u_int16_t __retired4; 109 #if BYTE_ORDER == LITTLE_ENDIAN 110 u_int8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */ 111 u_int8_t atap_dmamode_act; /* multiword DMA mode active */ 112 u_int8_t atap_piomode_supp; /* 64: PIO mode supported */ 113 u_int8_t __junk4; 114 #else 115 u_int8_t atap_dmamode_act; /* multiword DMA mode active */ 116 u_int8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */ 117 u_int8_t __junk4; 118 u_int8_t atap_piomode_supp; /* 64: PIO mode supported */ 119 #endif 120 u_int16_t atap_dmatiming_mimi; /* 65: minimum DMA cycle time */ 121 u_int16_t atap_dmatiming_recom; /* 66: recommended DMA cycle time */ 122 u_int16_t atap_piotiming; /* 67: mini PIO cycle time without FC */ 123 u_int16_t atap_piotiming_iordy; /* 68: mini PIO cycle time with IORDY FC */ 124 u_int16_t __reserved3[2]; 125 /* words 71-72 are ATAPI only */ 126 u_int16_t atap_pkt_br; /* 71: time (ns) to bus release */ 127 u_int16_t atap_pkt_bsyclr; /* 72: tme to clear BSY after service */ 128 u_int16_t __reserved4[2]; 129 u_int16_t atap_queuedepth; /* 75: */ 130 #define WDC_QUEUE_DEPTH_MASK 0x0F 131 u_int16_t atap_sata_caps;/* 76: */ 132 #define SATA_SIGNAL_GEN1 0x02 133 #define SATA_SIGNAL_GEN2 0x04 134 #define SATA_NATIVE_CMDQ 0x0100 135 #define SATA_HOST_PWR_MGMT 0x0200 136 u_int16_t atap_sata_reserved; /* 77: */ 137 u_int16_t atap_sata_features_supp; /* 78: */ 138 #define SATA_NONZERO_OFFSETS 0x02 139 #define SATA_DMA_SETUP_AUTO 0x04 140 #define SATA_DRIVE_PWR_MGMT 0x08 141 u_int16_t atap_sata_features_en; /* 79: */ 142 u_int16_t atap_ata_major; /* 80: Major version number */ 143 #define WDC_VER_ATA1 0x0002 144 #define WDC_VER_ATA2 0x0004 145 #define WDC_VER_ATA3 0x0008 146 #define WDC_VER_ATA4 0x0010 147 #define WDC_VER_ATA5 0x0020 148 #define WDC_VER_ATA6 0x0040 149 #define WDC_VER_ATA7 0x0080 150 u_int16_t atap_ata_minor; /* 81: Minor version number */ 151 u_int16_t atap_cmd_set1; /* 82: command set supported */ 152 #define WDC_CMD1_NOP 0x4000 /* NOP */ 153 #define WDC_CMD1_RB 0x2000 /* READ BUFFER */ 154 #define WDC_CMD1_WB 0x1000 /* WRITE BUFFER */ 155 /* 0x0800 Obsolete */ 156 #define WDC_CMD1_HPA 0x0400 /* Host Protected Area */ 157 #define WDC_CMD1_DVRST 0x0200 /* DEVICE RESET */ 158 #define WDC_CMD1_SRV 0x0100 /* SERVICE */ 159 #define WDC_CMD1_RLSE 0x0080 /* release interrupt */ 160 #define WDC_CMD1_AHEAD 0x0040 /* look-ahead */ 161 #define WDC_CMD1_CACHE 0x0020 /* write cache */ 162 #define WDC_CMD1_PKT 0x0010 /* PACKET */ 163 #define WDC_CMD1_PM 0x0008 /* Power Management */ 164 #define WDC_CMD1_REMOV 0x0004 /* Removable Media */ 165 #define WDC_CMD1_SEC 0x0002 /* Security Mode */ 166 #define WDC_CMD1_SMART 0x0001 /* SMART */ 167 u_int16_t atap_cmd_set2; /* 83: command set supported */ 168 #define ATA_CMD2_FCE 0x2000 /* FLUSH CACHE EXT */ 169 #define WDC_CMD2_FC 0x1000 /* FLUSH CACHE */ 170 #define WDC_CMD2_DCO 0x0800 /* Device Configuration Overlay */ 171 #define ATA_CMD2_LBA48 0x0400 /* 48-bit Address */ 172 #define WDC_CMD2_AAM 0x0200 /* Automatic Acoustic Management */ 173 #define WDC_CMD2_SM 0x0100 /* SET MAX security extention */ 174 #define WDC_CMD2_SFREQ 0x0040 /* SET FEATURE is required 175 to spin-up after power-up */ 176 #define WDC_CMD2_PUIS 0x0020 /* Power-Up In Standby */ 177 #define WDC_CMD2_RMSN 0x0010 /* Removable Media Status Notify */ 178 #define ATA_CMD2_APM 0x0008 /* Advanced Power Management */ 179 #define ATA_CMD2_CFA 0x0004 /* CFA */ 180 #define ATA_CMD2_RWQ 0x0002 /* READ/WRITE DMA QUEUED */ 181 #define WDC_CMD2_DM 0x0001 /* DOWNLOAD MICROCODE */ 182 u_int16_t atap_cmd_ext; /* 84: command/features supp. ext. */ 183 #define ATA_CMDE_TLCONT 0x1000 /* Time-limited R/W Continuous */ 184 #define ATA_CMDE_TL 0x0800 /* Time-limited R/W */ 185 #define ATA_CMDE_URGW 0x0400 /* URG for WRITE STREAM DMA/PIO */ 186 #define ATA_CMDE_URGR 0x0200 /* URG for READ STREAM DMA/PIO */ 187 #define ATA_CMDE_WWN 0x0100 /* World Wide name */ 188 #define ATA_CMDE_WQFE 0x0080 /* WRITE DMA QUEUED FUA EXT */ 189 #define ATA_CMDE_WFE 0x0040 /* WRITE DMA/MULTIPLE FUA EXT */ 190 #define ATA_CMDE_GPL 0x0020 /* General Purpose Logging */ 191 #define ATA_CMDE_STREAM 0x0010 /* Streaming */ 192 #define ATA_CMDE_MCPTC 0x0008 /* Media Card Pass Through Cmd */ 193 #define ATA_CMDE_MS 0x0004 /* Media serial number */ 194 #define ATA_CMDE_SST 0x0002 /* SMART self-test */ 195 #define ATA_CMDE_SEL 0x0001 /* SMART error logging */ 196 u_int16_t atap_cmd1_en; /* 85: cmd/features enabled */ 197 /* bits are the same as atap_cmd_set1 */ 198 u_int16_t atap_cmd2_en; /* 86: cmd/features enabled */ 199 /* bits are the same as atap_cmd_set2 */ 200 u_int16_t atap_cmd_def; /* 87: cmd/features default */ 201 #if BYTE_ORDER == LITTLE_ENDIAN 202 u_int8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */ 203 u_int8_t atap_udmamode_act; /* Ultra-DMA mode active */ 204 #else 205 u_int8_t atap_udmamode_act; /* Ultra-DMA mode active */ 206 u_int8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */ 207 #endif 208 /* 89-92 are ATA-only */ 209 u_int16_t atap_seu_time; /* 89: Sec. Erase Unit compl. time */ 210 u_int16_t atap_eseu_time; /* 90: Enhanced SEU compl. time */ 211 u_int16_t atap_apm_val; /* 91: current APM value */ 212 u_int16_t __reserved6[35]; /* 92-126: reserved */ 213 u_int16_t atap_rmsn_supp; /* 127: remov. media status notif. */ 214 #define WDC_RMSN_SUPP_MASK 0x0003 215 #define WDC_RMSN_SUPP 0x0001 216 u_int16_t atap_sec_st; /* 128: security status */ 217 #define WDC_SEC_LEV_MAX 0x0100 218 #define WDC_SEC_ESE_SUPP 0x0020 219 #define WDC_SEC_EXP 0x0010 220 #define WDC_SEC_FROZEN 0x0008 221 #define WDC_SEC_LOCKED 0x0004 222 #define WDC_SEC_EN 0x0002 223 #define WDC_SEC_SUPP 0x0001 224 }; 225 226 /* 227 * If WDSM_ATTR_ADVISORY, device exceeded intended design life period. 228 * If not WDSM_ATTR_ADVISORY, imminent data loss predicted. 229 */ 230 #define WDSM_ATTR_ADVISORY 1 231 232 /* 233 * If WDSM_ATTR_COLLECTIVE, attribute only updated in off-line testing. 234 * If not WDSM_ATTR_COLLECTIVE, attribute updated also in on-line testing. 235 */ 236 #define WDSM_ATTR_COLLECTIVE 2 237 238 struct ata_smart_attr { 239 u_int8_t id; /* attribute id number */ 240 u_int16_t flags; 241 u_int8_t value; /* attribute value */ 242 u_int8_t worst; 243 u_int8_t raw[6]; 244 u_int8_t reserved; 245 } __attribute__((packed)); 246 247 struct ata_smart_attributes { 248 u_int16_t data_structure_revision; 249 struct ata_smart_attr attributes[30]; 250 u_int8_t offline_data_collection_status; 251 u_int8_t self_test_exec_status; 252 u_int16_t total_time_to_complete_off_line; 253 u_int8_t vendor_specific_366; 254 u_int8_t offline_data_collection_capability; 255 u_int16_t smart_capability; 256 u_int8_t errorlog_capability; 257 u_int8_t vendor_specific_371; 258 u_int8_t short_test_completion_time; 259 u_int8_t extend_test_completion_time; 260 u_int8_t reserved_374_385[12]; 261 u_int8_t vendor_specific_386_509[125]; 262 int8_t checksum; 263 } __attribute__((packed)); 264 265 struct ata_smart_thresh { 266 u_int8_t id; 267 u_int8_t value; 268 u_int8_t reserved[10]; 269 } __attribute__((packed)); 270 271 struct ata_smart_thresholds { 272 u_int16_t data_structure_revision; 273 struct ata_smart_thresh thresholds[30]; 274 u_int8_t reserved[18]; 275 u_int8_t vendor_specific[131]; 276 int8_t checksum; 277 } __attribute__((packed)); 278 279 struct ata_smart_selftest { 280 u_int8_t number; 281 u_int8_t status; 282 uint16_t time_stamp; 283 u_int8_t failure_check_point; 284 u_int32_t lba_first_error; 285 u_int8_t vendor_specific[15]; 286 } __attribute__((packed)); 287 288 struct ata_smart_selftestlog { 289 u_int16_t data_structure_revision; 290 struct ata_smart_selftest log_entries[21]; 291 u_int8_t vendorspecific[2]; 292 u_int8_t mostrecenttest; 293 u_int8_t reserved[2]; 294 u_int8_t checksum; 295 } __attribute__((packed)); 296 297 #endif /* _DEV_ATA_ATAREG_H_ */ 298
Indexes created Wed Oct 01 07:09:59 GMT 2025