atareg.h revision 1.18
1 /* $NetBSD: atareg.h,v 1.18 2004/05/03 20:11:40 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to Berkeley by 37 * William Jolitz. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. Neither the name of the University nor the names of its contributors 48 * may be used to endorse or promote products derived from this software 49 * without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 52 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 53 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 54 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 55 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 56 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 57 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 59 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 60 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 61 * SUCH DAMAGE. 62 * 63 * @(#)wdreg.h 7.1 (Berkeley) 5/9/91 64 */ 65 66 #ifndef _DEV_ATA_ATAREG_H_ 67 #define _DEV_ATA_ATAREG_H_ 68 69 /* 70 * ATA Task File register definitions. 71 */ 72 73 /* Status bits. */ 74 #define WDCS_BSY 0x80 /* busy */ 75 #define WDCS_DRDY 0x40 /* drive ready */ 76 #define WDCS_DWF 0x20 /* drive write fault */ 77 #define WDCS_DSC 0x10 /* drive seek complete */ 78 #define WDCS_DRQ 0x08 /* data request */ 79 #define WDCS_CORR 0x04 /* corrected data */ 80 #define WDCS_IDX 0x02 /* index */ 81 #define WDCS_ERR 0x01 /* error */ 82 #define WDCS_BITS \ 83 "\020\010bsy\007drdy\006dwf\005dsc\004drq\003corr\002idx\001err" 84 85 /* Error bits. */ 86 #define WDCE_BBK 0x80 /* bad block detected */ 87 #define WDCE_CRC 0x80 /* CRC error (Ultra-DMA only) */ 88 #define WDCE_UNC 0x40 /* uncorrectable data error */ 89 #define WDCE_MC 0x20 /* media changed */ 90 #define WDCE_IDNF 0x10 /* id not found */ 91 #define WDCE_MCR 0x08 /* media change requested */ 92 #define WDCE_ABRT 0x04 /* aborted command */ 93 #define WDCE_TK0NF 0x02 /* track 0 not found */ 94 #define WDCE_AMNF 0x01 /* address mark not found */ 95 96 /* Commands for Disk Controller. */ 97 #define WDCC_NOP 0x00 /* Always fail with "aborted command" */ 98 #define WDCC_RECAL 0x10 /* disk restore code -- resets cntlr */ 99 100 #define WDCC_READ 0x20 /* disk read code */ 101 #define WDCC_WRITE 0x30 /* disk write code */ 102 #define WDCC__LONG 0x02 /* modifier -- access ecc bytes */ 103 #define WDCC__NORETRY 0x01 /* modifier -- no retrys */ 104 105 #define WDCC_FORMAT 0x50 /* disk format code */ 106 #define WDCC_DIAGNOSE 0x90 /* controller diagnostic */ 107 #define WDCC_IDP 0x91 /* initialize drive parameters */ 108 109 #define WDCC_SMART 0xb0 /* Self Mon, Analysis, Reporting Tech */ 110 111 #define WDCC_READMULTI 0xc4 /* read multiple */ 112 #define WDCC_WRITEMULTI 0xc5 /* write multiple */ 113 #define WDCC_SETMULTI 0xc6 /* set multiple mode */ 114 115 #define WDCC_READDMA 0xc8 /* read with DMA */ 116 #define WDCC_WRITEDMA 0xca /* write with DMA */ 117 118 #define WDCC_ACKMC 0xdb /* acknowledge media change */ 119 #define WDCC_LOCK 0xde /* lock drawer */ 120 #define WDCC_UNLOCK 0xdf /* unlock drawer */ 121 122 #define WDCC_FLUSHCACHE 0xe7 /* Flush cache */ 123 #define WDCC_FLUSHCACHE_EXT 0xea /* Flush cache ext */ 124 #define WDCC_IDENTIFY 0xec /* read parameters from controller */ 125 #define SET_FEATURES 0xef /* set features */ 126 127 #define WDCC_IDLE 0xe3 /* set idle timer & enter idle mode */ 128 #define WDCC_IDLE_IMMED 0xe1 /* enter idle mode */ 129 #define WDCC_SLEEP 0xe6 /* enter sleep mode */ 130 #define WDCC_STANDBY 0xe2 /* set standby timer & enter standby */ 131 #define WDCC_STANDBY_IMMED 0xe0 /* enter standby mode */ 132 #define WDCC_CHECK_PWR 0xe5 /* check power mode */ 133 134 /* Big Drive support */ 135 #define WDCC_READ_EXT 0x24 /* read 48-bit addressing */ 136 #define WDCC_WRITE_EXT 0x34 /* write 48-bit addressing */ 137 138 #define WDCC_READMULTI_EXT 0x29 /* read multiple 48-bit addressing */ 139 #define WDCC_WRITEMULTI_EXT 0x39 /* write multiple 48-bit addressing */ 140 141 #define WDCC_READDMA_EXT 0x25 /* read 48-bit addressing with DMA */ 142 #define WDCC_WRITEDMA_EXT 0x35 /* write 48-bit addressing with DMA */ 143 144 /* Subcommands for SET_FEATURES (features register) */ 145 #define WDSF_WRITE_CACHE_EN 0x02 146 #define WDSF_SET_MODE 0x03 147 #define WDSF_REASSIGN_EN 0x04 148 #define WDSF_RETRY_DS 0x33 149 #define WDSF_SET_CACHE_SGMT 0x54 150 #define WDSF_READAHEAD_DS 0x55 151 #define WDSF_POD_DS 0x66 152 #define WDSF_ECC_DS 0x77 153 #define WDSF_WRITE_CACHE_DS 0x82 154 #define WDSF_REASSIGN_DS 0x84 155 #define WDSF_ECC_EN 0x88 156 #define WDSF_RETRY_EN 0x99 157 #define WDSF_SET_CURRENT 0x9a 158 #define WDSF_READAHEAD_EN 0xaa 159 #define WDSF_PREFETCH_SET 0xab 160 #define WDSF_POD_EN 0xcc 161 162 /* Subcommands for SMART (features register) */ 163 #define WDSM_RD_DATA 0xd0 164 #define WDSM_RD_THRESHOLDS 0xd1 165 #define WDSM_ATTR_AUTOSAVE_EN 0xd2 166 #define WDSM_SAVE_ATTR 0xd3 167 #define WDSM_EXEC_OFFL_IMM 0xd4 168 #define WDSM_RD_LOG 0xd5 169 #define WDSM_ENABLE_OPS 0xd8 170 #define WDSM_DISABLE_OPS 0xd9 171 #define WDSM_STATUS 0xda 172 173 #define WDSMART_CYL 0xc24f 174 175 /* parameters uploaded to device/heads register */ 176 #define WDSD_IBM 0xa0 /* forced to 512 byte sector, ecc */ 177 #define WDSD_CHS 0x00 /* cylinder/head/sector addressing */ 178 #define WDSD_LBA 0x40 /* logical block addressing */ 179 180 /* Commands for ATAPI devices */ 181 #define ATAPI_CHECK_POWER_MODE 0xe5 182 #define ATAPI_EXEC_DRIVE_DIAGS 0x90 183 #define ATAPI_IDLE_IMMEDIATE 0xe1 184 #define ATAPI_NOP 0x00 185 #define ATAPI_PKT_CMD 0xa0 186 #define ATAPI_IDENTIFY_DEVICE 0xa1 187 #define ATAPI_SOFT_RESET 0x08 188 #define ATAPI_SLEEP 0xe6 189 #define ATAPI_STANDBY_IMMEDIATE 0xe0 190 191 /* Bytes used by ATAPI_PACKET_COMMAND (feature register) */ 192 #define ATAPI_PKT_CMD_FTRE_DMA 0x01 193 #define ATAPI_PKT_CMD_FTRE_OVL 0x02 194 195 /* ireason */ 196 #define WDCI_CMD 0x01 /* command(1) or data(0) */ 197 #define WDCI_IN 0x02 /* transfer to(1) or from(0) the host */ 198 #define WDCI_RELEASE 0x04 /* bus released until completion */ 199 200 #define PHASE_CMDOUT (WDCS_DRQ | WDCI_CMD) 201 #define PHASE_DATAIN (WDCS_DRQ | WDCI_IN) 202 #define PHASE_DATAOUT (WDCS_DRQ) 203 #define PHASE_COMPLETED (WDCI_IN | WDCI_CMD) 204 #define PHASE_ABORTED (0) 205 206 /* 207 * Drive parameter structure for ATA/ATAPI. 208 * Bit fields: WDC_* : common to ATA/ATAPI 209 * ATA_* : ATA only 210 * ATAPI_* : ATAPI only. 211 */ 212 struct ataparams { 213 /* drive info */ 214 u_int16_t atap_config; /* 0: general configuration */ 215 #define WDC_CFG_ATAPI_MASK 0xc000 216 #define WDC_CFG_ATAPI 0x8000 217 #define ATA_CFG_REMOVABLE 0x0080 218 #define ATA_CFG_FIXED 0x0040 219 #define ATAPI_CFG_TYPE_MASK 0x1f00 220 #define ATAPI_CFG_TYPE(x) (((x) & ATAPI_CFG_TYPE_MASK) >> 8) 221 #define ATAPI_CFG_REMOV 0x0080 222 #define ATAPI_CFG_DRQ_MASK 0x0060 223 #define ATAPI_CFG_STD_DRQ 0x0000 224 #define ATAPI_CFG_IRQ_DRQ 0x0020 225 #define ATAPI_CFG_ACCEL_DRQ 0x0040 226 #define ATAPI_CFG_CMD_MASK 0x0003 227 #define ATAPI_CFG_CMD_12 0x0000 228 #define ATAPI_CFG_CMD_16 0x0001 229 /* words 1-9 are ATA only */ 230 u_int16_t atap_cylinders; /* 1: # of non-removable cylinders */ 231 u_int16_t __reserved1; 232 u_int16_t atap_heads; /* 3: # of heads */ 233 u_int16_t __retired1[2]; /* 4-5: # of unform. bytes/track */ 234 u_int16_t atap_sectors; /* 6: # of sectors */ 235 u_int16_t __retired2[3]; 236 237 u_int8_t atap_serial[20]; /* 10-19: serial number */ 238 u_int16_t __retired3[2]; 239 u_int16_t __obsolete1; 240 u_int8_t atap_revision[8]; /* 23-26: firmware revision */ 241 u_int8_t atap_model[40]; /* 27-46: model number */ 242 u_int16_t atap_multi; /* 47: maximum sectors per irq (ATA) */ 243 u_int16_t __reserved2; 244 u_int16_t atap_capabilities1; /* 49: capability flags */ 245 #define WDC_CAP_IORDY 0x0800 246 #define WDC_CAP_IORDY_DSBL 0x0400 247 #define WDC_CAP_LBA 0x0200 248 #define WDC_CAP_DMA 0x0100 249 #define ATA_CAP_STBY 0x2000 250 #define ATAPI_CAP_INTERL_DMA 0x8000 251 #define ATAPI_CAP_CMD_QUEUE 0x4000 252 #define ATAPI_CAP_OVERLP 0X2000 253 #define ATAPI_CAP_ATA_RST 0x1000 254 u_int16_t atap_capabilities2; /* 50: capability flags (ATA) */ 255 #if BYTE_ORDER == LITTLE_ENDIAN 256 u_int8_t __junk2; 257 u_int8_t atap_oldpiotiming; /* 51: old PIO timing mode */ 258 u_int8_t __junk3; 259 u_int8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */ 260 #else 261 u_int8_t atap_oldpiotiming; /* 51: old PIO timing mode */ 262 u_int8_t __junk2; 263 u_int8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */ 264 u_int8_t __junk3; 265 #endif 266 u_int16_t atap_extensions; /* 53: extensions supported */ 267 #define WDC_EXT_UDMA_MODES 0x0004 268 #define WDC_EXT_MODES 0x0002 269 #define WDC_EXT_GEOM 0x0001 270 /* words 54-62 are ATA only */ 271 u_int16_t atap_curcylinders; /* 54: current logical cylinders */ 272 u_int16_t atap_curheads; /* 55: current logical heads */ 273 u_int16_t atap_cursectors; /* 56: current logical sectors/tracks */ 274 u_int16_t atap_curcapacity[2]; /* 57-58: current capacity */ 275 u_int16_t atap_curmulti; /* 59: current multi-sector setting */ 276 #define WDC_MULTI_VALID 0x0100 277 #define WDC_MULTI_MASK 0x00ff 278 u_int16_t atap_capacity[2]; /* 60-61: total capacity (LBA only) */ 279 u_int16_t __retired4; 280 #if BYTE_ORDER == LITTLE_ENDIAN 281 u_int8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */ 282 u_int8_t atap_dmamode_act; /* multiword DMA mode active */ 283 u_int8_t atap_piomode_supp; /* 64: PIO mode supported */ 284 u_int8_t __junk4; 285 #else 286 u_int8_t atap_dmamode_act; /* multiword DMA mode active */ 287 u_int8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */ 288 u_int8_t __junk4; 289 u_int8_t atap_piomode_supp; /* 64: PIO mode supported */ 290 #endif 291 u_int16_t atap_dmatiming_mimi; /* 65: minimum DMA cycle time */ 292 u_int16_t atap_dmatiming_recom; /* 66: recommended DMA cycle time */ 293 u_int16_t atap_piotiming; /* 67: mini PIO cycle time without FC */ 294 u_int16_t atap_piotiming_iordy; /* 68: mini PIO cycle time with IORDY FC */ 295 u_int16_t __reserved3[2]; 296 /* words 71-72 are ATAPI only */ 297 u_int16_t atap_pkt_br; /* 71: time (ns) to bus release */ 298 u_int16_t atap_pkt_bsyclr; /* 72: tme to clear BSY after service */ 299 u_int16_t __reserved4[2]; 300 u_int16_t atap_queuedepth; /* 75: */ 301 #define WDC_QUEUE_DEPTH_MASK 0x0F 302 u_int16_t atap_sata_caps;/* 76: */ 303 #define SATA_SIGNAL_GEN1 0x02 304 #define SATA_SIGNAL_GEN2 0x04 305 #define SATA_NATIVE_CMDQ 0x0100 306 #define SATA_HOST_PWR_MGMT 0x0200 307 u_int16_t atap_sata_reserved; /* 77: */ 308 u_int16_t atap_sata_features_supp; /* 78: */ 309 #define SATA_NONZERO_OFFSETS 0x02 310 #define SATA_DMA_SETUP_AUTO 0x04 311 #define SATA_DRIVE_PWR_MGMT 0x08 312 u_int16_t atap_sata_features_en; /* 79: */ 313 u_int16_t atap_ata_major; /* 80: Major version number */ 314 #define WDC_VER_ATA1 0x0002 315 #define WDC_VER_ATA2 0x0004 316 #define WDC_VER_ATA3 0x0008 317 #define WDC_VER_ATA4 0x0010 318 #define WDC_VER_ATA5 0x0020 319 #define WDC_VER_ATA6 0x0040 320 #define WDC_VER_ATA7 0x0080 321 u_int16_t atap_ata_minor; /* 81: Minor version number */ 322 u_int16_t atap_cmd_set1; /* 82: command set supported */ 323 #define WDC_CMD1_NOP 0x4000 /* NOP */ 324 #define WDC_CMD1_RB 0x2000 /* READ BUFFER */ 325 #define WDC_CMD1_WB 0x1000 /* WRITE BUFFER */ 326 /* 0x0800 Obsolete */ 327 #define WDC_CMD1_HPA 0x0400 /* Host Protected Area */ 328 #define WDC_CMD1_DVRST 0x0200 /* DEVICE RESET */ 329 #define WDC_CMD1_SRV 0x0100 /* SERVICE */ 330 #define WDC_CMD1_RLSE 0x0080 /* release interrupt */ 331 #define WDC_CMD1_AHEAD 0x0040 /* look-ahead */ 332 #define WDC_CMD1_CACHE 0x0020 /* write cache */ 333 #define WDC_CMD1_PKT 0x0010 /* PACKET */ 334 #define WDC_CMD1_PM 0x0008 /* Power Management */ 335 #define WDC_CMD1_REMOV 0x0004 /* Removable Media */ 336 #define WDC_CMD1_SEC 0x0002 /* Security Mode */ 337 #define WDC_CMD1_SMART 0x0001 /* SMART */ 338 u_int16_t atap_cmd_set2; /* 83: command set supported */ 339 #define ATA_CMD2_FCE 0x2000 /* FLUSH CACHE EXT */ 340 #define WDC_CMD2_FC 0x1000 /* FLUSH CACHE */ 341 #define WDC_CMD2_DCO 0x0800 /* Device Configuration Overlay */ 342 #define ATA_CMD2_LBA48 0x0400 /* 48-bit Address */ 343 #define WDC_CMD2_AAM 0x0200 /* Automatic Acoustic Management */ 344 #define WDC_CMD2_SM 0x0100 /* SET MAX security extension */ 345 #define WDC_CMD2_SFREQ 0x0040 /* SET FEATURE is required 346 to spin-up after power-up */ 347 #define WDC_CMD2_PUIS 0x0020 /* Power-Up In Standby */ 348 #define WDC_CMD2_RMSN 0x0010 /* Removable Media Status Notify */ 349 #define ATA_CMD2_APM 0x0008 /* Advanced Power Management */ 350 #define ATA_CMD2_CFA 0x0004 /* CFA */ 351 #define ATA_CMD2_RWQ 0x0002 /* READ/WRITE DMA QUEUED */ 352 #define WDC_CMD2_DM 0x0001 /* DOWNLOAD MICROCODE */ 353 u_int16_t atap_cmd_ext; /* 84: command/features supp. ext. */ 354 #define ATA_CMDE_TLCONT 0x1000 /* Time-limited R/W Continuous */ 355 #define ATA_CMDE_TL 0x0800 /* Time-limited R/W */ 356 #define ATA_CMDE_URGW 0x0400 /* URG for WRITE STREAM DMA/PIO */ 357 #define ATA_CMDE_URGR 0x0200 /* URG for READ STREAM DMA/PIO */ 358 #define ATA_CMDE_WWN 0x0100 /* World Wide name */ 359 #define ATA_CMDE_WQFE 0x0080 /* WRITE DMA QUEUED FUA EXT */ 360 #define ATA_CMDE_WFE 0x0040 /* WRITE DMA/MULTIPLE FUA EXT */ 361 #define ATA_CMDE_GPL 0x0020 /* General Purpose Logging */ 362 #define ATA_CMDE_STREAM 0x0010 /* Streaming */ 363 #define ATA_CMDE_MCPTC 0x0008 /* Media Card Pass Through Cmd */ 364 #define ATA_CMDE_MS 0x0004 /* Media serial number */ 365 #define ATA_CMDE_SST 0x0002 /* SMART self-test */ 366 #define ATA_CMDE_SEL 0x0001 /* SMART error logging */ 367 u_int16_t atap_cmd1_en; /* 85: cmd/features enabled */ 368 /* bits are the same as atap_cmd_set1 */ 369 u_int16_t atap_cmd2_en; /* 86: cmd/features enabled */ 370 /* bits are the same as atap_cmd_set2 */ 371 u_int16_t atap_cmd_def; /* 87: cmd/features default */ 372 #if BYTE_ORDER == LITTLE_ENDIAN 373 u_int8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */ 374 u_int8_t atap_udmamode_act; /* Ultra-DMA mode active */ 375 #else 376 u_int8_t atap_udmamode_act; /* Ultra-DMA mode active */ 377 u_int8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */ 378 #endif 379 /* 89-92 are ATA-only */ 380 u_int16_t atap_seu_time; /* 89: Sec. Erase Unit compl. time */ 381 u_int16_t atap_eseu_time; /* 90: Enhanced SEU compl. time */ 382 u_int16_t atap_apm_val; /* 91: current APM value */ 383 u_int16_t __reserved6[35]; /* 92-126: reserved */ 384 u_int16_t atap_rmsn_supp; /* 127: remov. media status notif. */ 385 #define WDC_RMSN_SUPP_MASK 0x0003 386 #define WDC_RMSN_SUPP 0x0001 387 u_int16_t atap_sec_st; /* 128: security status */ 388 #define WDC_SEC_LEV_MAX 0x0100 389 #define WDC_SEC_ESE_SUPP 0x0020 390 #define WDC_SEC_EXP 0x0010 391 #define WDC_SEC_FROZEN 0x0008 392 #define WDC_SEC_LOCKED 0x0004 393 #define WDC_SEC_EN 0x0002 394 #define WDC_SEC_SUPP 0x0001 395 }; 396 397 /* 398 * If WDSM_ATTR_ADVISORY, device exceeded intended design life period. 399 * If not WDSM_ATTR_ADVISORY, imminent data loss predicted. 400 */ 401 #define WDSM_ATTR_ADVISORY 1 402 403 /* 404 * If WDSM_ATTR_COLLECTIVE, attribute only updated in off-line testing. 405 * If not WDSM_ATTR_COLLECTIVE, attribute updated also in on-line testing. 406 */ 407 #define WDSM_ATTR_COLLECTIVE 2 408 409 /* 410 * ATA SMART attributes 411 */ 412 413 struct ata_smart_attr { 414 u_int8_t id; /* attribute id number */ 415 u_int16_t flags; 416 u_int8_t value; /* attribute value */ 417 u_int8_t worst; 418 u_int8_t raw[6]; 419 u_int8_t reserved; 420 } __attribute__((packed)); 421 422 struct ata_smart_attributes { 423 u_int16_t data_structure_revision; 424 struct ata_smart_attr attributes[30]; 425 u_int8_t offline_data_collection_status; 426 u_int8_t self_test_exec_status; 427 u_int16_t total_time_to_complete_off_line; 428 u_int8_t vendor_specific_366; 429 u_int8_t offline_data_collection_capability; 430 u_int16_t smart_capability; 431 u_int8_t errorlog_capability; 432 u_int8_t vendor_specific_371; 433 u_int8_t short_test_completion_time; 434 u_int8_t extend_test_completion_time; 435 u_int8_t reserved_374_385[12]; 436 u_int8_t vendor_specific_386_509[125]; 437 int8_t checksum; 438 } __attribute__((packed)); 439 440 struct ata_smart_thresh { 441 u_int8_t id; 442 u_int8_t value; 443 u_int8_t reserved[10]; 444 } __attribute__((packed)); 445 446 struct ata_smart_thresholds { 447 u_int16_t data_structure_revision; 448 struct ata_smart_thresh thresholds[30]; 449 u_int8_t reserved[18]; 450 u_int8_t vendor_specific[131]; 451 int8_t checksum; 452 } __attribute__((packed)); 453 454 struct ata_smart_selftest { 455 u_int8_t number; 456 u_int8_t status; 457 uint16_t time_stamp; 458 u_int8_t failure_check_point; 459 u_int32_t lba_first_error; 460 u_int8_t vendor_specific[15]; 461 } __attribute__((packed)); 462 463 struct ata_smart_selftestlog { 464 u_int16_t data_structure_revision; 465 struct ata_smart_selftest log_entries[21]; 466 u_int8_t vendorspecific[2]; 467 u_int8_t mostrecenttest; 468 u_int8_t reserved[2]; 469 u_int8_t checksum; 470 } __attribute__((packed)); 471 472 #endif /* _DEV_ATA_ATAREG_H_ */ 473
Indexes created Tue Sep 30 11:09:46 GMT 2025