atareg.h revision 1.20
1 /* $NetBSD: atareg.h,v 1.20 2004/08/21 02:17:07 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to Berkeley by 37 * William Jolitz. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. Neither the name of the University nor the names of its contributors 48 * may be used to endorse or promote products derived from this software 49 * without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 52 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 53 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 54 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 55 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 56 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 57 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 59 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 60 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 61 * SUCH DAMAGE. 62 * 63 * @(#)wdreg.h 7.1 (Berkeley) 5/9/91 64 */ 65 66 #ifndef _DEV_ATA_ATAREG_H_ 67 #define _DEV_ATA_ATAREG_H_ 68 69 /* 70 * ATA Task File register definitions. 71 */ 72 73 /* Status bits. */ 74 #define WDCS_BSY 0x80 /* busy */ 75 #define WDCS_DRDY 0x40 /* drive ready */ 76 #define WDCS_DWF 0x20 /* drive write fault */ 77 #define WDCS_DSC 0x10 /* drive seek complete */ 78 #define WDCS_DRQ 0x08 /* data request */ 79 #define WDCS_CORR 0x04 /* corrected data */ 80 #define WDCS_IDX 0x02 /* index */ 81 #define WDCS_ERR 0x01 /* error */ 82 #define WDCS_BITS \ 83 "\020\010bsy\007drdy\006dwf\005dsc\004drq\003corr\002idx\001err" 84 85 /* Error bits. */ 86 #define WDCE_BBK 0x80 /* bad block detected */ 87 #define WDCE_CRC 0x80 /* CRC error (Ultra-DMA only) */ 88 #define WDCE_UNC 0x40 /* uncorrectable data error */ 89 #define WDCE_MC 0x20 /* media changed */ 90 #define WDCE_IDNF 0x10 /* id not found */ 91 #define WDCE_MCR 0x08 /* media change requested */ 92 #define WDCE_ABRT 0x04 /* aborted command */ 93 #define WDCE_TK0NF 0x02 /* track 0 not found */ 94 #define WDCE_AMNF 0x01 /* address mark not found */ 95 96 /* Commands for Disk Controller. */ 97 #define WDCC_NOP 0x00 /* Always fail with "aborted command" */ 98 #define WDCC_RECAL 0x10 /* disk restore code -- resets cntlr */ 99 100 #define WDCC_READ 0x20 /* disk read code */ 101 #define WDCC_WRITE 0x30 /* disk write code */ 102 #define WDCC__LONG 0x02 /* modifier -- access ecc bytes */ 103 #define WDCC__NORETRY 0x01 /* modifier -- no retrys */ 104 105 #define WDCC_FORMAT 0x50 /* disk format code */ 106 #define WDCC_DIAGNOSE 0x90 /* controller diagnostic */ 107 #define WDCC_IDP 0x91 /* initialize drive parameters */ 108 109 #define WDCC_SMART 0xb0 /* Self Mon, Analysis, Reporting Tech */ 110 111 #define WDCC_READMULTI 0xc4 /* read multiple */ 112 #define WDCC_WRITEMULTI 0xc5 /* write multiple */ 113 #define WDCC_SETMULTI 0xc6 /* set multiple mode */ 114 115 #define WDCC_READDMA 0xc8 /* read with DMA */ 116 #define WDCC_WRITEDMA 0xca /* write with DMA */ 117 118 #define WDCC_ACKMC 0xdb /* acknowledge media change */ 119 #define WDCC_LOCK 0xde /* lock drawer */ 120 #define WDCC_UNLOCK 0xdf /* unlock drawer */ 121 122 #define WDCC_FLUSHCACHE 0xe7 /* Flush cache */ 123 #define WDCC_FLUSHCACHE_EXT 0xea /* Flush cache ext */ 124 #define WDCC_IDENTIFY 0xec /* read parameters from controller */ 125 #define SET_FEATURES 0xef /* set features */ 126 127 #define WDCC_IDLE 0xe3 /* set idle timer & enter idle mode */ 128 #define WDCC_IDLE_IMMED 0xe1 /* enter idle mode */ 129 #define WDCC_SLEEP 0xe6 /* enter sleep mode */ 130 #define WDCC_STANDBY 0xe2 /* set standby timer & enter standby */ 131 #define WDCC_STANDBY_IMMED 0xe0 /* enter standby mode */ 132 #define WDCC_CHECK_PWR 0xe5 /* check power mode */ 133 134 /* Big Drive support */ 135 #define WDCC_READ_EXT 0x24 /* read 48-bit addressing */ 136 #define WDCC_WRITE_EXT 0x34 /* write 48-bit addressing */ 137 138 #define WDCC_READMULTI_EXT 0x29 /* read multiple 48-bit addressing */ 139 #define WDCC_WRITEMULTI_EXT 0x39 /* write multiple 48-bit addressing */ 140 141 #define WDCC_READDMA_EXT 0x25 /* read 48-bit addressing with DMA */ 142 #define WDCC_WRITEDMA_EXT 0x35 /* write 48-bit addressing with DMA */ 143 144 /* Convert a 32-bit command to a 48-bit command. */ 145 static __inline int __unused 146 atacmd_to48(int cmd32) 147 { 148 switch (cmd32) { 149 case WDCC_READ: 150 return WDCC_READ_EXT; 151 case WDCC_WRITE: 152 return WDCC_WRITE_EXT; 153 case WDCC_READMULTI: 154 return WDCC_READMULTI_EXT; 155 case WDCC_WRITEMULTI: 156 return WDCC_WRITEMULTI_EXT; 157 case WDCC_READDMA: 158 return WDCC_READDMA_EXT; 159 case WDCC_WRITEDMA: 160 return WDCC_WRITEDMA_EXT; 161 default: 162 panic("atacmd_to48: illegal 32-bit command: %d", cmd32); 163 /* NOTREACHED */ 164 } 165 } 166 167 /* Native SATA command queueing */ 168 #define WDCC_READ_FPDMA_QUEUED 0x60 /* SATA native queued read (48bit) */ 169 #define WDCC_WRITE_FPDMA_QUEUED 0x61 /* SATA native queued write (48bit) */ 170 171 /* Convert a 32-bit command to a Native SATA Queued command. */ 172 static __inline int __unused 173 atacmd_tostatq(int cmd32) 174 { 175 switch (cmd32) { 176 case WDCC_READDMA: 177 return WDCC_READ_FPDMA_QUEUED; 178 case WDCC_WRITEDMA: 179 return WDCC_WRITE_FPDMA_QUEUED; 180 default: 181 panic("atacmd_tosataq: illegal 32-bit command: %d", cmd32); 182 /* NOTREACHED */ 183 } 184 } 185 186 /* Subcommands for SET_FEATURES (features register) */ 187 #define WDSF_WRITE_CACHE_EN 0x02 188 #define WDSF_SET_MODE 0x03 189 #define WDSF_REASSIGN_EN 0x04 190 #define WDSF_RETRY_DS 0x33 191 #define WDSF_SET_CACHE_SGMT 0x54 192 #define WDSF_READAHEAD_DS 0x55 193 #define WDSF_POD_DS 0x66 194 #define WDSF_ECC_DS 0x77 195 #define WDSF_WRITE_CACHE_DS 0x82 196 #define WDSF_REASSIGN_DS 0x84 197 #define WDSF_ECC_EN 0x88 198 #define WDSF_RETRY_EN 0x99 199 #define WDSF_SET_CURRENT 0x9a 200 #define WDSF_READAHEAD_EN 0xaa 201 #define WDSF_PREFETCH_SET 0xab 202 #define WDSF_POD_EN 0xcc 203 204 /* Subcommands for SMART (features register) */ 205 #define WDSM_RD_DATA 0xd0 206 #define WDSM_RD_THRESHOLDS 0xd1 207 #define WDSM_ATTR_AUTOSAVE_EN 0xd2 208 #define WDSM_SAVE_ATTR 0xd3 209 #define WDSM_EXEC_OFFL_IMM 0xd4 210 #define WDSM_RD_LOG 0xd5 211 #define WDSM_ENABLE_OPS 0xd8 212 #define WDSM_DISABLE_OPS 0xd9 213 #define WDSM_STATUS 0xda 214 215 #define WDSMART_CYL 0xc24f 216 217 /* parameters uploaded to device/heads register */ 218 #define WDSD_IBM 0xa0 /* forced to 512 byte sector, ecc */ 219 #define WDSD_CHS 0x00 /* cylinder/head/sector addressing */ 220 #define WDSD_LBA 0x40 /* logical block addressing */ 221 222 /* Commands for ATAPI devices */ 223 #define ATAPI_CHECK_POWER_MODE 0xe5 224 #define ATAPI_EXEC_DRIVE_DIAGS 0x90 225 #define ATAPI_IDLE_IMMEDIATE 0xe1 226 #define ATAPI_NOP 0x00 227 #define ATAPI_PKT_CMD 0xa0 228 #define ATAPI_IDENTIFY_DEVICE 0xa1 229 #define ATAPI_SOFT_RESET 0x08 230 #define ATAPI_SLEEP 0xe6 231 #define ATAPI_STANDBY_IMMEDIATE 0xe0 232 233 /* Bytes used by ATAPI_PACKET_COMMAND (feature register) */ 234 #define ATAPI_PKT_CMD_FTRE_DMA 0x01 235 #define ATAPI_PKT_CMD_FTRE_OVL 0x02 236 237 /* ireason */ 238 #define WDCI_CMD 0x01 /* command(1) or data(0) */ 239 #define WDCI_IN 0x02 /* transfer to(1) or from(0) the host */ 240 #define WDCI_RELEASE 0x04 /* bus released until completion */ 241 242 #define PHASE_CMDOUT (WDCS_DRQ | WDCI_CMD) 243 #define PHASE_DATAIN (WDCS_DRQ | WDCI_IN) 244 #define PHASE_DATAOUT (WDCS_DRQ) 245 #define PHASE_COMPLETED (WDCI_IN | WDCI_CMD) 246 #define PHASE_ABORTED (0) 247 248 /* 249 * Drive parameter structure for ATA/ATAPI. 250 * Bit fields: WDC_* : common to ATA/ATAPI 251 * ATA_* : ATA only 252 * ATAPI_* : ATAPI only. 253 */ 254 struct ataparams { 255 /* drive info */ 256 u_int16_t atap_config; /* 0: general configuration */ 257 #define WDC_CFG_ATAPI_MASK 0xc000 258 #define WDC_CFG_ATAPI 0x8000 259 #define ATA_CFG_REMOVABLE 0x0080 260 #define ATA_CFG_FIXED 0x0040 261 #define ATAPI_CFG_TYPE_MASK 0x1f00 262 #define ATAPI_CFG_TYPE(x) (((x) & ATAPI_CFG_TYPE_MASK) >> 8) 263 #define ATAPI_CFG_REMOV 0x0080 264 #define ATAPI_CFG_DRQ_MASK 0x0060 265 #define ATAPI_CFG_STD_DRQ 0x0000 266 #define ATAPI_CFG_IRQ_DRQ 0x0020 267 #define ATAPI_CFG_ACCEL_DRQ 0x0040 268 #define ATAPI_CFG_CMD_MASK 0x0003 269 #define ATAPI_CFG_CMD_12 0x0000 270 #define ATAPI_CFG_CMD_16 0x0001 271 /* words 1-9 are ATA only */ 272 u_int16_t atap_cylinders; /* 1: # of non-removable cylinders */ 273 u_int16_t __reserved1; 274 u_int16_t atap_heads; /* 3: # of heads */ 275 u_int16_t __retired1[2]; /* 4-5: # of unform. bytes/track */ 276 u_int16_t atap_sectors; /* 6: # of sectors */ 277 u_int16_t __retired2[3]; 278 279 u_int8_t atap_serial[20]; /* 10-19: serial number */ 280 u_int16_t __retired3[2]; 281 u_int16_t __obsolete1; 282 u_int8_t atap_revision[8]; /* 23-26: firmware revision */ 283 u_int8_t atap_model[40]; /* 27-46: model number */ 284 u_int16_t atap_multi; /* 47: maximum sectors per irq (ATA) */ 285 u_int16_t __reserved2; 286 u_int16_t atap_capabilities1; /* 49: capability flags */ 287 #define WDC_CAP_IORDY 0x0800 288 #define WDC_CAP_IORDY_DSBL 0x0400 289 #define WDC_CAP_LBA 0x0200 290 #define WDC_CAP_DMA 0x0100 291 #define ATA_CAP_STBY 0x2000 292 #define ATAPI_CAP_INTERL_DMA 0x8000 293 #define ATAPI_CAP_CMD_QUEUE 0x4000 294 #define ATAPI_CAP_OVERLP 0X2000 295 #define ATAPI_CAP_ATA_RST 0x1000 296 u_int16_t atap_capabilities2; /* 50: capability flags (ATA) */ 297 #if BYTE_ORDER == LITTLE_ENDIAN 298 u_int8_t __junk2; 299 u_int8_t atap_oldpiotiming; /* 51: old PIO timing mode */ 300 u_int8_t __junk3; 301 u_int8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */ 302 #else 303 u_int8_t atap_oldpiotiming; /* 51: old PIO timing mode */ 304 u_int8_t __junk2; 305 u_int8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */ 306 u_int8_t __junk3; 307 #endif 308 u_int16_t atap_extensions; /* 53: extensions supported */ 309 #define WDC_EXT_UDMA_MODES 0x0004 310 #define WDC_EXT_MODES 0x0002 311 #define WDC_EXT_GEOM 0x0001 312 /* words 54-62 are ATA only */ 313 u_int16_t atap_curcylinders; /* 54: current logical cylinders */ 314 u_int16_t atap_curheads; /* 55: current logical heads */ 315 u_int16_t atap_cursectors; /* 56: current logical sectors/tracks */ 316 u_int16_t atap_curcapacity[2]; /* 57-58: current capacity */ 317 u_int16_t atap_curmulti; /* 59: current multi-sector setting */ 318 #define WDC_MULTI_VALID 0x0100 319 #define WDC_MULTI_MASK 0x00ff 320 u_int16_t atap_capacity[2]; /* 60-61: total capacity (LBA only) */ 321 u_int16_t __retired4; 322 #if BYTE_ORDER == LITTLE_ENDIAN 323 u_int8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */ 324 u_int8_t atap_dmamode_act; /* multiword DMA mode active */ 325 u_int8_t atap_piomode_supp; /* 64: PIO mode supported */ 326 u_int8_t __junk4; 327 #else 328 u_int8_t atap_dmamode_act; /* multiword DMA mode active */ 329 u_int8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */ 330 u_int8_t __junk4; 331 u_int8_t atap_piomode_supp; /* 64: PIO mode supported */ 332 #endif 333 u_int16_t atap_dmatiming_mimi; /* 65: minimum DMA cycle time */ 334 u_int16_t atap_dmatiming_recom; /* 66: recommended DMA cycle time */ 335 u_int16_t atap_piotiming; /* 67: mini PIO cycle time without FC */ 336 u_int16_t atap_piotiming_iordy; /* 68: mini PIO cycle time with IORDY FC */ 337 u_int16_t __reserved3[2]; 338 /* words 71-72 are ATAPI only */ 339 u_int16_t atap_pkt_br; /* 71: time (ns) to bus release */ 340 u_int16_t atap_pkt_bsyclr; /* 72: tme to clear BSY after service */ 341 u_int16_t __reserved4[2]; 342 u_int16_t atap_queuedepth; /* 75: */ 343 #define WDC_QUEUE_DEPTH_MASK 0x0F 344 u_int16_t atap_sata_caps;/* 76: */ 345 #define SATA_SIGNAL_GEN1 0x02 346 #define SATA_SIGNAL_GEN2 0x04 347 #define SATA_NATIVE_CMDQ 0x0100 348 #define SATA_HOST_PWR_MGMT 0x0200 349 u_int16_t atap_sata_reserved; /* 77: */ 350 u_int16_t atap_sata_features_supp; /* 78: */ 351 #define SATA_NONZERO_OFFSETS 0x02 352 #define SATA_DMA_SETUP_AUTO 0x04 353 #define SATA_DRIVE_PWR_MGMT 0x08 354 u_int16_t atap_sata_features_en; /* 79: */ 355 u_int16_t atap_ata_major; /* 80: Major version number */ 356 #define WDC_VER_ATA1 0x0002 357 #define WDC_VER_ATA2 0x0004 358 #define WDC_VER_ATA3 0x0008 359 #define WDC_VER_ATA4 0x0010 360 #define WDC_VER_ATA5 0x0020 361 #define WDC_VER_ATA6 0x0040 362 #define WDC_VER_ATA7 0x0080 363 u_int16_t atap_ata_minor; /* 81: Minor version number */ 364 u_int16_t atap_cmd_set1; /* 82: command set supported */ 365 #define WDC_CMD1_NOP 0x4000 /* NOP */ 366 #define WDC_CMD1_RB 0x2000 /* READ BUFFER */ 367 #define WDC_CMD1_WB 0x1000 /* WRITE BUFFER */ 368 /* 0x0800 Obsolete */ 369 #define WDC_CMD1_HPA 0x0400 /* Host Protected Area */ 370 #define WDC_CMD1_DVRST 0x0200 /* DEVICE RESET */ 371 #define WDC_CMD1_SRV 0x0100 /* SERVICE */ 372 #define WDC_CMD1_RLSE 0x0080 /* release interrupt */ 373 #define WDC_CMD1_AHEAD 0x0040 /* look-ahead */ 374 #define WDC_CMD1_CACHE 0x0020 /* write cache */ 375 #define WDC_CMD1_PKT 0x0010 /* PACKET */ 376 #define WDC_CMD1_PM 0x0008 /* Power Management */ 377 #define WDC_CMD1_REMOV 0x0004 /* Removable Media */ 378 #define WDC_CMD1_SEC 0x0002 /* Security Mode */ 379 #define WDC_CMD1_SMART 0x0001 /* SMART */ 380 u_int16_t atap_cmd_set2; /* 83: command set supported */ 381 #define ATA_CMD2_FCE 0x2000 /* FLUSH CACHE EXT */ 382 #define WDC_CMD2_FC 0x1000 /* FLUSH CACHE */ 383 #define WDC_CMD2_DCO 0x0800 /* Device Configuration Overlay */ 384 #define ATA_CMD2_LBA48 0x0400 /* 48-bit Address */ 385 #define WDC_CMD2_AAM 0x0200 /* Automatic Acoustic Management */ 386 #define WDC_CMD2_SM 0x0100 /* SET MAX security extension */ 387 #define WDC_CMD2_SFREQ 0x0040 /* SET FEATURE is required 388 to spin-up after power-up */ 389 #define WDC_CMD2_PUIS 0x0020 /* Power-Up In Standby */ 390 #define WDC_CMD2_RMSN 0x0010 /* Removable Media Status Notify */ 391 #define ATA_CMD2_APM 0x0008 /* Advanced Power Management */ 392 #define ATA_CMD2_CFA 0x0004 /* CFA */ 393 #define ATA_CMD2_RWQ 0x0002 /* READ/WRITE DMA QUEUED */ 394 #define WDC_CMD2_DM 0x0001 /* DOWNLOAD MICROCODE */ 395 u_int16_t atap_cmd_ext; /* 84: command/features supp. ext. */ 396 #define ATA_CMDE_TLCONT 0x1000 /* Time-limited R/W Continuous */ 397 #define ATA_CMDE_TL 0x0800 /* Time-limited R/W */ 398 #define ATA_CMDE_URGW 0x0400 /* URG for WRITE STREAM DMA/PIO */ 399 #define ATA_CMDE_URGR 0x0200 /* URG for READ STREAM DMA/PIO */ 400 #define ATA_CMDE_WWN 0x0100 /* World Wide name */ 401 #define ATA_CMDE_WQFE 0x0080 /* WRITE DMA QUEUED FUA EXT */ 402 #define ATA_CMDE_WFE 0x0040 /* WRITE DMA/MULTIPLE FUA EXT */ 403 #define ATA_CMDE_GPL 0x0020 /* General Purpose Logging */ 404 #define ATA_CMDE_STREAM 0x0010 /* Streaming */ 405 #define ATA_CMDE_MCPTC 0x0008 /* Media Card Pass Through Cmd */ 406 #define ATA_CMDE_MS 0x0004 /* Media serial number */ 407 #define ATA_CMDE_SST 0x0002 /* SMART self-test */ 408 #define ATA_CMDE_SEL 0x0001 /* SMART error logging */ 409 u_int16_t atap_cmd1_en; /* 85: cmd/features enabled */ 410 /* bits are the same as atap_cmd_set1 */ 411 u_int16_t atap_cmd2_en; /* 86: cmd/features enabled */ 412 /* bits are the same as atap_cmd_set2 */ 413 u_int16_t atap_cmd_def; /* 87: cmd/features default */ 414 #if BYTE_ORDER == LITTLE_ENDIAN 415 u_int8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */ 416 u_int8_t atap_udmamode_act; /* Ultra-DMA mode active */ 417 #else 418 u_int8_t atap_udmamode_act; /* Ultra-DMA mode active */ 419 u_int8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */ 420 #endif 421 /* 89-92 are ATA-only */ 422 u_int16_t atap_seu_time; /* 89: Sec. Erase Unit compl. time */ 423 u_int16_t atap_eseu_time; /* 90: Enhanced SEU compl. time */ 424 u_int16_t atap_apm_val; /* 91: current APM value */ 425 u_int16_t __reserved6[35]; /* 92-126: reserved */ 426 u_int16_t atap_rmsn_supp; /* 127: remov. media status notif. */ 427 #define WDC_RMSN_SUPP_MASK 0x0003 428 #define WDC_RMSN_SUPP 0x0001 429 u_int16_t atap_sec_st; /* 128: security status */ 430 #define WDC_SEC_LEV_MAX 0x0100 431 #define WDC_SEC_ESE_SUPP 0x0020 432 #define WDC_SEC_EXP 0x0010 433 #define WDC_SEC_FROZEN 0x0008 434 #define WDC_SEC_LOCKED 0x0004 435 #define WDC_SEC_EN 0x0002 436 #define WDC_SEC_SUPP 0x0001 437 }; 438 439 /* 440 * If WDSM_ATTR_ADVISORY, device exceeded intended design life period. 441 * If not WDSM_ATTR_ADVISORY, imminent data loss predicted. 442 */ 443 #define WDSM_ATTR_ADVISORY 1 444 445 /* 446 * If WDSM_ATTR_COLLECTIVE, attribute only updated in off-line testing. 447 * If not WDSM_ATTR_COLLECTIVE, attribute updated also in on-line testing. 448 */ 449 #define WDSM_ATTR_COLLECTIVE 2 450 451 /* 452 * ATA SMART attributes 453 */ 454 455 struct ata_smart_attr { 456 u_int8_t id; /* attribute id number */ 457 u_int16_t flags; 458 u_int8_t value; /* attribute value */ 459 u_int8_t worst; 460 u_int8_t raw[6]; 461 u_int8_t reserved; 462 } __attribute__((packed)); 463 464 struct ata_smart_attributes { 465 u_int16_t data_structure_revision; 466 struct ata_smart_attr attributes[30]; 467 u_int8_t offline_data_collection_status; 468 u_int8_t self_test_exec_status; 469 u_int16_t total_time_to_complete_off_line; 470 u_int8_t vendor_specific_366; 471 u_int8_t offline_data_collection_capability; 472 u_int16_t smart_capability; 473 u_int8_t errorlog_capability; 474 u_int8_t vendor_specific_371; 475 u_int8_t short_test_completion_time; 476 u_int8_t extend_test_completion_time; 477 u_int8_t reserved_374_385[12]; 478 u_int8_t vendor_specific_386_509[125]; 479 int8_t checksum; 480 } __attribute__((packed)); 481 482 struct ata_smart_thresh { 483 u_int8_t id; 484 u_int8_t value; 485 u_int8_t reserved[10]; 486 } __attribute__((packed)); 487 488 struct ata_smart_thresholds { 489 u_int16_t data_structure_revision; 490 struct ata_smart_thresh thresholds[30]; 491 u_int8_t reserved[18]; 492 u_int8_t vendor_specific[131]; 493 int8_t checksum; 494 } __attribute__((packed)); 495 496 struct ata_smart_selftest { 497 u_int8_t number; 498 u_int8_t status; 499 uint16_t time_stamp; 500 u_int8_t failure_check_point; 501 u_int32_t lba_first_error; 502 u_int8_t vendor_specific[15]; 503 } __attribute__((packed)); 504 505 struct ata_smart_selftestlog { 506 u_int16_t data_structure_revision; 507 struct ata_smart_selftest log_entries[21]; 508 u_int8_t vendorspecific[2]; 509 u_int8_t mostrecenttest; 510 u_int8_t reserved[2]; 511 u_int8_t checksum; 512 } __attribute__((packed)); 513 514 #endif /* _DEV_ATA_ATAREG_H_ */ 515
Indexes created Tue Sep 30 11:09:46 GMT 2025