atareg.h revision 1.21
1 /* $NetBSD: atareg.h,v 1.21 2004/08/23 10:08:48 he Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to Berkeley by 37 * William Jolitz. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. Neither the name of the University nor the names of its contributors 48 * may be used to endorse or promote products derived from this software 49 * without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 52 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 53 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 54 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 55 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 56 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 57 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 59 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 60 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 61 * SUCH DAMAGE. 62 * 63 * @(#)wdreg.h 7.1 (Berkeley) 5/9/91 64 */ 65 66 #ifndef _DEV_ATA_ATAREG_H_ 67 #define _DEV_ATA_ATAREG_H_ 68 69 /* 70 * ATA Task File register definitions. 71 */ 72 73 /* Status bits. */ 74 #define WDCS_BSY 0x80 /* busy */ 75 #define WDCS_DRDY 0x40 /* drive ready */ 76 #define WDCS_DWF 0x20 /* drive write fault */ 77 #define WDCS_DSC 0x10 /* drive seek complete */ 78 #define WDCS_DRQ 0x08 /* data request */ 79 #define WDCS_CORR 0x04 /* corrected data */ 80 #define WDCS_IDX 0x02 /* index */ 81 #define WDCS_ERR 0x01 /* error */ 82 #define WDCS_BITS \ 83 "\020\010bsy\007drdy\006dwf\005dsc\004drq\003corr\002idx\001err" 84 85 /* Error bits. */ 86 #define WDCE_BBK 0x80 /* bad block detected */ 87 #define WDCE_CRC 0x80 /* CRC error (Ultra-DMA only) */ 88 #define WDCE_UNC 0x40 /* uncorrectable data error */ 89 #define WDCE_MC 0x20 /* media changed */ 90 #define WDCE_IDNF 0x10 /* id not found */ 91 #define WDCE_MCR 0x08 /* media change requested */ 92 #define WDCE_ABRT 0x04 /* aborted command */ 93 #define WDCE_TK0NF 0x02 /* track 0 not found */ 94 #define WDCE_AMNF 0x01 /* address mark not found */ 95 96 /* Commands for Disk Controller. */ 97 #define WDCC_NOP 0x00 /* Always fail with "aborted command" */ 98 #define WDCC_RECAL 0x10 /* disk restore code -- resets cntlr */ 99 100 #define WDCC_READ 0x20 /* disk read code */ 101 #define WDCC_WRITE 0x30 /* disk write code */ 102 #define WDCC__LONG 0x02 /* modifier -- access ecc bytes */ 103 #define WDCC__NORETRY 0x01 /* modifier -- no retrys */ 104 105 #define WDCC_FORMAT 0x50 /* disk format code */ 106 #define WDCC_DIAGNOSE 0x90 /* controller diagnostic */ 107 #define WDCC_IDP 0x91 /* initialize drive parameters */ 108 109 #define WDCC_SMART 0xb0 /* Self Mon, Analysis, Reporting Tech */ 110 111 #define WDCC_READMULTI 0xc4 /* read multiple */ 112 #define WDCC_WRITEMULTI 0xc5 /* write multiple */ 113 #define WDCC_SETMULTI 0xc6 /* set multiple mode */ 114 115 #define WDCC_READDMA 0xc8 /* read with DMA */ 116 #define WDCC_WRITEDMA 0xca /* write with DMA */ 117 118 #define WDCC_ACKMC 0xdb /* acknowledge media change */ 119 #define WDCC_LOCK 0xde /* lock drawer */ 120 #define WDCC_UNLOCK 0xdf /* unlock drawer */ 121 122 #define WDCC_FLUSHCACHE 0xe7 /* Flush cache */ 123 #define WDCC_FLUSHCACHE_EXT 0xea /* Flush cache ext */ 124 #define WDCC_IDENTIFY 0xec /* read parameters from controller */ 125 #define SET_FEATURES 0xef /* set features */ 126 127 #define WDCC_IDLE 0xe3 /* set idle timer & enter idle mode */ 128 #define WDCC_IDLE_IMMED 0xe1 /* enter idle mode */ 129 #define WDCC_SLEEP 0xe6 /* enter sleep mode */ 130 #define WDCC_STANDBY 0xe2 /* set standby timer & enter standby */ 131 #define WDCC_STANDBY_IMMED 0xe0 /* enter standby mode */ 132 #define WDCC_CHECK_PWR 0xe5 /* check power mode */ 133 134 /* Big Drive support */ 135 #define WDCC_READ_EXT 0x24 /* read 48-bit addressing */ 136 #define WDCC_WRITE_EXT 0x34 /* write 48-bit addressing */ 137 138 #define WDCC_READMULTI_EXT 0x29 /* read multiple 48-bit addressing */ 139 #define WDCC_WRITEMULTI_EXT 0x39 /* write multiple 48-bit addressing */ 140 141 #define WDCC_READDMA_EXT 0x25 /* read 48-bit addressing with DMA */ 142 #define WDCC_WRITEDMA_EXT 0x35 /* write 48-bit addressing with DMA */ 143 144 #ifdef _KERNEL 145 /* Convert a 32-bit command to a 48-bit command. */ 146 static __inline int __unused 147 atacmd_to48(int cmd32) 148 { 149 switch (cmd32) { 150 case WDCC_READ: 151 return WDCC_READ_EXT; 152 case WDCC_WRITE: 153 return WDCC_WRITE_EXT; 154 case WDCC_READMULTI: 155 return WDCC_READMULTI_EXT; 156 case WDCC_WRITEMULTI: 157 return WDCC_WRITEMULTI_EXT; 158 case WDCC_READDMA: 159 return WDCC_READDMA_EXT; 160 case WDCC_WRITEDMA: 161 return WDCC_WRITEDMA_EXT; 162 default: 163 panic("atacmd_to48: illegal 32-bit command: %d", cmd32); 164 /* NOTREACHED */ 165 } 166 } 167 #endif /* _KERNEL */ 168 169 /* Native SATA command queueing */ 170 #define WDCC_READ_FPDMA_QUEUED 0x60 /* SATA native queued read (48bit) */ 171 #define WDCC_WRITE_FPDMA_QUEUED 0x61 /* SATA native queued write (48bit) */ 172 173 #ifdef _KERNEL 174 /* Convert a 32-bit command to a Native SATA Queued command. */ 175 static __inline int __unused 176 atacmd_tostatq(int cmd32) 177 { 178 switch (cmd32) { 179 case WDCC_READDMA: 180 return WDCC_READ_FPDMA_QUEUED; 181 case WDCC_WRITEDMA: 182 return WDCC_WRITE_FPDMA_QUEUED; 183 default: 184 panic("atacmd_tosataq: illegal 32-bit command: %d", cmd32); 185 /* NOTREACHED */ 186 } 187 } 188 #endif /* _KERNEL */ 189 190 /* Subcommands for SET_FEATURES (features register) */ 191 #define WDSF_WRITE_CACHE_EN 0x02 192 #define WDSF_SET_MODE 0x03 193 #define WDSF_REASSIGN_EN 0x04 194 #define WDSF_RETRY_DS 0x33 195 #define WDSF_SET_CACHE_SGMT 0x54 196 #define WDSF_READAHEAD_DS 0x55 197 #define WDSF_POD_DS 0x66 198 #define WDSF_ECC_DS 0x77 199 #define WDSF_WRITE_CACHE_DS 0x82 200 #define WDSF_REASSIGN_DS 0x84 201 #define WDSF_ECC_EN 0x88 202 #define WDSF_RETRY_EN 0x99 203 #define WDSF_SET_CURRENT 0x9a 204 #define WDSF_READAHEAD_EN 0xaa 205 #define WDSF_PREFETCH_SET 0xab 206 #define WDSF_POD_EN 0xcc 207 208 /* Subcommands for SMART (features register) */ 209 #define WDSM_RD_DATA 0xd0 210 #define WDSM_RD_THRESHOLDS 0xd1 211 #define WDSM_ATTR_AUTOSAVE_EN 0xd2 212 #define WDSM_SAVE_ATTR 0xd3 213 #define WDSM_EXEC_OFFL_IMM 0xd4 214 #define WDSM_RD_LOG 0xd5 215 #define WDSM_ENABLE_OPS 0xd8 216 #define WDSM_DISABLE_OPS 0xd9 217 #define WDSM_STATUS 0xda 218 219 #define WDSMART_CYL 0xc24f 220 221 /* parameters uploaded to device/heads register */ 222 #define WDSD_IBM 0xa0 /* forced to 512 byte sector, ecc */ 223 #define WDSD_CHS 0x00 /* cylinder/head/sector addressing */ 224 #define WDSD_LBA 0x40 /* logical block addressing */ 225 226 /* Commands for ATAPI devices */ 227 #define ATAPI_CHECK_POWER_MODE 0xe5 228 #define ATAPI_EXEC_DRIVE_DIAGS 0x90 229 #define ATAPI_IDLE_IMMEDIATE 0xe1 230 #define ATAPI_NOP 0x00 231 #define ATAPI_PKT_CMD 0xa0 232 #define ATAPI_IDENTIFY_DEVICE 0xa1 233 #define ATAPI_SOFT_RESET 0x08 234 #define ATAPI_SLEEP 0xe6 235 #define ATAPI_STANDBY_IMMEDIATE 0xe0 236 237 /* Bytes used by ATAPI_PACKET_COMMAND (feature register) */ 238 #define ATAPI_PKT_CMD_FTRE_DMA 0x01 239 #define ATAPI_PKT_CMD_FTRE_OVL 0x02 240 241 /* ireason */ 242 #define WDCI_CMD 0x01 /* command(1) or data(0) */ 243 #define WDCI_IN 0x02 /* transfer to(1) or from(0) the host */ 244 #define WDCI_RELEASE 0x04 /* bus released until completion */ 245 246 #define PHASE_CMDOUT (WDCS_DRQ | WDCI_CMD) 247 #define PHASE_DATAIN (WDCS_DRQ | WDCI_IN) 248 #define PHASE_DATAOUT (WDCS_DRQ) 249 #define PHASE_COMPLETED (WDCI_IN | WDCI_CMD) 250 #define PHASE_ABORTED (0) 251 252 /* 253 * Drive parameter structure for ATA/ATAPI. 254 * Bit fields: WDC_* : common to ATA/ATAPI 255 * ATA_* : ATA only 256 * ATAPI_* : ATAPI only. 257 */ 258 struct ataparams { 259 /* drive info */ 260 u_int16_t atap_config; /* 0: general configuration */ 261 #define WDC_CFG_ATAPI_MASK 0xc000 262 #define WDC_CFG_ATAPI 0x8000 263 #define ATA_CFG_REMOVABLE 0x0080 264 #define ATA_CFG_FIXED 0x0040 265 #define ATAPI_CFG_TYPE_MASK 0x1f00 266 #define ATAPI_CFG_TYPE(x) (((x) & ATAPI_CFG_TYPE_MASK) >> 8) 267 #define ATAPI_CFG_REMOV 0x0080 268 #define ATAPI_CFG_DRQ_MASK 0x0060 269 #define ATAPI_CFG_STD_DRQ 0x0000 270 #define ATAPI_CFG_IRQ_DRQ 0x0020 271 #define ATAPI_CFG_ACCEL_DRQ 0x0040 272 #define ATAPI_CFG_CMD_MASK 0x0003 273 #define ATAPI_CFG_CMD_12 0x0000 274 #define ATAPI_CFG_CMD_16 0x0001 275 /* words 1-9 are ATA only */ 276 u_int16_t atap_cylinders; /* 1: # of non-removable cylinders */ 277 u_int16_t __reserved1; 278 u_int16_t atap_heads; /* 3: # of heads */ 279 u_int16_t __retired1[2]; /* 4-5: # of unform. bytes/track */ 280 u_int16_t atap_sectors; /* 6: # of sectors */ 281 u_int16_t __retired2[3]; 282 283 u_int8_t atap_serial[20]; /* 10-19: serial number */ 284 u_int16_t __retired3[2]; 285 u_int16_t __obsolete1; 286 u_int8_t atap_revision[8]; /* 23-26: firmware revision */ 287 u_int8_t atap_model[40]; /* 27-46: model number */ 288 u_int16_t atap_multi; /* 47: maximum sectors per irq (ATA) */ 289 u_int16_t __reserved2; 290 u_int16_t atap_capabilities1; /* 49: capability flags */ 291 #define WDC_CAP_IORDY 0x0800 292 #define WDC_CAP_IORDY_DSBL 0x0400 293 #define WDC_CAP_LBA 0x0200 294 #define WDC_CAP_DMA 0x0100 295 #define ATA_CAP_STBY 0x2000 296 #define ATAPI_CAP_INTERL_DMA 0x8000 297 #define ATAPI_CAP_CMD_QUEUE 0x4000 298 #define ATAPI_CAP_OVERLP 0X2000 299 #define ATAPI_CAP_ATA_RST 0x1000 300 u_int16_t atap_capabilities2; /* 50: capability flags (ATA) */ 301 #if BYTE_ORDER == LITTLE_ENDIAN 302 u_int8_t __junk2; 303 u_int8_t atap_oldpiotiming; /* 51: old PIO timing mode */ 304 u_int8_t __junk3; 305 u_int8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */ 306 #else 307 u_int8_t atap_oldpiotiming; /* 51: old PIO timing mode */ 308 u_int8_t __junk2; 309 u_int8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */ 310 u_int8_t __junk3; 311 #endif 312 u_int16_t atap_extensions; /* 53: extensions supported */ 313 #define WDC_EXT_UDMA_MODES 0x0004 314 #define WDC_EXT_MODES 0x0002 315 #define WDC_EXT_GEOM 0x0001 316 /* words 54-62 are ATA only */ 317 u_int16_t atap_curcylinders; /* 54: current logical cylinders */ 318 u_int16_t atap_curheads; /* 55: current logical heads */ 319 u_int16_t atap_cursectors; /* 56: current logical sectors/tracks */ 320 u_int16_t atap_curcapacity[2]; /* 57-58: current capacity */ 321 u_int16_t atap_curmulti; /* 59: current multi-sector setting */ 322 #define WDC_MULTI_VALID 0x0100 323 #define WDC_MULTI_MASK 0x00ff 324 u_int16_t atap_capacity[2]; /* 60-61: total capacity (LBA only) */ 325 u_int16_t __retired4; 326 #if BYTE_ORDER == LITTLE_ENDIAN 327 u_int8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */ 328 u_int8_t atap_dmamode_act; /* multiword DMA mode active */ 329 u_int8_t atap_piomode_supp; /* 64: PIO mode supported */ 330 u_int8_t __junk4; 331 #else 332 u_int8_t atap_dmamode_act; /* multiword DMA mode active */ 333 u_int8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */ 334 u_int8_t __junk4; 335 u_int8_t atap_piomode_supp; /* 64: PIO mode supported */ 336 #endif 337 u_int16_t atap_dmatiming_mimi; /* 65: minimum DMA cycle time */ 338 u_int16_t atap_dmatiming_recom; /* 66: recommended DMA cycle time */ 339 u_int16_t atap_piotiming; /* 67: mini PIO cycle time without FC */ 340 u_int16_t atap_piotiming_iordy; /* 68: mini PIO cycle time with IORDY FC */ 341 u_int16_t __reserved3[2]; 342 /* words 71-72 are ATAPI only */ 343 u_int16_t atap_pkt_br; /* 71: time (ns) to bus release */ 344 u_int16_t atap_pkt_bsyclr; /* 72: tme to clear BSY after service */ 345 u_int16_t __reserved4[2]; 346 u_int16_t atap_queuedepth; /* 75: */ 347 #define WDC_QUEUE_DEPTH_MASK 0x0F 348 u_int16_t atap_sata_caps;/* 76: */ 349 #define SATA_SIGNAL_GEN1 0x02 350 #define SATA_SIGNAL_GEN2 0x04 351 #define SATA_NATIVE_CMDQ 0x0100 352 #define SATA_HOST_PWR_MGMT 0x0200 353 u_int16_t atap_sata_reserved; /* 77: */ 354 u_int16_t atap_sata_features_supp; /* 78: */ 355 #define SATA_NONZERO_OFFSETS 0x02 356 #define SATA_DMA_SETUP_AUTO 0x04 357 #define SATA_DRIVE_PWR_MGMT 0x08 358 u_int16_t atap_sata_features_en; /* 79: */ 359 u_int16_t atap_ata_major; /* 80: Major version number */ 360 #define WDC_VER_ATA1 0x0002 361 #define WDC_VER_ATA2 0x0004 362 #define WDC_VER_ATA3 0x0008 363 #define WDC_VER_ATA4 0x0010 364 #define WDC_VER_ATA5 0x0020 365 #define WDC_VER_ATA6 0x0040 366 #define WDC_VER_ATA7 0x0080 367 u_int16_t atap_ata_minor; /* 81: Minor version number */ 368 u_int16_t atap_cmd_set1; /* 82: command set supported */ 369 #define WDC_CMD1_NOP 0x4000 /* NOP */ 370 #define WDC_CMD1_RB 0x2000 /* READ BUFFER */ 371 #define WDC_CMD1_WB 0x1000 /* WRITE BUFFER */ 372 /* 0x0800 Obsolete */ 373 #define WDC_CMD1_HPA 0x0400 /* Host Protected Area */ 374 #define WDC_CMD1_DVRST 0x0200 /* DEVICE RESET */ 375 #define WDC_CMD1_SRV 0x0100 /* SERVICE */ 376 #define WDC_CMD1_RLSE 0x0080 /* release interrupt */ 377 #define WDC_CMD1_AHEAD 0x0040 /* look-ahead */ 378 #define WDC_CMD1_CACHE 0x0020 /* write cache */ 379 #define WDC_CMD1_PKT 0x0010 /* PACKET */ 380 #define WDC_CMD1_PM 0x0008 /* Power Management */ 381 #define WDC_CMD1_REMOV 0x0004 /* Removable Media */ 382 #define WDC_CMD1_SEC 0x0002 /* Security Mode */ 383 #define WDC_CMD1_SMART 0x0001 /* SMART */ 384 u_int16_t atap_cmd_set2; /* 83: command set supported */ 385 #define ATA_CMD2_FCE 0x2000 /* FLUSH CACHE EXT */ 386 #define WDC_CMD2_FC 0x1000 /* FLUSH CACHE */ 387 #define WDC_CMD2_DCO 0x0800 /* Device Configuration Overlay */ 388 #define ATA_CMD2_LBA48 0x0400 /* 48-bit Address */ 389 #define WDC_CMD2_AAM 0x0200 /* Automatic Acoustic Management */ 390 #define WDC_CMD2_SM 0x0100 /* SET MAX security extension */ 391 #define WDC_CMD2_SFREQ 0x0040 /* SET FEATURE is required 392 to spin-up after power-up */ 393 #define WDC_CMD2_PUIS 0x0020 /* Power-Up In Standby */ 394 #define WDC_CMD2_RMSN 0x0010 /* Removable Media Status Notify */ 395 #define ATA_CMD2_APM 0x0008 /* Advanced Power Management */ 396 #define ATA_CMD2_CFA 0x0004 /* CFA */ 397 #define ATA_CMD2_RWQ 0x0002 /* READ/WRITE DMA QUEUED */ 398 #define WDC_CMD2_DM 0x0001 /* DOWNLOAD MICROCODE */ 399 u_int16_t atap_cmd_ext; /* 84: command/features supp. ext. */ 400 #define ATA_CMDE_TLCONT 0x1000 /* Time-limited R/W Continuous */ 401 #define ATA_CMDE_TL 0x0800 /* Time-limited R/W */ 402 #define ATA_CMDE_URGW 0x0400 /* URG for WRITE STREAM DMA/PIO */ 403 #define ATA_CMDE_URGR 0x0200 /* URG for READ STREAM DMA/PIO */ 404 #define ATA_CMDE_WWN 0x0100 /* World Wide name */ 405 #define ATA_CMDE_WQFE 0x0080 /* WRITE DMA QUEUED FUA EXT */ 406 #define ATA_CMDE_WFE 0x0040 /* WRITE DMA/MULTIPLE FUA EXT */ 407 #define ATA_CMDE_GPL 0x0020 /* General Purpose Logging */ 408 #define ATA_CMDE_STREAM 0x0010 /* Streaming */ 409 #define ATA_CMDE_MCPTC 0x0008 /* Media Card Pass Through Cmd */ 410 #define ATA_CMDE_MS 0x0004 /* Media serial number */ 411 #define ATA_CMDE_SST 0x0002 /* SMART self-test */ 412 #define ATA_CMDE_SEL 0x0001 /* SMART error logging */ 413 u_int16_t atap_cmd1_en; /* 85: cmd/features enabled */ 414 /* bits are the same as atap_cmd_set1 */ 415 u_int16_t atap_cmd2_en; /* 86: cmd/features enabled */ 416 /* bits are the same as atap_cmd_set2 */ 417 u_int16_t atap_cmd_def; /* 87: cmd/features default */ 418 #if BYTE_ORDER == LITTLE_ENDIAN 419 u_int8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */ 420 u_int8_t atap_udmamode_act; /* Ultra-DMA mode active */ 421 #else 422 u_int8_t atap_udmamode_act; /* Ultra-DMA mode active */ 423 u_int8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */ 424 #endif 425 /* 89-92 are ATA-only */ 426 u_int16_t atap_seu_time; /* 89: Sec. Erase Unit compl. time */ 427 u_int16_t atap_eseu_time; /* 90: Enhanced SEU compl. time */ 428 u_int16_t atap_apm_val; /* 91: current APM value */ 429 u_int16_t __reserved6[35]; /* 92-126: reserved */ 430 u_int16_t atap_rmsn_supp; /* 127: remov. media status notif. */ 431 #define WDC_RMSN_SUPP_MASK 0x0003 432 #define WDC_RMSN_SUPP 0x0001 433 u_int16_t atap_sec_st; /* 128: security status */ 434 #define WDC_SEC_LEV_MAX 0x0100 435 #define WDC_SEC_ESE_SUPP 0x0020 436 #define WDC_SEC_EXP 0x0010 437 #define WDC_SEC_FROZEN 0x0008 438 #define WDC_SEC_LOCKED 0x0004 439 #define WDC_SEC_EN 0x0002 440 #define WDC_SEC_SUPP 0x0001 441 }; 442 443 /* 444 * If WDSM_ATTR_ADVISORY, device exceeded intended design life period. 445 * If not WDSM_ATTR_ADVISORY, imminent data loss predicted. 446 */ 447 #define WDSM_ATTR_ADVISORY 1 448 449 /* 450 * If WDSM_ATTR_COLLECTIVE, attribute only updated in off-line testing. 451 * If not WDSM_ATTR_COLLECTIVE, attribute updated also in on-line testing. 452 */ 453 #define WDSM_ATTR_COLLECTIVE 2 454 455 /* 456 * ATA SMART attributes 457 */ 458 459 struct ata_smart_attr { 460 u_int8_t id; /* attribute id number */ 461 u_int16_t flags; 462 u_int8_t value; /* attribute value */ 463 u_int8_t worst; 464 u_int8_t raw[6]; 465 u_int8_t reserved; 466 } __attribute__((packed)); 467 468 struct ata_smart_attributes { 469 u_int16_t data_structure_revision; 470 struct ata_smart_attr attributes[30]; 471 u_int8_t offline_data_collection_status; 472 u_int8_t self_test_exec_status; 473 u_int16_t total_time_to_complete_off_line; 474 u_int8_t vendor_specific_366; 475 u_int8_t offline_data_collection_capability; 476 u_int16_t smart_capability; 477 u_int8_t errorlog_capability; 478 u_int8_t vendor_specific_371; 479 u_int8_t short_test_completion_time; 480 u_int8_t extend_test_completion_time; 481 u_int8_t reserved_374_385[12]; 482 u_int8_t vendor_specific_386_509[125]; 483 int8_t checksum; 484 } __attribute__((packed)); 485 486 struct ata_smart_thresh { 487 u_int8_t id; 488 u_int8_t value; 489 u_int8_t reserved[10]; 490 } __attribute__((packed)); 491 492 struct ata_smart_thresholds { 493 u_int16_t data_structure_revision; 494 struct ata_smart_thresh thresholds[30]; 495 u_int8_t reserved[18]; 496 u_int8_t vendor_specific[131]; 497 int8_t checksum; 498 } __attribute__((packed)); 499 500 struct ata_smart_selftest { 501 u_int8_t number; 502 u_int8_t status; 503 uint16_t time_stamp; 504 u_int8_t failure_check_point; 505 u_int32_t lba_first_error; 506 u_int8_t vendor_specific[15]; 507 } __attribute__((packed)); 508 509 struct ata_smart_selftestlog { 510 u_int16_t data_structure_revision; 511 struct ata_smart_selftest log_entries[21]; 512 u_int8_t vendorspecific[2]; 513 u_int8_t mostrecenttest; 514 u_int8_t reserved[2]; 515 u_int8_t checksum; 516 } __attribute__((packed)); 517 518 #endif /* _DEV_ATA_ATAREG_H_ */ 519
Indexes created Tue Sep 30 11:09:46 GMT 2025