atareg.h revision 1.36
1 /* $NetBSD: atareg.h,v 1.36 2010/01/21 23:26:58 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1991 The Regents of the University of California. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to Berkeley by 32 * William Jolitz. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. Neither the name of the University nor the names of its contributors 43 * may be used to endorse or promote products derived from this software 44 * without specific prior written permission. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 49 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 56 * SUCH DAMAGE. 57 * 58 * @(#)wdreg.h 7.1 (Berkeley) 5/9/91 59 */ 60 61 #ifndef _DEV_ATA_ATAREG_H_ 62 #define _DEV_ATA_ATAREG_H_ 63 64 /* 65 * ATA Task File register definitions. 66 */ 67 68 /* Status bits. */ 69 #define WDCS_BSY 0x80 /* busy */ 70 #define WDCS_DRDY 0x40 /* drive ready */ 71 #define WDCS_DWF 0x20 /* drive write fault */ 72 #define WDCS_DSC 0x10 /* drive seek complete */ 73 #define WDCS_DRQ 0x08 /* data request */ 74 #define WDCS_CORR 0x04 /* corrected data */ 75 #define WDCS_IDX 0x02 /* index */ 76 #define WDCS_ERR 0x01 /* error */ 77 #define WDCS_BITS \ 78 "\020\010bsy\007drdy\006dwf\005dsc\004drq\003corr\002idx\001err" 79 80 /* Error bits. */ 81 #define WDCE_BBK 0x80 /* bad block detected */ 82 #define WDCE_CRC 0x80 /* CRC error (Ultra-DMA only) */ 83 #define WDCE_UNC 0x40 /* uncorrectable data error */ 84 #define WDCE_MC 0x20 /* media changed */ 85 #define WDCE_IDNF 0x10 /* id not found */ 86 #define WDCE_MCR 0x08 /* media change requested */ 87 #define WDCE_ABRT 0x04 /* aborted command */ 88 #define WDCE_TK0NF 0x02 /* track 0 not found */ 89 #define WDCE_AMNF 0x01 /* address mark not found */ 90 91 /* Commands for Disk Controller. */ 92 #define WDCC_NOP 0x00 /* Always fail with "aborted command" */ 93 #define WDCC_RECAL 0x10 /* disk restore code -- resets cntlr */ 94 95 #define WDCC_READ 0x20 /* disk read code */ 96 #define WDCC_WRITE 0x30 /* disk write code */ 97 #define WDCC__LONG 0x02 /* modifier -- access ecc bytes */ 98 #define WDCC__NORETRY 0x01 /* modifier -- no retrys */ 99 100 #define WDCC_FORMAT 0x50 /* disk format code */ 101 #define WDCC_DIAGNOSE 0x90 /* controller diagnostic */ 102 #define WDCC_IDP 0x91 /* initialize drive parameters */ 103 104 #define WDCC_SMART 0xb0 /* Self Mon, Analysis, Reporting Tech */ 105 106 #define WDCC_READMULTI 0xc4 /* read multiple */ 107 #define WDCC_WRITEMULTI 0xc5 /* write multiple */ 108 #define WDCC_SETMULTI 0xc6 /* set multiple mode */ 109 110 #define WDCC_READDMA 0xc8 /* read with DMA */ 111 #define WDCC_WRITEDMA 0xca /* write with DMA */ 112 113 #define WDCC_ACKMC 0xdb /* acknowledge media change */ 114 #define WDCC_LOCK 0xde /* lock drawer */ 115 #define WDCC_UNLOCK 0xdf /* unlock drawer */ 116 117 #define WDCC_FLUSHCACHE 0xe7 /* Flush cache */ 118 #define WDCC_FLUSHCACHE_EXT 0xea /* Flush cache ext */ 119 #define WDCC_IDENTIFY 0xec /* read parameters from controller */ 120 #define SET_FEATURES 0xef /* set features */ 121 122 #define WDCC_IDLE 0xe3 /* set idle timer & enter idle mode */ 123 #define WDCC_IDLE_IMMED 0xe1 /* enter idle mode */ 124 #define WDCC_SLEEP 0xe6 /* enter sleep mode */ 125 #define WDCC_STANDBY 0xe2 /* set standby timer & enter standby */ 126 #define WDCC_STANDBY_IMMED 0xe0 /* enter standby mode */ 127 #define WDCC_CHECK_PWR 0xe5 /* check power mode */ 128 129 #define WDCC_SECURITY_FREEZE 0xf5 /* freeze locking state */ 130 131 /* Big Drive support */ 132 #define WDCC_READ_EXT 0x24 /* read 48-bit addressing */ 133 #define WDCC_WRITE_EXT 0x34 /* write 48-bit addressing */ 134 135 #define WDCC_READMULTI_EXT 0x29 /* read multiple 48-bit addressing */ 136 #define WDCC_WRITEMULTI_EXT 0x39 /* write multiple 48-bit addressing */ 137 138 #define WDCC_READDMA_EXT 0x25 /* read 48-bit addressing with DMA */ 139 #define WDCC_WRITEDMA_EXT 0x35 /* write 48-bit addressing with DMA */ 140 141 #if defined(_KERNEL) || defined(_STANDALONE) 142 #include <dev/ata/ataconf.h> 143 144 /* Convert a 32-bit command to a 48-bit command. */ 145 static __inline int 146 atacmd_to48(int cmd32) 147 { 148 switch (cmd32) { 149 case WDCC_READ: 150 return WDCC_READ_EXT; 151 case WDCC_WRITE: 152 return WDCC_WRITE_EXT; 153 case WDCC_READMULTI: 154 return WDCC_READMULTI_EXT; 155 case WDCC_WRITEMULTI: 156 return WDCC_WRITEMULTI_EXT; 157 #if NATA_DMA 158 case WDCC_READDMA: 159 return WDCC_READDMA_EXT; 160 case WDCC_WRITEDMA: 161 return WDCC_WRITEDMA_EXT; 162 #endif 163 default: 164 panic("atacmd_to48: illegal 32-bit command: %d", cmd32); 165 /* NOTREACHED */ 166 } 167 } 168 #endif /* _KERNEL || _STANDALONE */ 169 170 /* Native SATA command queueing */ 171 #define WDCC_READ_FPDMA_QUEUED 0x60 /* SATA native queued read (48bit) */ 172 #define WDCC_WRITE_FPDMA_QUEUED 0x61 /* SATA native queued write (48bit) */ 173 174 #ifdef _KERNEL 175 /* Convert a 32-bit command to a Native SATA Queued command. */ 176 static __inline int 177 atacmd_tostatq(int cmd32) 178 { 179 switch (cmd32) { 180 case WDCC_READDMA: 181 return WDCC_READ_FPDMA_QUEUED; 182 case WDCC_WRITEDMA: 183 return WDCC_WRITE_FPDMA_QUEUED; 184 default: 185 panic("atacmd_tosataq: illegal 32-bit command: %d", cmd32); 186 /* NOTREACHED */ 187 } 188 } 189 #endif /* _KERNEL */ 190 191 /* Subcommands for SET_FEATURES (features register) */ 192 #define WDSF_8BIT_PIO_EN 0x01 193 #define WDSF_WRITE_CACHE_EN 0x02 194 #define WDSF_SET_MODE 0x03 195 #define WDSF_REASSIGN_EN 0x04 196 #define WDSF_APM_EN 0x05 197 #define WDSF_RETRY_DS 0x33 198 #define WDSF_SET_CACHE_SGMT 0x54 199 #define WDSF_READAHEAD_DS 0x55 200 #define WDSF_POD_DS 0x66 201 #define WDSF_ECC_DS 0x77 202 #define WDSF_WRITE_CACHE_DS 0x82 203 #define WDSF_REASSIGN_DS 0x84 204 #define WDSF_APM_DS 0x85 205 #define WDSF_ECC_EN 0x88 206 #define WDSF_RETRY_EN 0x99 207 #define WDSF_SET_CURRENT 0x9a 208 #define WDSF_READAHEAD_EN 0xaa 209 #define WDSF_PREFETCH_SET 0xab 210 #define WDSF_POD_EN 0xcc 211 212 /* Subcommands for SMART (features register) */ 213 #define WDSM_RD_DATA 0xd0 214 #define WDSM_RD_THRESHOLDS 0xd1 215 #define WDSM_ATTR_AUTOSAVE_EN 0xd2 216 #define WDSM_SAVE_ATTR 0xd3 217 #define WDSM_EXEC_OFFL_IMM 0xd4 218 #define WDSM_RD_LOG 0xd5 219 #define WDSM_ENABLE_OPS 0xd8 220 #define WDSM_DISABLE_OPS 0xd9 221 #define WDSM_STATUS 0xda 222 223 #define WDSMART_CYL 0xc24f 224 225 /* parameters uploaded to device/heads register */ 226 #define WDSD_IBM 0xa0 /* forced to 512 byte sector, ecc */ 227 #define WDSD_CHS 0x00 /* cylinder/head/sector addressing */ 228 #define WDSD_LBA 0x40 /* logical block addressing */ 229 230 /* Commands for ATAPI devices */ 231 #define ATAPI_CHECK_POWER_MODE 0xe5 232 #define ATAPI_EXEC_DRIVE_DIAGS 0x90 233 #define ATAPI_IDLE_IMMEDIATE 0xe1 234 #define ATAPI_NOP 0x00 235 #define ATAPI_PKT_CMD 0xa0 236 #define ATAPI_IDENTIFY_DEVICE 0xa1 237 #define ATAPI_SOFT_RESET 0x08 238 #define ATAPI_SLEEP 0xe6 239 #define ATAPI_STANDBY_IMMEDIATE 0xe0 240 241 /* Bytes used by ATAPI_PACKET_COMMAND (feature register) */ 242 #define ATAPI_PKT_CMD_FTRE_DMA 0x01 243 #define ATAPI_PKT_CMD_FTRE_OVL 0x02 244 245 /* ireason */ 246 #define WDCI_CMD 0x01 /* command(1) or data(0) */ 247 #define WDCI_IN 0x02 /* transfer to(1) or from(0) the host */ 248 #define WDCI_RELEASE 0x04 /* bus released until completion */ 249 250 #define PHASE_CMDOUT (WDCS_DRQ | WDCI_CMD) 251 #define PHASE_DATAIN (WDCS_DRQ | WDCI_IN) 252 #define PHASE_DATAOUT (WDCS_DRQ) 253 #define PHASE_COMPLETED (WDCI_IN | WDCI_CMD) 254 #define PHASE_ABORTED (0) 255 256 /* 257 * Drive parameter structure for ATA/ATAPI. 258 * Bit fields: WDC_* : common to ATA/ATAPI 259 * ATA_* : ATA only 260 * ATAPI_* : ATAPI only. 261 */ 262 struct ataparams { 263 /* drive info */ 264 uint16_t atap_config; /* 0: general configuration */ 265 #define WDC_CFG_ATAPI_MASK 0xc000 266 #define WDC_CFG_ATAPI 0x8000 267 #define ATA_CFG_REMOVABLE 0x0080 268 #define ATA_CFG_FIXED 0x0040 269 #define ATAPI_CFG_TYPE_MASK 0x1f00 270 #define ATAPI_CFG_TYPE(x) (((x) & ATAPI_CFG_TYPE_MASK) >> 8) 271 #define ATAPI_CFG_REMOV 0x0080 272 #define ATAPI_CFG_DRQ_MASK 0x0060 273 #define ATAPI_CFG_STD_DRQ 0x0000 274 #define ATAPI_CFG_IRQ_DRQ 0x0020 275 #define ATAPI_CFG_ACCEL_DRQ 0x0040 276 #define ATAPI_CFG_CMD_MASK 0x0003 277 #define ATAPI_CFG_CMD_12 0x0000 278 #define ATAPI_CFG_CMD_16 0x0001 279 /* words 1-9 are ATA only */ 280 uint16_t atap_cylinders; /* 1: # of non-removable cylinders */ 281 uint16_t __reserved1; 282 uint16_t atap_heads; /* 3: # of heads */ 283 uint16_t __retired1[2]; /* 4-5: # of unform. bytes/track */ 284 uint16_t atap_sectors; /* 6: # of sectors */ 285 uint16_t __retired2[3]; 286 287 uint8_t atap_serial[20]; /* 10-19: serial number */ 288 uint16_t __retired3[2]; 289 uint16_t __obsolete1; 290 uint8_t atap_revision[8]; /* 23-26: firmware revision */ 291 uint8_t atap_model[40]; /* 27-46: model number */ 292 uint16_t atap_multi; /* 47: maximum sectors per irq (ATA) */ 293 uint16_t __reserved2; 294 uint16_t atap_capabilities1; /* 49: capability flags */ 295 #define WDC_CAP_IORDY 0x0800 296 #define WDC_CAP_IORDY_DSBL 0x0400 297 #define WDC_CAP_LBA 0x0200 298 #define WDC_CAP_DMA 0x0100 299 #define ATA_CAP_STBY 0x2000 300 #define ATAPI_CAP_INTERL_DMA 0x8000 301 #define ATAPI_CAP_CMD_QUEUE 0x4000 302 #define ATAPI_CAP_OVERLP 0X2000 303 #define ATAPI_CAP_ATA_RST 0x1000 304 uint16_t atap_capabilities2; /* 50: capability flags (ATA) */ 305 #if BYTE_ORDER == LITTLE_ENDIAN 306 uint8_t __junk2; 307 uint8_t atap_oldpiotiming; /* 51: old PIO timing mode */ 308 uint8_t __junk3; 309 uint8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */ 310 #else 311 uint8_t atap_oldpiotiming; /* 51: old PIO timing mode */ 312 uint8_t __junk2; 313 uint8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */ 314 uint8_t __junk3; 315 #endif 316 uint16_t atap_extensions; /* 53: extensions supported */ 317 #define WDC_EXT_UDMA_MODES 0x0004 318 #define WDC_EXT_MODES 0x0002 319 #define WDC_EXT_GEOM 0x0001 320 /* words 54-62 are ATA only */ 321 uint16_t atap_curcylinders; /* 54: current logical cylinders */ 322 uint16_t atap_curheads; /* 55: current logical heads */ 323 uint16_t atap_cursectors; /* 56: current logical sectors/tracks */ 324 uint16_t atap_curcapacity[2]; /* 57-58: current capacity */ 325 uint16_t atap_curmulti; /* 59: current multi-sector setting */ 326 #define WDC_MULTI_VALID 0x0100 327 #define WDC_MULTI_MASK 0x00ff 328 uint16_t atap_capacity[2]; /* 60-61: total capacity (LBA only) */ 329 uint16_t __retired4; 330 #if BYTE_ORDER == LITTLE_ENDIAN 331 uint8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */ 332 uint8_t atap_dmamode_act; /* multiword DMA mode active */ 333 uint8_t atap_piomode_supp; /* 64: PIO mode supported */ 334 uint8_t __junk4; 335 #else 336 uint8_t atap_dmamode_act; /* multiword DMA mode active */ 337 uint8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */ 338 uint8_t __junk4; 339 uint8_t atap_piomode_supp; /* 64: PIO mode supported */ 340 #endif 341 uint16_t atap_dmatiming_mimi; /* 65: minimum DMA cycle time */ 342 uint16_t atap_dmatiming_recom; /* 66: recommended DMA cycle time */ 343 uint16_t atap_piotiming; /* 67: mini PIO cycle time without FC */ 344 uint16_t atap_piotiming_iordy; /* 68: mini PIO cycle time with IORDY FC */ 345 uint16_t __reserved3[2]; 346 /* words 71-72 are ATAPI only */ 347 uint16_t atap_pkt_br; /* 71: time (ns) to bus release */ 348 uint16_t atap_pkt_bsyclr; /* 72: tme to clear BSY after service */ 349 uint16_t __reserved4[2]; 350 uint16_t atap_queuedepth; /* 75: */ 351 #define WDC_QUEUE_DEPTH_MASK 0x1F 352 uint16_t atap_sata_caps; /* 76: */ 353 #define SATA_SIGNAL_GEN1 0x02 354 #define SATA_SIGNAL_GEN2 0x04 355 #define SATA_NATIVE_CMDQ 0x0100 356 #define SATA_HOST_PWR_MGMT 0x0200 357 #define SATA_PHY_EVNT_CNT 0x0400 358 uint16_t atap_sata_reserved; /* 77: */ 359 uint16_t atap_sata_features_supp; /* 78: */ 360 #define SATA_NONZERO_OFFSETS 0x02 361 #define SATA_DMA_SETUP_AUTO 0x04 362 #define SATA_DRIVE_PWR_MGMT 0x08 363 #define SATA_IN_ORDER_DATA 0x10 364 #define SATA_SW_STTNGS_PRS 0x40 365 uint16_t atap_sata_features_en; /* 79: */ 366 uint16_t atap_ata_major; /* 80: Major version number */ 367 #define WDC_VER_ATA1 0x0002 368 #define WDC_VER_ATA2 0x0004 369 #define WDC_VER_ATA3 0x0008 370 #define WDC_VER_ATA4 0x0010 371 #define WDC_VER_ATA5 0x0020 372 #define WDC_VER_ATA6 0x0040 373 #define WDC_VER_ATA7 0x0080 374 uint16_t atap_ata_minor; /* 81: Minor version number */ 375 uint16_t atap_cmd_set1; /* 82: command set supported */ 376 #define WDC_CMD1_NOP 0x4000 /* NOP */ 377 #define WDC_CMD1_RB 0x2000 /* READ BUFFER */ 378 #define WDC_CMD1_WB 0x1000 /* WRITE BUFFER */ 379 /* 0x0800 Obsolete */ 380 #define WDC_CMD1_HPA 0x0400 /* Host Protected Area */ 381 #define WDC_CMD1_DVRST 0x0200 /* DEVICE RESET */ 382 #define WDC_CMD1_SRV 0x0100 /* SERVICE */ 383 #define WDC_CMD1_RLSE 0x0080 /* release interrupt */ 384 #define WDC_CMD1_AHEAD 0x0040 /* look-ahead */ 385 #define WDC_CMD1_CACHE 0x0020 /* write cache */ 386 #define WDC_CMD1_PKT 0x0010 /* PACKET */ 387 #define WDC_CMD1_PM 0x0008 /* Power Management */ 388 #define WDC_CMD1_REMOV 0x0004 /* Removable Media */ 389 #define WDC_CMD1_SEC 0x0002 /* Security Mode */ 390 #define WDC_CMD1_SMART 0x0001 /* SMART */ 391 uint16_t atap_cmd_set2; /* 83: command set supported */ 392 #define ATA_CMD2_FCE 0x2000 /* FLUSH CACHE EXT */ 393 #define WDC_CMD2_FC 0x1000 /* FLUSH CACHE */ 394 #define WDC_CMD2_DCO 0x0800 /* Device Configuration Overlay */ 395 #define ATA_CMD2_LBA48 0x0400 /* 48-bit Address */ 396 #define WDC_CMD2_AAM 0x0200 /* Automatic Acoustic Management */ 397 #define WDC_CMD2_SM 0x0100 /* SET MAX security extension */ 398 #define WDC_CMD2_SFREQ 0x0040 /* SET FEATURE is required 399 to spin-up after power-up */ 400 #define WDC_CMD2_PUIS 0x0020 /* Power-Up In Standby */ 401 #define WDC_CMD2_RMSN 0x0010 /* Removable Media Status Notify */ 402 #define ATA_CMD2_APM 0x0008 /* Advanced Power Management */ 403 #define ATA_CMD2_CFA 0x0004 /* CFA */ 404 #define ATA_CMD2_RWQ 0x0002 /* READ/WRITE DMA QUEUED */ 405 #define WDC_CMD2_DM 0x0001 /* DOWNLOAD MICROCODE */ 406 uint16_t atap_cmd_ext; /* 84: command/features supp. ext. */ 407 #define ATA_CMDE_TLCONT 0x1000 /* Time-limited R/W Continuous */ 408 #define ATA_CMDE_TL 0x0800 /* Time-limited R/W */ 409 #define ATA_CMDE_URGW 0x0400 /* URG for WRITE STREAM DMA/PIO */ 410 #define ATA_CMDE_URGR 0x0200 /* URG for READ STREAM DMA/PIO */ 411 #define ATA_CMDE_WWN 0x0100 /* World Wide name */ 412 #define ATA_CMDE_WQFE 0x0080 /* WRITE DMA QUEUED FUA EXT */ 413 #define ATA_CMDE_WFE 0x0040 /* WRITE DMA/MULTIPLE FUA EXT */ 414 #define ATA_CMDE_GPL 0x0020 /* General Purpose Logging */ 415 #define ATA_CMDE_STREAM 0x0010 /* Streaming */ 416 #define ATA_CMDE_MCPTC 0x0008 /* Media Card Pass Through Cmd */ 417 #define ATA_CMDE_MS 0x0004 /* Media serial number */ 418 #define ATA_CMDE_SST 0x0002 /* SMART self-test */ 419 #define ATA_CMDE_SEL 0x0001 /* SMART error logging */ 420 uint16_t atap_cmd1_en; /* 85: cmd/features enabled */ 421 /* bits are the same as atap_cmd_set1 */ 422 uint16_t atap_cmd2_en; /* 86: cmd/features enabled */ 423 /* bits are the same as atap_cmd_set2 */ 424 uint16_t atap_cmd_def; /* 87: cmd/features default */ 425 #if BYTE_ORDER == LITTLE_ENDIAN 426 uint8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */ 427 uint8_t atap_udmamode_act; /* Ultra-DMA mode active */ 428 #else 429 uint8_t atap_udmamode_act; /* Ultra-DMA mode active */ 430 uint8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */ 431 #endif 432 /* 89-92 are ATA-only */ 433 uint16_t atap_seu_time; /* 89: Sec. Erase Unit compl. time */ 434 uint16_t atap_eseu_time; /* 90: Enhanced SEU compl. time */ 435 uint16_t atap_apm_val; /* 91: current APM value */ 436 uint16_t __reserved5[8]; /* 92-99: reserved */ 437 uint16_t atap_max_lba[4]; /* 100-103: Max. user LBA addr */ 438 uint16_t __reserved6[4]; /* 104-107: reserved */ 439 uint16_t atap_wwn[4]; /* 108-111: World Wide Name */ 440 uint16_t __reserved7[15]; /* 112-126: reserved */ 441 uint16_t atap_rmsn_supp; /* 127: remov. media status notif. */ 442 #define WDC_RMSN_SUPP_MASK 0x0003 443 #define WDC_RMSN_SUPP 0x0001 444 uint16_t atap_sec_st; /* 128: security status */ 445 #define WDC_SEC_LEV_MAX 0x0100 446 #define WDC_SEC_ESE_SUPP 0x0020 447 #define WDC_SEC_EXP 0x0010 448 #define WDC_SEC_FROZEN 0x0008 449 #define WDC_SEC_LOCKED 0x0004 450 #define WDC_SEC_EN 0x0002 451 #define WDC_SEC_SUPP 0x0001 452 }; 453 454 /* 455 * If WDSM_ATTR_ADVISORY, device exceeded intended design life period. 456 * If not WDSM_ATTR_ADVISORY, imminent data loss predicted. 457 */ 458 #define WDSM_ATTR_ADVISORY 1 459 460 /* 461 * If WDSM_ATTR_COLLECTIVE, attribute only updated in off-line testing. 462 * If not WDSM_ATTR_COLLECTIVE, attribute updated also in on-line testing. 463 */ 464 #define WDSM_ATTR_COLLECTIVE 2 465 466 /* 467 * ATA SMART attributes 468 */ 469 470 struct ata_smart_attr { 471 uint8_t id; /* attribute id number */ 472 uint16_t flags; 473 uint8_t value; /* attribute value */ 474 uint8_t worst; 475 uint8_t raw[6]; 476 uint8_t reserved; 477 } __packed; 478 479 struct ata_smart_attributes { 480 uint16_t data_structure_revision; 481 struct ata_smart_attr attributes[30]; 482 uint8_t offline_data_collection_status; 483 uint8_t self_test_exec_status; 484 uint16_t total_time_to_complete_off_line; 485 uint8_t vendor_specific_366; 486 uint8_t offline_data_collection_capability; 487 uint16_t smart_capability; 488 uint8_t errorlog_capability; 489 uint8_t vendor_specific_371; 490 uint8_t short_test_completion_time; 491 uint8_t extend_test_completion_time; 492 uint8_t reserved_374_385[12]; 493 uint8_t vendor_specific_386_509[125]; 494 int8_t checksum; 495 } __packed; 496 497 struct ata_smart_thresh { 498 uint8_t id; 499 uint8_t value; 500 uint8_t reserved[10]; 501 } __packed; 502 503 struct ata_smart_thresholds { 504 uint16_ data_structure_revision; 505 struct ata_smart_thresh thresholds[30]; 506 uint8_t reserved[18]; 507 uint8_t vendor_specific[131]; 508 int8_t checksum; 509 } __packed; 510 511 struct ata_smart_selftest { 512 uint8_t number; 513 uint8_t status; 514 uint16_t time_stamp; 515 uint8_t failure_check_point; 516 uint32_t lba_first_error; 517 uint8_t vendor_specific[15]; 518 } __packed; 519 520 struct ata_smart_selftestlog { 521 uint16_t data_structure_revision; 522 struct ata_smart_selftest log_entries[21]; 523 uint8_t vendorspecific[2]; 524 uint8_t mostrecenttest; 525 uint8_t reserved[2]; 526 uint8_t checksum; 527 } __packed; 528 529 #endif /* _DEV_ATA_ATAREG_H_ */ 530
Indexes created Tue Sep 30 11:09:46 GMT 2025