atareg.h revision 1.41
1 /* $NetBSD: atareg.h,v 1.41 2012/10/19 17:09:07 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1991 The Regents of the University of California. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to Berkeley by 32 * William Jolitz. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. Neither the name of the University nor the names of its contributors 43 * may be used to endorse or promote products derived from this software 44 * without specific prior written permission. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 49 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 56 * SUCH DAMAGE. 57 * 58 * @(#)wdreg.h 7.1 (Berkeley) 5/9/91 59 */ 60 61 #ifndef _DEV_ATA_ATAREG_H_ 62 #define _DEV_ATA_ATAREG_H_ 63 64 /* 65 * ATA Task File register definitions. 66 */ 67 68 /* Status bits. */ 69 #define WDCS_BSY 0x80 /* busy */ 70 #define WDCS_DRDY 0x40 /* drive ready */ 71 #define WDCS_DWF 0x20 /* drive write fault */ 72 #define WDCS_DSC 0x10 /* drive seek complete */ 73 #define WDCS_DRQ 0x08 /* data request */ 74 #define WDCS_CORR 0x04 /* corrected data */ 75 #define WDCS_IDX 0x02 /* index */ 76 #define WDCS_ERR 0x01 /* error */ 77 #define WDCS_BITS \ 78 "\020\010bsy\007drdy\006dwf\005dsc\004drq\003corr\002idx\001err" 79 80 /* Error bits. */ 81 #define WDCE_BBK 0x80 /* bad block detected */ 82 #define WDCE_CRC 0x80 /* CRC error (Ultra-DMA only) */ 83 #define WDCE_UNC 0x40 /* uncorrectable data error */ 84 #define WDCE_MC 0x20 /* media changed */ 85 #define WDCE_IDNF 0x10 /* id not found */ 86 #define WDCE_MCR 0x08 /* media change requested */ 87 #define WDCE_ABRT 0x04 /* aborted command */ 88 #define WDCE_TK0NF 0x02 /* track 0 not found */ 89 #define WDCE_AMNF 0x01 /* address mark not found */ 90 91 /* Commands for Disk Controller. */ 92 #define WDCC_NOP 0x00 /* Always fail with "aborted command" */ 93 #define ATA_DATA_SET_MANAGEMENT 0x06 94 #define WDCC_RECAL 0x10 /* disk restore code -- resets cntlr */ 95 96 #define WDCC_READ 0x20 /* disk read code */ 97 #define WDCC_WRITE 0x30 /* disk write code */ 98 #define WDCC__LONG 0x02 /* modifier -- access ecc bytes */ 99 #define WDCC__NORETRY 0x01 /* modifier -- no retrys */ 100 101 #define WDCC_FORMAT 0x50 /* disk format code */ 102 #define WDCC_DIAGNOSE 0x90 /* controller diagnostic */ 103 #define WDCC_IDP 0x91 /* initialize drive parameters */ 104 105 #define WDCC_SMART 0xb0 /* Self Mon, Analysis, Reporting Tech */ 106 107 #define WDCC_READMULTI 0xc4 /* read multiple */ 108 #define WDCC_WRITEMULTI 0xc5 /* write multiple */ 109 #define WDCC_SETMULTI 0xc6 /* set multiple mode */ 110 111 #define WDCC_READDMA 0xc8 /* read with DMA */ 112 #define WDCC_WRITEDMA 0xca /* write with DMA */ 113 114 #define WDCC_ACKMC 0xdb /* acknowledge media change */ 115 #define WDCC_LOCK 0xde /* lock drawer */ 116 #define WDCC_UNLOCK 0xdf /* unlock drawer */ 117 118 #define WDCC_FLUSHCACHE 0xe7 /* Flush cache */ 119 #define WDCC_FLUSHCACHE_EXT 0xea /* Flush cache ext */ 120 #define WDCC_IDENTIFY 0xec /* read parameters from controller */ 121 #define SET_FEATURES 0xef /* set features */ 122 123 #define WDCC_IDLE 0xe3 /* set idle timer & enter idle mode */ 124 #define WDCC_IDLE_IMMED 0xe1 /* enter idle mode */ 125 #define WDCC_SLEEP 0xe6 /* enter sleep mode */ 126 #define WDCC_STANDBY 0xe2 /* set standby timer & enter standby */ 127 #define WDCC_STANDBY_IMMED 0xe0 /* enter standby mode */ 128 #define WDCC_CHECK_PWR 0xe5 /* check power mode */ 129 130 #define WDCC_SECURITY_FREEZE 0xf5 /* freeze locking state */ 131 132 /* Big Drive support */ 133 #define WDCC_READ_EXT 0x24 /* read 48-bit addressing */ 134 #define WDCC_WRITE_EXT 0x34 /* write 48-bit addressing */ 135 136 #define WDCC_READMULTI_EXT 0x29 /* read multiple 48-bit addressing */ 137 #define WDCC_WRITEMULTI_EXT 0x39 /* write multiple 48-bit addressing */ 138 139 #define WDCC_READDMA_EXT 0x25 /* read 48-bit addressing with DMA */ 140 #define WDCC_WRITEDMA_EXT 0x35 /* write 48-bit addressing with DMA */ 141 142 #if defined(_KERNEL) || defined(_STANDALONE) 143 #include <dev/ata/ataconf.h> 144 145 /* Convert a 32-bit command to a 48-bit command. */ 146 static __inline int 147 atacmd_to48(int cmd32) 148 { 149 switch (cmd32) { 150 case WDCC_READ: 151 return WDCC_READ_EXT; 152 case WDCC_WRITE: 153 return WDCC_WRITE_EXT; 154 case WDCC_READMULTI: 155 return WDCC_READMULTI_EXT; 156 case WDCC_WRITEMULTI: 157 return WDCC_WRITEMULTI_EXT; 158 #if NATA_DMA 159 case WDCC_READDMA: 160 return WDCC_READDMA_EXT; 161 case WDCC_WRITEDMA: 162 return WDCC_WRITEDMA_EXT; 163 #endif 164 default: 165 panic("atacmd_to48: illegal 32-bit command: %d", cmd32); 166 /* NOTREACHED */ 167 } 168 } 169 #endif /* _KERNEL || _STANDALONE */ 170 171 /* Native SATA command queueing */ 172 #define WDCC_READ_FPDMA_QUEUED 0x60 /* SATA native queued read (48bit) */ 173 #define WDCC_WRITE_FPDMA_QUEUED 0x61 /* SATA native queued write (48bit) */ 174 175 #ifdef _KERNEL 176 /* Convert a 32-bit command to a Native SATA Queued command. */ 177 static __inline int 178 atacmd_tostatq(int cmd32) 179 { 180 switch (cmd32) { 181 case WDCC_READDMA: 182 return WDCC_READ_FPDMA_QUEUED; 183 case WDCC_WRITEDMA: 184 return WDCC_WRITE_FPDMA_QUEUED; 185 default: 186 panic("atacmd_tosataq: illegal 32-bit command: %d", cmd32); 187 /* NOTREACHED */ 188 } 189 } 190 #endif /* _KERNEL */ 191 192 /* Subcommands for SET_FEATURES (features register) */ 193 #define WDSF_8BIT_PIO_EN 0x01 194 #define WDSF_WRITE_CACHE_EN 0x02 195 #define WDSF_SET_MODE 0x03 196 #define WDSF_REASSIGN_EN 0x04 197 #define WDSF_APM_EN 0x05 198 #define WDSF_PUIS_EN 0x06 199 #define WDSF_PUIS_SPIN_UP 0x07 200 #define WDSF_SATA_EN 0x10 201 #define WDSF_RETRY_DS 0x33 202 #define WDSF_AAM_EN 0x42 203 #define WDSF_SET_CACHE_SGMT 0x54 204 #define WDSF_READAHEAD_DS 0x55 205 #define WDSF_POD_DS 0x66 206 #define WDSF_ECC_DS 0x77 207 #define WDSF_WRITE_CACHE_DS 0x82 208 #define WDSF_REASSIGN_DS 0x84 209 #define WDSF_APM_DS 0x85 210 #define WDSF_PUIS_DS 0x86 211 #define WDSF_ECC_EN 0x88 212 #define WDSF_SATA_DS 0x90 213 #define WDSF_RETRY_EN 0x99 214 #define WDSF_SET_CURRENT 0x9a 215 #define WDSF_READAHEAD_EN 0xaa 216 #define WDSF_PREFETCH_SET 0xab 217 #define WDSF_AAM_DS 0xc2 218 #define WDSF_POD_EN 0xcc 219 220 /* Subcommands for WDSF_SATA (count register) */ 221 #define WDSF_SATA_NONZERO_OFFSETS 0x01 222 #define WDSF_SATA_DMA_SETUP_AUTO 0x02 223 #define WDSF_SATA_DRIVE_PWR_MGMT 0x03 224 #define WDSF_SATA_IN_ORDER_DATA 0x04 225 #define WDSF_SATA_ASYNC_NOTIFY 0x05 226 #define WDSF_SATA_SW_STTNGS_PRS 0x06 227 228 /* Subcommands for SMART (features register) */ 229 #define WDSM_RD_DATA 0xd0 230 #define WDSM_RD_THRESHOLDS 0xd1 231 #define WDSM_ATTR_AUTOSAVE_EN 0xd2 232 #define WDSM_SAVE_ATTR 0xd3 233 #define WDSM_EXEC_OFFL_IMM 0xd4 234 #define WDSM_RD_LOG 0xd5 235 #define WDSM_ENABLE_OPS 0xd8 236 #define WDSM_DISABLE_OPS 0xd9 237 #define WDSM_STATUS 0xda 238 239 #define WDSMART_CYL 0xc24f 240 241 /* parameters uploaded to device/heads register */ 242 #define WDSD_IBM 0xa0 /* forced to 512 byte sector, ecc */ 243 #define WDSD_CHS 0x00 /* cylinder/head/sector addressing */ 244 #define WDSD_LBA 0x40 /* logical block addressing */ 245 246 /* Commands for ATAPI devices */ 247 #define ATAPI_CHECK_POWER_MODE 0xe5 248 #define ATAPI_EXEC_DRIVE_DIAGS 0x90 249 #define ATAPI_IDLE_IMMEDIATE 0xe1 250 #define ATAPI_NOP 0x00 251 #define ATAPI_PKT_CMD 0xa0 252 #define ATAPI_IDENTIFY_DEVICE 0xa1 253 #define ATAPI_SOFT_RESET 0x08 254 #define ATAPI_SLEEP 0xe6 255 #define ATAPI_STANDBY_IMMEDIATE 0xe0 256 257 /* Bytes used by ATAPI_PACKET_COMMAND (feature register) */ 258 #define ATAPI_PKT_CMD_FTRE_DMA 0x01 259 #define ATAPI_PKT_CMD_FTRE_OVL 0x02 260 261 /* ireason */ 262 #define WDCI_CMD 0x01 /* command(1) or data(0) */ 263 #define WDCI_IN 0x02 /* transfer to(1) or from(0) the host */ 264 #define WDCI_RELEASE 0x04 /* bus released until completion */ 265 266 #define PHASE_CMDOUT (WDCS_DRQ | WDCI_CMD) 267 #define PHASE_DATAIN (WDCS_DRQ | WDCI_IN) 268 #define PHASE_DATAOUT (WDCS_DRQ) 269 #define PHASE_COMPLETED (WDCI_IN | WDCI_CMD) 270 #define PHASE_ABORTED (0) 271 272 /* 273 * Drive parameter structure for ATA/ATAPI. 274 * Bit fields: WDC_* : common to ATA/ATAPI 275 * ATA_* : ATA only 276 * ATAPI_* : ATAPI only. 277 */ 278 struct ataparams { 279 /* drive info */ 280 uint16_t atap_config; /* 0: general configuration */ 281 #define WDC_CFG_ATAPI_MASK 0xc000 282 #define WDC_CFG_ATAPI 0x8000 283 #define ATA_CFG_REMOVABLE 0x0080 284 #define ATA_CFG_FIXED 0x0040 285 #define ATAPI_CFG_TYPE_MASK 0x1f00 286 #define ATAPI_CFG_TYPE(x) (((x) & ATAPI_CFG_TYPE_MASK) >> 8) 287 #define ATAPI_CFG_REMOV 0x0080 288 #define ATAPI_CFG_DRQ_MASK 0x0060 289 #define ATAPI_CFG_STD_DRQ 0x0000 290 #define ATAPI_CFG_IRQ_DRQ 0x0020 291 #define ATAPI_CFG_ACCEL_DRQ 0x0040 292 #define ATAPI_CFG_CMD_MASK 0x0003 293 #define ATAPI_CFG_CMD_12 0x0000 294 #define ATAPI_CFG_CMD_16 0x0001 295 /* words 1-9 are ATA only */ 296 uint16_t atap_cylinders; /* 1: # of non-removable cylinders */ 297 uint16_t __reserved1; 298 uint16_t atap_heads; /* 3: # of heads */ 299 uint16_t __retired1[2]; /* 4-5: # of unform. bytes/track */ 300 uint16_t atap_sectors; /* 6: # of sectors */ 301 uint16_t __retired2[3]; 302 303 uint8_t atap_serial[20]; /* 10-19: serial number */ 304 uint16_t __retired3[2]; 305 uint16_t __obsolete1; 306 uint8_t atap_revision[8]; /* 23-26: firmware revision */ 307 uint8_t atap_model[40]; /* 27-46: model number */ 308 uint16_t atap_multi; /* 47: maximum sectors per irq (ATA) */ 309 uint16_t __reserved2; 310 uint16_t atap_capabilities1; /* 49: capability flags */ 311 #define WDC_CAP_IORDY 0x0800 312 #define WDC_CAP_IORDY_DSBL 0x0400 313 #define WDC_CAP_LBA 0x0200 314 #define WDC_CAP_DMA 0x0100 315 #define ATA_CAP_STBY 0x2000 316 #define ATAPI_CAP_INTERL_DMA 0x8000 317 #define ATAPI_CAP_CMD_QUEUE 0x4000 318 #define ATAPI_CAP_OVERLP 0X2000 319 #define ATAPI_CAP_ATA_RST 0x1000 320 uint16_t atap_capabilities2; /* 50: capability flags (ATA) */ 321 #if BYTE_ORDER == LITTLE_ENDIAN 322 uint8_t __junk2; 323 uint8_t atap_oldpiotiming; /* 51: old PIO timing mode */ 324 uint8_t __junk3; 325 uint8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */ 326 #else 327 uint8_t atap_oldpiotiming; /* 51: old PIO timing mode */ 328 uint8_t __junk2; 329 uint8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */ 330 uint8_t __junk3; 331 #endif 332 uint16_t atap_extensions; /* 53: extensions supported */ 333 #define WDC_EXT_UDMA_MODES 0x0004 334 #define WDC_EXT_MODES 0x0002 335 #define WDC_EXT_GEOM 0x0001 336 /* words 54-62 are ATA only */ 337 uint16_t atap_curcylinders; /* 54: current logical cylinders */ 338 uint16_t atap_curheads; /* 55: current logical heads */ 339 uint16_t atap_cursectors; /* 56: current logical sectors/tracks */ 340 uint16_t atap_curcapacity[2]; /* 57-58: current capacity */ 341 uint16_t atap_curmulti; /* 59: current multi-sector setting */ 342 #define WDC_MULTI_VALID 0x0100 343 #define WDC_MULTI_MASK 0x00ff 344 uint16_t atap_capacity[2]; /* 60-61: total capacity (LBA only) */ 345 uint16_t __retired4; 346 #if BYTE_ORDER == LITTLE_ENDIAN 347 uint8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */ 348 uint8_t atap_dmamode_act; /* multiword DMA mode active */ 349 uint8_t atap_piomode_supp; /* 64: PIO mode supported */ 350 uint8_t __junk4; 351 #else 352 uint8_t atap_dmamode_act; /* multiword DMA mode active */ 353 uint8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */ 354 uint8_t __junk4; 355 uint8_t atap_piomode_supp; /* 64: PIO mode supported */ 356 #endif 357 uint16_t atap_dmatiming_mimi; /* 65: minimum DMA cycle time */ 358 uint16_t atap_dmatiming_recom; /* 66: recommended DMA cycle time */ 359 uint16_t atap_piotiming; /* 67: mini PIO cycle time without FC */ 360 uint16_t atap_piotiming_iordy; /* 68: mini PIO cycle time with IORDY FC */ 361 uint16_t __reserved3[2]; 362 /* words 71-72 are ATAPI only */ 363 uint16_t atap_pkt_br; /* 71: time (ns) to bus release */ 364 uint16_t atap_pkt_bsyclr; /* 72: tme to clear BSY after service */ 365 uint16_t __reserved4[2]; 366 uint16_t atap_queuedepth; /* 75: */ 367 #define WDC_QUEUE_DEPTH_MASK 0x1F 368 uint16_t atap_sata_caps; /* 76: */ 369 #define SATA_SIGNAL_GEN1 0x02 370 #define SATA_SIGNAL_GEN2 0x04 371 #define SATA_SIGNAL_GEN3 0x08 372 #define SATA_NATIVE_CMDQ 0x0100 373 #define SATA_HOST_PWR_MGMT 0x0200 374 #define SATA_PHY_EVNT_CNT 0x0400 375 uint16_t atap_sata_reserved; /* 77: */ 376 uint16_t atap_sata_features_supp; /* 78: */ 377 #define SATA_NONZERO_OFFSETS 0x02 378 #define SATA_DMA_SETUP_AUTO 0x04 379 #define SATA_DRIVE_PWR_MGMT 0x08 380 #define SATA_IN_ORDER_DATA 0x10 381 #define SATA_SW_STTNGS_PRS 0x40 382 uint16_t atap_sata_features_en; /* 79: */ 383 uint16_t atap_ata_major; /* 80: Major version number */ 384 #define WDC_VER_ATA1 0x0002 385 #define WDC_VER_ATA2 0x0004 386 #define WDC_VER_ATA3 0x0008 387 #define WDC_VER_ATA4 0x0010 388 #define WDC_VER_ATA5 0x0020 389 #define WDC_VER_ATA6 0x0040 390 #define WDC_VER_ATA7 0x0080 391 #define WDC_VER_ATA8 0x0100 392 uint16_t atap_ata_minor; /* 81: Minor version number */ 393 uint16_t atap_cmd_set1; /* 82: command set supported */ 394 #define WDC_CMD1_NOP 0x4000 /* NOP */ 395 #define WDC_CMD1_RB 0x2000 /* READ BUFFER */ 396 #define WDC_CMD1_WB 0x1000 /* WRITE BUFFER */ 397 /* 0x0800 Obsolete */ 398 #define WDC_CMD1_HPA 0x0400 /* Host Protected Area */ 399 #define WDC_CMD1_DVRST 0x0200 /* DEVICE RESET */ 400 #define WDC_CMD1_SRV 0x0100 /* SERVICE */ 401 #define WDC_CMD1_RLSE 0x0080 /* release interrupt */ 402 #define WDC_CMD1_AHEAD 0x0040 /* look-ahead */ 403 #define WDC_CMD1_CACHE 0x0020 /* write cache */ 404 #define WDC_CMD1_PKT 0x0010 /* PACKET */ 405 #define WDC_CMD1_PM 0x0008 /* Power Management */ 406 #define WDC_CMD1_REMOV 0x0004 /* Removable Media */ 407 #define WDC_CMD1_SEC 0x0002 /* Security Mode */ 408 #define WDC_CMD1_SMART 0x0001 /* SMART */ 409 uint16_t atap_cmd_set2; /* 83: command set supported */ 410 #define ATA_CMD2_FCE 0x2000 /* FLUSH CACHE EXT */ 411 #define WDC_CMD2_FC 0x1000 /* FLUSH CACHE */ 412 #define WDC_CMD2_DCO 0x0800 /* Device Configuration Overlay */ 413 #define ATA_CMD2_LBA48 0x0400 /* 48-bit Address */ 414 #define WDC_CMD2_AAM 0x0200 /* Automatic Acoustic Management */ 415 #define WDC_CMD2_SM 0x0100 /* SET MAX security extension */ 416 #define WDC_CMD2_SFREQ 0x0040 /* SET FEATURE is required 417 to spin-up after power-up */ 418 #define WDC_CMD2_PUIS 0x0020 /* Power-Up In Standby */ 419 #define WDC_CMD2_RMSN 0x0010 /* Removable Media Status Notify */ 420 #define ATA_CMD2_APM 0x0008 /* Advanced Power Management */ 421 #define ATA_CMD2_CFA 0x0004 /* CFA */ 422 #define ATA_CMD2_RWQ 0x0002 /* READ/WRITE DMA QUEUED */ 423 #define WDC_CMD2_DM 0x0001 /* DOWNLOAD MICROCODE */ 424 uint16_t atap_cmd_ext; /* 84: command/features supp. ext. */ 425 #define ATA_CMDE_TLCONT 0x1000 /* Time-limited R/W Continuous */ 426 #define ATA_CMDE_TL 0x0800 /* Time-limited R/W */ 427 #define ATA_CMDE_URGW 0x0400 /* URG for WRITE STREAM DMA/PIO */ 428 #define ATA_CMDE_URGR 0x0200 /* URG for READ STREAM DMA/PIO */ 429 #define ATA_CMDE_WWN 0x0100 /* World Wide name */ 430 #define ATA_CMDE_WQFE 0x0080 /* WRITE DMA QUEUED FUA EXT */ 431 #define ATA_CMDE_WFE 0x0040 /* WRITE DMA/MULTIPLE FUA EXT */ 432 #define ATA_CMDE_GPL 0x0020 /* General Purpose Logging */ 433 #define ATA_CMDE_STREAM 0x0010 /* Streaming */ 434 #define ATA_CMDE_MCPTC 0x0008 /* Media Card Pass Through Cmd */ 435 #define ATA_CMDE_MS 0x0004 /* Media serial number */ 436 #define ATA_CMDE_SST 0x0002 /* SMART self-test */ 437 #define ATA_CMDE_SEL 0x0001 /* SMART error logging */ 438 uint16_t atap_cmd1_en; /* 85: cmd/features enabled */ 439 /* bits are the same as atap_cmd_set1 */ 440 uint16_t atap_cmd2_en; /* 86: cmd/features enabled */ 441 /* bits are the same as atap_cmd_set2 */ 442 uint16_t atap_cmd_def; /* 87: cmd/features default */ 443 #if BYTE_ORDER == LITTLE_ENDIAN 444 uint8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */ 445 uint8_t atap_udmamode_act; /* Ultra-DMA mode active */ 446 #else 447 uint8_t atap_udmamode_act; /* Ultra-DMA mode active */ 448 uint8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */ 449 #endif 450 /* 89-92 are ATA-only */ 451 uint16_t atap_seu_time; /* 89: Sec. Erase Unit compl. time */ 452 uint16_t atap_eseu_time; /* 90: Enhanced SEU compl. time */ 453 uint16_t atap_apm_val; /* 91: current APM value */ 454 uint16_t __reserved5[8]; /* 92-99: reserved */ 455 uint16_t atap_max_lba[4]; /* 100-103: Max. user LBA addr */ 456 uint16_t __reserved6; /* 104: reserved */ 457 uint16_t max_dsm_blocks; /* 105: DSM (ATA-8/ACS-2) */ 458 uint16_t atap_secsz; /* 106: physical/logical sector size */ 459 #define ATA_SECSZ_VALID_MASK 0xc000 460 #define ATA_SECSZ_VALID 0x4000 461 #define ATA_SECSZ_LPS 0x2000 /* long physical sectors */ 462 #define ATA_SECSZ_LLS 0x1000 /* long logical sectors */ 463 #define ATA_SECSZ_LPS_SZMSK 0x000f /* 2**N logical per physical */ 464 uint16_t atap_iso7779_isd; /* 107: ISO 7779 inter-seek delay */ 465 uint16_t atap_wwn[4]; /* 108-111: World Wide Name */ 466 uint16_t __reserved7[5]; /* 112-116 */ 467 uint16_t atap_lls_secsz[2]; /* 117-118: long logical sector size */ 468 uint16_t __reserved8[8]; /* 119-126 */ 469 uint16_t atap_rmsn_supp; /* 127: remov. media status notif. */ 470 #define WDC_RMSN_SUPP_MASK 0x0003 471 #define WDC_RMSN_SUPP 0x0001 472 uint16_t atap_sec_st; /* 128: security status */ 473 #define WDC_SEC_LEV_MAX 0x0100 474 #define WDC_SEC_ESE_SUPP 0x0020 475 #define WDC_SEC_EXP 0x0010 476 #define WDC_SEC_FROZEN 0x0008 477 #define WDC_SEC_LOCKED 0x0004 478 #define WDC_SEC_EN 0x0002 479 #define WDC_SEC_SUPP 0x0001 480 uint16_t __reserved9[31]; /* 129-159: vendor specific */ 481 uint16_t atap_cfa_power; /* 160: CFA powermode */ 482 #define ATA_CFA_MAX_MASK 0x0fff 483 #define ATA_CFA_MODE1_DIS 0x1000 /* CFA Mode 1 Disabled */ 484 #define ATA_CFA_MODE1_REQ 0x2000 /* CFA Mode 1 Required */ 485 #define ATA_CFA_WORD160 0x8000 /* Word 160 supported */ 486 uint16_t __reserved10[8]; /* 161-168: reserved for CFA */ 487 uint16_t support_dsm; /* 169: DSM (ATA-8/ACS-2) */ 488 #define ATA_SUPPORT_DSM_TRIM 0x0001 489 uint16_t __reserved10a[6]; /* 170-175: reserved for CFA */ 490 uint8_t atap_media_serial[60]; /* 176-205: media serial number */ 491 uint16_t __reserved11[3]; /* 206-208: */ 492 uint16_t atap_logical_align; /* 209: logical/physical alignment */ 493 #define ATA_LA_VALID_MASK 0xc000 494 #define ATA_LA_VALID 0x4000 495 #define ATA_LA_MASK 0x3fff /* offset of sector LBA 0 in PBA 0 */ 496 uint16_t __reserved12[45]; /* 210-254: */ 497 uint16_t atap_integrity; /* 255: Integrity word */ 498 #define WDC_INTEGRITY_MAGIC_MASK 0x00ff 499 #define WDC_INTEGRITY_MAGIC 0x00a5 500 }; 501 502 /* 503 * If WDSM_ATTR_ADVISORY, device exceeded intended design life period. 504 * If not WDSM_ATTR_ADVISORY, imminent data loss predicted. 505 */ 506 #define WDSM_ATTR_ADVISORY 1 507 508 /* 509 * If WDSM_ATTR_COLLECTIVE, attribute only updated in off-line testing. 510 * If not WDSM_ATTR_COLLECTIVE, attribute updated also in on-line testing. 511 */ 512 #define WDSM_ATTR_COLLECTIVE 2 513 514 /* 515 * ATA SMART attributes 516 */ 517 518 struct ata_smart_attr { 519 uint8_t id; /* attribute id number */ 520 uint16_t flags; 521 uint8_t value; /* attribute value */ 522 uint8_t worst; 523 uint8_t raw[6]; 524 uint8_t reserved; 525 } __packed; 526 527 struct ata_smart_attributes { 528 uint16_t data_structure_revision; 529 struct ata_smart_attr attributes[30]; 530 uint8_t offline_data_collection_status; 531 uint8_t self_test_exec_status; 532 uint16_t total_time_to_complete_off_line; 533 uint8_t vendor_specific_366; 534 uint8_t offline_data_collection_capability; 535 uint16_t smart_capability; 536 uint8_t errorlog_capability; 537 uint8_t vendor_specific_371; 538 uint8_t short_test_completion_time; 539 uint8_t extend_test_completion_time; 540 uint8_t reserved_374_385[12]; 541 uint8_t vendor_specific_386_509[125]; 542 int8_t checksum; 543 } __packed; 544 545 struct ata_smart_thresh { 546 uint8_t id; 547 uint8_t value; 548 uint8_t reserved[10]; 549 } __packed; 550 551 struct ata_smart_thresholds { 552 uint16_t data_structure_revision; 553 struct ata_smart_thresh thresholds[30]; 554 uint8_t reserved[18]; 555 uint8_t vendor_specific[131]; 556 int8_t checksum; 557 } __packed; 558 559 struct ata_smart_selftest { 560 uint8_t number; 561 uint8_t status; 562 uint16_t time_stamp; 563 uint8_t failure_check_point; 564 uint32_t lba_first_error; 565 uint8_t vendor_specific[15]; 566 } __packed; 567 568 struct ata_smart_selftestlog { 569 uint16_t data_structure_revision; 570 struct ata_smart_selftest log_entries[21]; 571 uint8_t vendorspecific[2]; 572 uint8_t mostrecenttest; 573 uint8_t reserved[2]; 574 uint8_t checksum; 575 } __packed; 576 577 #endif /* _DEV_ATA_ATAREG_H_ */ 578
Indexes created Mon Sep 29 21:09:56 GMT 2025