atareg.h revision 1.8.10.1
1 /* $NetBSD: atareg.h,v 1.8.10.1 2004/05/14 06:04:40 jdc Exp $ */ 2 3 /* 4 * Drive parameter structure for ATA/ATAPI. 5 * Bit fields: WDC_* : common to ATA/ATAPI 6 * ATA_* : ATA only 7 * ATAPI_* : ATAPI only. 8 */ 9 struct ataparams { 10 /* drive info */ 11 u_int16_t atap_config; /* 0: general configuration */ 12 #define WDC_CFG_ATAPI_MASK 0xc000 13 #define WDC_CFG_ATAPI 0x8000 14 #define ATA_CFG_REMOVABLE 0x0080 15 #define ATA_CFG_FIXED 0x0040 16 #define ATAPI_CFG_TYPE_MASK 0x1f00 17 #define ATAPI_CFG_TYPE(x) (((x) & ATAPI_CFG_TYPE_MASK) >> 8) 18 #define ATAPI_CFG_REMOV 0x0080 19 #define ATAPI_CFG_DRQ_MASK 0x0060 20 #define ATAPI_CFG_STD_DRQ 0x0000 21 #define ATAPI_CFG_IRQ_DRQ 0x0020 22 #define ATAPI_CFG_ACCEL_DRQ 0x0040 23 #define ATAPI_CFG_CMD_MASK 0x0003 24 #define ATAPI_CFG_CMD_12 0x0000 25 #define ATAPI_CFG_CMD_16 0x0001 26 /* words 1-9 are ATA only */ 27 u_int16_t atap_cylinders; /* 1: # of non-removable cylinders */ 28 u_int16_t __reserved1; 29 u_int16_t atap_heads; /* 3: # of heads */ 30 u_int16_t __retired1[2]; /* 4-5: # of unform. bytes/track */ 31 u_int16_t atap_sectors; /* 6: # of sectors */ 32 u_int16_t __retired2[3]; 33 34 u_int8_t atap_serial[20]; /* 10-19: serial number */ 35 u_int16_t __retired3[2]; 36 u_int16_t __obsolete1; 37 u_int8_t atap_revision[8]; /* 23-26: firmware revision */ 38 u_int8_t atap_model[40]; /* 27-46: model number */ 39 u_int16_t atap_multi; /* 47: maximum sectors per irq (ATA) */ 40 u_int16_t __reserved2; 41 u_int16_t atap_capabilities1; /* 49: capability flags */ 42 #define WDC_CAP_IORDY 0x0800 43 #define WDC_CAP_IORDY_DSBL 0x0400 44 #define WDC_CAP_LBA 0x0200 45 #define WDC_CAP_DMA 0x0100 46 #define ATA_CAP_STBY 0x2000 47 #define ATAPI_CAP_INTERL_DMA 0x8000 48 #define ATAPI_CAP_CMD_QUEUE 0x4000 49 #define ATAPI_CAP_OVERLP 0X2000 50 #define ATAPI_CAP_ATA_RST 0x1000 51 u_int16_t atap_capabilities2; /* 50: capability flags (ATA) */ 52 #if BYTE_ORDER == LITTLE_ENDIAN 53 u_int8_t __junk2; 54 u_int8_t atap_oldpiotiming; /* 51: old PIO timing mode */ 55 u_int8_t __junk3; 56 u_int8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */ 57 #else 58 u_int8_t atap_oldpiotiming; /* 51: old PIO timing mode */ 59 u_int8_t __junk2; 60 u_int8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */ 61 u_int8_t __junk3; 62 #endif 63 u_int16_t atap_extensions; /* 53: extensions supported */ 64 #define WDC_EXT_UDMA_MODES 0x0004 65 #define WDC_EXT_MODES 0x0002 66 #define WDC_EXT_GEOM 0x0001 67 /* words 54-62 are ATA only */ 68 u_int16_t atap_curcylinders; /* 54: current logical cyliners */ 69 u_int16_t atap_curheads; /* 55: current logical heads */ 70 u_int16_t atap_cursectors; /* 56: current logical sectors/tracks */ 71 u_int16_t atap_curcapacity[2]; /* 57-58: current capacity */ 72 u_int16_t atap_curmulti; /* 59: current multi-sector setting */ 73 #define WDC_MULTI_VALID 0x0100 74 #define WDC_MULTI_MASK 0x00ff 75 u_int16_t atap_capacity[2]; /* 60-61: total capacity (LBA only) */ 76 u_int16_t __retired4; 77 #if BYTE_ORDER == LITTLE_ENDIAN 78 u_int8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */ 79 u_int8_t atap_dmamode_act; /* multiword DMA mode active */ 80 u_int8_t atap_piomode_supp; /* 64: PIO mode supported */ 81 u_int8_t __junk4; 82 #else 83 u_int8_t atap_dmamode_act; /* multiword DMA mode active */ 84 u_int8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */ 85 u_int8_t __junk4; 86 u_int8_t atap_piomode_supp; /* 64: PIO mode supported */ 87 #endif 88 u_int16_t atap_dmatiming_mimi; /* 65: minimum DMA cycle time */ 89 u_int16_t atap_dmatiming_recom; /* 66: recomended DMA cycle time */ 90 u_int16_t atap_piotiming; /* 67: mini PIO cycle time without FC */ 91 u_int16_t atap_piotiming_iordy; /* 68: mini PIO cycle time with IORDY FC */ 92 u_int16_t __reserved3[2]; 93 /* words 71-72 are ATAPI only */ 94 u_int16_t atap_pkt_br; /* 71: time (ns) to bus release */ 95 u_int16_t atap_pkt_bsyclr; /* 72: tme to clear BSY after service */ 96 u_int16_t __reserved4[2]; 97 u_int16_t atap_queuedepth; /* 75: */ 98 #define WDC_QUEUE_DEPTH_MASK 0x0F 99 u_int16_t __reserved5[4]; 100 u_int16_t atap_ata_major; /* 80: Major version number */ 101 #define WDC_VER_ATA1 0x0002 102 #define WDC_VER_ATA2 0x0004 103 #define WDC_VER_ATA3 0x0008 104 #define WDC_VER_ATA4 0x0010 105 #define WDC_VER_ATA5 0x0020 106 #define WDC_VER_ATA6 0x0040 107 #define WDC_VER_ATA7 0x0080 108 u_int16_t atap_ata_minor; /* 81: Minor version number */ 109 u_int16_t atap_cmd_set1; /* 82: command set supported */ 110 #define WDC_CMD1_NOP 0x4000 /* NOP */ 111 #define WDC_CMD1_RB 0x2000 /* READ BUFFER */ 112 #define WDC_CMD1_WB 0x1000 /* WRITE BUFFER */ 113 /* 0x0800 Obsolete */ 114 #define WDC_CMD1_HPA 0x0400 /* Host Protected Area */ 115 #define WDC_CMD1_DVRST 0x0200 /* DEVICE RESET */ 116 #define WDC_CMD1_SRV 0x0100 /* SERVICE */ 117 #define WDC_CMD1_RLSE 0x0080 /* release interrupt */ 118 #define WDC_CMD1_AHEAD 0x0040 /* look-ahead */ 119 #define WDC_CMD1_CACHE 0x0020 /* write cache */ 120 #define WDC_CMD1_PKT 0x0010 /* PACKET */ 121 #define WDC_CMD1_PM 0x0008 /* Power Management */ 122 #define WDC_CMD1_REMOV 0x0004 /* Removable Media */ 123 #define WDC_CMD1_SEC 0x0002 /* Security Mode */ 124 #define WDC_CMD1_SMART 0x0001 /* SMART */ 125 u_int16_t atap_cmd_set2; /* 83: command set supported */ 126 #define ATA_CMD2_FCE 0x2000 /* FLUSH CACHE EXT */ 127 #define WDC_CMD2_FC 0x1000 /* FLUSH CACHE */ 128 #define WDC_CMD2_DCO 0x0800 /* Device Configuration Overlay */ 129 #define ATA_CMD2_LBA48 0x0400 /* 48-bit Address */ 130 #define WDC_CMD2_AAM 0x0200 /* Automatic Acoustic Management */ 131 #define WDC_CMD2_SM 0x0100 /* SET MAX security extention */ 132 #define WDC_CMD2_SFREQ 0x0040 /* SET FEATURE is required 133 to spin-up after power-up */ 134 #define WDC_CMD2_PUIS 0x0020 /* Power-Up In Standby */ 135 #define WDC_CMD2_RMSN 0x0010 /* Removable Media Status Notify */ 136 #define ATA_CMD2_APM 0x0008 /* Advanced Power Management */ 137 #define ATA_CMD2_CFA 0x0004 /* CFA */ 138 #define ATA_CMD2_RWQ 0x0002 /* READ/WRITE DMA QUEUED */ 139 #define WDC_CMD2_DM 0x0001 /* DOWNLOAD MICROCODE */ 140 u_int16_t atap_cmd_ext; /* 84: command/features supp. ext. */ 141 #define ATA_CMDE_TLCONT 0x1000 /* Time-limited R/W Continuous */ 142 #define ATA_CMDE_TL 0x0800 /* Time-limited R/W */ 143 #define ATA_CMDE_URGW 0x0400 /* URG for WRITE STREAM DMA/PIO */ 144 #define ATA_CMDE_URGR 0x0200 /* URG for READ STREAM DMA/PIO */ 145 #define ATA_CMDE_WWN 0x0100 /* World Wide name */ 146 #define ATA_CMDE_WQFE 0x0080 /* WRITE DMA QUEUED FUA EXT */ 147 #define ATA_CMDE_WFE 0x0040 /* WRITE DMA/MULTIPLE FUA EXT */ 148 #define ATA_CMDE_GPL 0x0020 /* General Purpose Logging */ 149 #define ATA_CMDE_STREAM 0x0010 /* Streaming */ 150 #define ATA_CMDE_MCPTC 0x0008 /* Media Card Pass Through Cmd */ 151 #define ATA_CMDE_MS 0x0004 /* Media serial number */ 152 #define ATA_CMDE_SST 0x0002 /* SMART self-test */ 153 #define ATA_CMDE_SEL 0x0001 /* SMART error logging */ 154 u_int16_t atap_cmd1_en; /* 85: cmd/features enabled */ 155 /* bits are the same as atap_cmd_set1 */ 156 u_int16_t atap_cmd2_en; /* 86: cmd/features enabled */ 157 #define WDC_CAP_LBA48 (1L << 10) 158 /* bits are the same as atap_cmd_set2 */ 159 u_int16_t atap_cmd_def; /* 87: cmd/features default */ 160 #if BYTE_ORDER == LITTLE_ENDIAN 161 u_int8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */ 162 u_int8_t atap_udmamode_act; /* Ultra-DMA mode active */ 163 #else 164 u_int8_t atap_udmamode_act; /* Ultra-DMA mode active */ 165 u_int8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */ 166 #endif 167 /* 89-92 are ATA-only */ 168 u_int16_t atap_seu_time; /* 89: Sec. Erase Unit compl. time */ 169 u_int16_t atap_eseu_time; /* 90: Enhanced SEU compl. time */ 170 u_int16_t atap_apm_val; /* 91: current APM value */ 171 u_int16_t __reserved6[35]; /* 92-126: reserved */ 172 u_int16_t atap_rmsn_supp; /* 127: remov. media status notif. */ 173 #define WDC_RMSN_SUPP_MASK 0x0003 174 #define WDC_RMSN_SUPP 0x0001 175 u_int16_t atap_sec_st; /* 128: security status */ 176 #define WDC_SEC_LEV_MAX 0x0100 177 #define WDC_SEC_ESE_SUPP 0x0020 178 #define WDC_SEC_EXP 0x0010 179 #define WDC_SEC_FROZEN 0x0008 180 #define WDC_SEC_LOCKED 0x0004 181 #define WDC_SEC_EN 0x0002 182 #define WDC_SEC_SUPP 0x0001 183 }; 184
Indexes created Tue Oct 28 12:10:06 GMT 2025