atavar.h revision 1.13
1 /* $NetBSD: atavar.h,v 1.13 1999/03/10 13:11:43 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 */ 35 36 /* Hight-level functions and structures used by both ATA and ATAPI devices */ 37 38 /* Datas common to drives and controller drivers */ 39 struct ata_drive_datas { 40 u_int8_t drive; /* drive number */ 41 int8_t ata_vers; /* ATA version supported */ 42 u_int16_t drive_flags; /* bitmask for drives present/absent and cap */ 43 #define DRIVE_ATA 0x0001 44 #define DRIVE_ATAPI 0x0002 45 #define DRIVE_OLD 0x0004 46 #define DRIVE (DRIVE_ATA|DRIVE_ATAPI|DRIVE_OLD) 47 #define DRIVE_CAP32 0x0008 48 #define DRIVE_DMA 0x0010 49 #define DRIVE_UDMA 0x0020 50 #define DRIVE_MODE 0x0040 /* the drive reported its mode */ 51 #define DRIVE_RESET 0x0080 /* reset the drive state at next xfer */ 52 #define DRIVE_DMAERR 0x0100 /* Udma transfer had crc error, don't try DMA */ 53 /* 54 * Current setting of drive's PIO, DMA and UDMA modes. 55 * Is initialised by the disks drivers at attach time, and may be 56 * changed later by the controller's code if needed 57 */ 58 u_int8_t PIO_mode; /* Current setting of drive's PIO mode */ 59 u_int8_t DMA_mode; /* Current setting of drive's DMA mode */ 60 u_int8_t UDMA_mode; /* Current setting of drive's UDMA mode */ 61 /* Supported modes for this drive */ 62 u_int8_t PIO_cap; /* supported drive's PIO mode */ 63 u_int8_t DMA_cap; /* supported drive's DMA mode */ 64 u_int8_t UDMA_cap; /* supported drive's UDMA mode */ 65 /* 66 * Drive state. This is drive-type (ATA or ATAPI) dependant 67 * This is reset to 0 after a channel reset. 68 */ 69 u_int8_t state; 70 71 /* Number of DMA errors. Reset to 0 after every successful transfers. */ 72 u_int8_t n_dmaerrs; 73 /* downgrade mode after this many successive errors */ 74 #define NERRS_MAX 2 75 76 struct device *drv_softc; /* ATA drives softc, if any */ 77 void* chnl_softc; /* channel softc */ 78 }; 79 80 /* ATA/ATAPI common attachement datas */ 81 struct ata_atapi_attach { 82 u_int8_t aa_type; /* Type of device */ 83 #define T_ATA 0 84 #define T_ATAPI 1 85 u_int8_t aa_channel; /* controller's channel */ 86 u_int8_t aa_openings; /* Number of simultaneous commands possible */ 87 struct ata_drive_datas *aa_drv_data; 88 void *aa_bus_private; /* infos specifics to this bus */ 89 }; 90 91 /* User config flags that force (or disable) the use of a mode */ 92 #define ATA_CONFIG_PIO_MODES 0x0007 93 #define ATA_CONFIG_PIO_SET 0x0008 94 #define ATA_CONFIG_PIO_OFF 0 95 #define ATA_CONFIG_DMA_MODES 0x0070 96 #define ATA_CONFIG_DMA_SET 0x0080 97 #define ATA_CONFIG_DMA_DISABLE 0x0070 98 #define ATA_CONFIG_DMA_OFF 4 99 #define ATA_CONFIG_UDMA_MODES 0x0700 100 #define ATA_CONFIG_UDMA_SET 0x0800 101 #define ATA_CONFIG_UDMA_DISABLE 0x0700 102 #define ATA_CONFIG_UDMA_OFF 8 103 104 /* 105 * ATA/ATAPI commands description 106 * 107 * This structure defines the interface between the ATA/ATAPI device driver 108 * and the controller for short commands. It contains the command's parameter, 109 * the len of data's to read/write (if any), and a function to call upon 110 * completion. 111 * If no sleep is allowed, the driver can poll for command completion. 112 * Once the command completed, if the error registed is valid, the flag 113 * AT_ERROR is set and the error register value is copied to r_error . 114 * A separate interface is needed for read/write or ATAPI packet commands 115 * (which need multiple interrupts per commands). 116 */ 117 struct wdc_command { 118 u_int8_t r_command; /* Parameters to upload to registers */ 119 u_int8_t r_head; 120 u_int16_t r_cyl; 121 u_int8_t r_sector; 122 u_int8_t r_count; 123 u_int8_t r_precomp; 124 u_int8_t r_st_bmask; /* status register mask to wait for before command */ 125 u_int8_t r_st_pmask; /* status register mask to wait for after command */ 126 u_int8_t r_error; /* error register after command done */ 127 volatile u_int16_t flags; 128 #define AT_READ 0x0001 /* There is data to read */ 129 #define AT_WRITE 0x0002 /* There is data to write (excl. with AT_READ) */ 130 #define AT_WAIT 0x0008 /* wait in controller code for command completion */ 131 #define AT_POLL 0x0010 /* poll for command completion (no interrupts) */ 132 #define AT_DONE 0x0020 /* command is done */ 133 #define AT_ERROR 0x0040 /* command is done with error */ 134 #define AT_TIMEOU 0x0080 /* command timed out */ 135 #define AT_DF 0x0100 /* Drive fault */ 136 #define AT_READREG 0x0200 /* Read registers on completion */ 137 int timeout; /* timeout (in ms) */ 138 void *data; /* Data buffer address */ 139 int bcount; /* number of bytes to transfer */ 140 void (*callback) __P((void*)); /* command to call once command completed */ 141 void *callback_arg; /* argument passed to *callback() */ 142 }; 143 144 int wdc_exec_command __P((struct ata_drive_datas *, struct wdc_command*)); 145 #define WDC_COMPLETE 0x01 146 #define WDC_QUEUED 0x02 147 #define WDC_TRY_AGAIN 0x03 148 149 void wdc_probe_caps __P((struct ata_drive_datas*)); 150 int wdc_downgrade_mode __P((struct ata_drive_datas*)); 151 152 void wdc_reset_channel __P((struct ata_drive_datas *)); 153 154 int wdc_ata_addref __P((struct ata_drive_datas *)); 155 void wdc_ata_delref __P((struct ata_drive_datas *)); 156 157 struct ataparams; 158 int ata_get_params __P((struct ata_drive_datas*, u_int8_t, 159 struct ataparams *)); 160 int ata_set_mode __P((struct ata_drive_datas*, u_int8_t, u_int8_t)); 161 /* return code for these cmds */ 162 #define CMD_OK 0 163 #define CMD_ERR 1 164 #define CMD_AGAIN 2 165 166 void ata_perror __P((struct ata_drive_datas *, int, char *)); 167
Indexes created Mon Sep 29 21:09:56 GMT 2025