atavar.h revision 1.24 1 /* $NetBSD: atavar.h,v 1.24 2002/04/09 21:17:54 bouyer Exp $ */
2
3 /*
4 * Copyright (c) 1998, 2001 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by the University of
17 * California, Berkeley and its contributors.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /* Hight-level functions and structures used by both ATA and ATAPI devices */
36
37 /* Datas common to drives and controller drivers */
38 struct ata_drive_datas {
39 u_int8_t drive; /* drive number */
40 int8_t ata_vers; /* ATA version supported */
41 u_int16_t drive_flags; /* bitmask for drives present/absent and cap */
42 #define DRIVE_ATA 0x0001
43 #define DRIVE_ATAPI 0x0002
44 #define DRIVE_OLD 0x0004
45 #define DRIVE (DRIVE_ATA|DRIVE_ATAPI|DRIVE_OLD)
46 #define DRIVE_CAP32 0x0008
47 #define DRIVE_DMA 0x0010
48 #define DRIVE_UDMA 0x0020
49 #define DRIVE_MODE 0x0040 /* the drive reported its mode */
50 #define DRIVE_RESET 0x0080 /* reset the drive state at next xfer */
51 #define DRIVE_DMAERR 0x0100 /* Udma transfer had crc error, don't try DMA */
52 #define DRIVE_ATAPIST 0x0100 /* device is an ATAPI tape drive */
53 /*
54 * Current setting of drive's PIO, DMA and UDMA modes.
55 * Is initialised by the disks drivers at attach time, and may be
56 * changed later by the controller's code if needed
57 */
58 u_int8_t PIO_mode; /* Current setting of drive's PIO mode */
59 u_int8_t DMA_mode; /* Current setting of drive's DMA mode */
60 u_int8_t UDMA_mode; /* Current setting of drive's UDMA mode */
61 /* Supported modes for this drive */
62 u_int8_t PIO_cap; /* supported drive's PIO mode */
63 u_int8_t DMA_cap; /* supported drive's DMA mode */
64 u_int8_t UDMA_cap; /* supported drive's UDMA mode */
65 /*
66 * Drive state.
67 * This is reset to 0 after a channel reset.
68 */
69 u_int8_t state;
70 #define RESET 0
71 #define RECAL 1
72 #define RECAL_WAIT 2
73 #define PIOMODE 3
74 #define PIOMODE_WAIT 4
75 #define DMAMODE 5
76 #define DMAMODE_WAIT 6
77 #define GEOMETRY 7
78 #define GEOMETRY_WAIT 8
79 #define MULTIMODE 9
80 #define MULTIMODE_WAIT 10
81 #define READY 11
82
83 /* numbers of xfers and DMA errs. Used by ata_dmaerr() */
84 u_int8_t n_dmaerrs;
85 u_int32_t n_xfers;
86 /* Downgrade after NERRS_MAX errors in at most NXFER xfers */
87 #define NERRS_MAX 4
88 #define NXFER 4000
89
90 struct device *drv_softc; /* ATA drives softc, if any */
91 void* chnl_softc; /* channel softc */
92 };
93
94 /* User config flags that force (or disable) the use of a mode */
95 #define ATA_CONFIG_PIO_MODES 0x0007
96 #define ATA_CONFIG_PIO_SET 0x0008
97 #define ATA_CONFIG_PIO_OFF 0
98 #define ATA_CONFIG_DMA_MODES 0x0070
99 #define ATA_CONFIG_DMA_SET 0x0080
100 #define ATA_CONFIG_DMA_DISABLE 0x0070
101 #define ATA_CONFIG_DMA_OFF 4
102 #define ATA_CONFIG_UDMA_MODES 0x0700
103 #define ATA_CONFIG_UDMA_SET 0x0800
104 #define ATA_CONFIG_UDMA_DISABLE 0x0700
105 #define ATA_CONFIG_UDMA_OFF 8
106
107 /*
108 * ATA/ATAPI commands description
109 *
110 * This structure defines the interface between the ATA/ATAPI device driver
111 * and the controller for short commands. It contains the command's parameter,
112 * the len of data's to read/write (if any), and a function to call upon
113 * completion.
114 * If no sleep is allowed, the driver can poll for command completion.
115 * Once the command completed, if the error registed is valid, the flag
116 * AT_ERROR is set and the error register value is copied to r_error .
117 * A separate interface is needed for read/write or ATAPI packet commands
118 * (which need multiple interrupts per commands).
119 */
120 struct wdc_command {
121 u_int8_t r_command; /* Parameters to upload to registers */
122 u_int8_t r_head;
123 u_int16_t r_cyl;
124 u_int8_t r_sector;
125 u_int8_t r_count;
126 u_int8_t r_precomp;
127 u_int8_t r_st_bmask; /* status register mask to wait for before command */
128 u_int8_t r_st_pmask; /* status register mask to wait for after command */
129 u_int8_t r_error; /* error register after command done */
130 volatile u_int16_t flags;
131 #define AT_READ 0x0001 /* There is data to read */
132 #define AT_WRITE 0x0002 /* There is data to write (excl. with AT_READ) */
133 #define AT_WAIT 0x0008 /* wait in controller code for command completion */
134 #define AT_POLL 0x0010 /* poll for command completion (no interrupts) */
135 #define AT_DONE 0x0020 /* command is done */
136 #define AT_XFDONE 0x0040 /* data xfer is done */
137 #define AT_ERROR 0x0080 /* command is done with error */
138 #define AT_TIMEOU 0x0100 /* command timed out */
139 #define AT_DF 0x0200 /* Drive fault */
140 #define AT_READREG 0x0400 /* Read registers on completion */
141 int timeout; /* timeout (in ms) */
142 void *data; /* Data buffer address */
143 int bcount; /* number of bytes to transfer */
144 void (*callback) __P((void*)); /* command to call once command completed */
145 void *callback_arg; /* argument passed to *callback() */
146 };
147
148 int wdc_downgrade_mode __P((struct ata_drive_datas*));
149
150 struct ataparams;
151 int ata_get_params __P((struct ata_drive_datas*, u_int8_t,
152 struct ataparams *));
153 int ata_set_mode __P((struct ata_drive_datas*, u_int8_t, u_int8_t));
154 /* return code for these cmds */
155 #define CMD_OK 0
156 #define CMD_ERR 1
157 #define CMD_AGAIN 2
158
159 void ata_dmaerr __P((struct ata_drive_datas *));
160