atavar.h revision 1.30
1 /* $NetBSD: atavar.h,v 1.30 2003/12/14 02:45:48 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* Hight-level functions and structures used by both ATA and ATAPI devices */ 33 34 /* Datas common to drives and controller drivers */ 35 struct ata_drive_datas { 36 u_int8_t drive; /* drive number */ 37 int8_t ata_vers; /* ATA version supported */ 38 u_int16_t drive_flags; /* bitmask for drives present/absent and cap */ 39 #define DRIVE_ATA 0x0001 40 #define DRIVE_ATAPI 0x0002 41 #define DRIVE_OLD 0x0004 42 #define DRIVE (DRIVE_ATA|DRIVE_ATAPI|DRIVE_OLD) 43 #define DRIVE_CAP32 0x0008 44 #define DRIVE_DMA 0x0010 45 #define DRIVE_UDMA 0x0020 46 #define DRIVE_MODE 0x0040 /* the drive reported its mode */ 47 #define DRIVE_RESET 0x0080 /* reset the drive state at next xfer */ 48 #define DRIVE_DMAERR 0x0100 /* Udma transfer had crc error, don't try DMA */ 49 #define DRIVE_ATAPIST 0x0100 /* device is an ATAPI tape drive */ 50 /* 51 * Current setting of drive's PIO, DMA and UDMA modes. 52 * Is initialised by the disks drivers at attach time, and may be 53 * changed later by the controller's code if needed 54 */ 55 u_int8_t PIO_mode; /* Current setting of drive's PIO mode */ 56 u_int8_t DMA_mode; /* Current setting of drive's DMA mode */ 57 u_int8_t UDMA_mode; /* Current setting of drive's UDMA mode */ 58 /* Supported modes for this drive */ 59 u_int8_t PIO_cap; /* supported drive's PIO mode */ 60 u_int8_t DMA_cap; /* supported drive's DMA mode */ 61 u_int8_t UDMA_cap; /* supported drive's UDMA mode */ 62 /* 63 * Drive state. 64 * This is reset to 0 after a channel reset. 65 */ 66 u_int8_t state; 67 #define RESET 0 68 #define READY 1 69 70 /* numbers of xfers and DMA errs. Used by ata_dmaerr() */ 71 u_int8_t n_dmaerrs; 72 u_int32_t n_xfers; 73 /* Downgrade after NERRS_MAX errors in at most NXFER xfers */ 74 #define NERRS_MAX 4 75 #define NXFER 4000 76 77 struct device *drv_softc; /* ATA drives softc, if any */ 78 void *chnl_softc; /* channel softc */ 79 }; 80 81 /* User config flags that force (or disable) the use of a mode */ 82 #define ATA_CONFIG_PIO_MODES 0x0007 83 #define ATA_CONFIG_PIO_SET 0x0008 84 #define ATA_CONFIG_PIO_OFF 0 85 #define ATA_CONFIG_DMA_MODES 0x0070 86 #define ATA_CONFIG_DMA_SET 0x0080 87 #define ATA_CONFIG_DMA_DISABLE 0x0070 88 #define ATA_CONFIG_DMA_OFF 4 89 #define ATA_CONFIG_UDMA_MODES 0x0700 90 #define ATA_CONFIG_UDMA_SET 0x0800 91 #define ATA_CONFIG_UDMA_DISABLE 0x0700 92 #define ATA_CONFIG_UDMA_OFF 8 93 94 /* 95 * ATA/ATAPI commands description 96 * 97 * This structure defines the interface between the ATA/ATAPI device driver 98 * and the controller for short commands. It contains the command's parameter, 99 * the len of data's to read/write (if any), and a function to call upon 100 * completion. 101 * If no sleep is allowed, the driver can poll for command completion. 102 * Once the command completed, if the error registed is valid, the flag 103 * AT_ERROR is set and the error register value is copied to r_error . 104 * A separate interface is needed for read/write or ATAPI packet commands 105 * (which need multiple interrupts per commands). 106 */ 107 struct wdc_command { 108 u_int8_t r_command; /* Parameters to upload to registers */ 109 u_int8_t r_head; 110 u_int16_t r_cyl; 111 u_int8_t r_sector; 112 u_int8_t r_count; 113 u_int8_t r_precomp; 114 u_int8_t r_st_bmask; /* status register mask to wait for before command */ 115 u_int8_t r_st_pmask; /* status register mask to wait for after command */ 116 u_int8_t r_error; /* error register after command done */ 117 volatile u_int16_t flags; 118 #define AT_READ 0x0001 /* There is data to read */ 119 #define AT_WRITE 0x0002 /* There is data to write (excl. with AT_READ) */ 120 #define AT_WAIT 0x0008 /* wait in controller code for command completion */ 121 #define AT_POLL 0x0010 /* poll for command completion (no interrupts) */ 122 #define AT_DONE 0x0020 /* command is done */ 123 #define AT_XFDONE 0x0040 /* data xfer is done */ 124 #define AT_ERROR 0x0080 /* command is done with error */ 125 #define AT_TIMEOU 0x0100 /* command timed out */ 126 #define AT_DF 0x0200 /* Drive fault */ 127 #define AT_READREG 0x0400 /* Read registers on completion */ 128 int timeout; /* timeout (in ms) */ 129 void *data; /* Data buffer address */ 130 int bcount; /* number of bytes to transfer */ 131 void (*callback) __P((void *)); /* command to call once command completed */ 132 void *callback_arg; /* argument passed to *callback() */ 133 }; 134 135 /* 136 * If WDSM_ATTR_ADVISORY, device exceeded intended design life period. 137 * If not WDSM_ATTR_ADVISORY, imminent data loss predicted. 138 */ 139 #define WDSM_ATTR_ADVISORY 1 140 /* 141 * If WDSM_ATTR_COLLECTIVE, attribute only updated in off-line testing. 142 * If not WDSM_ATTR_COLLECTIVE, attribute updated also in on-line testing. 143 */ 144 #define WDSM_ATTR_COLLECTIVE 2 145 146 struct ata_smart_attr { 147 u_int8_t id; /* attribute id number */ 148 u_int16_t flags; 149 u_int8_t value; /* attribute value */ 150 u_int8_t vendor_specific[8]; 151 } __attribute__((packed)); 152 153 struct ata_smart_attributes { 154 u_int16_t data_structure_revision; 155 struct ata_smart_attr attributes[30]; 156 u_int8_t offline_data_collection_status; 157 u_int8_t self_test_exec_status; 158 u_int16_t total_time_to_complete_off_line; 159 u_int8_t vendor_specific_366; 160 u_int8_t offline_data_collection_capability; 161 u_int16_t smart_capability; 162 u_int8_t errorlog_capability; 163 u_int8_t vendor_specific_371; 164 u_int8_t short_test_completion_time; 165 u_int8_t extend_test_completion_time; 166 u_int8_t reserved_374_385[12]; 167 u_int8_t vendor_specific_386_509[125]; 168 int8_t checksum; 169 } __attribute__((packed)); 170 171 struct ata_smart_thresh { 172 u_int8_t id; 173 u_int8_t value; 174 u_int8_t reserved[10]; 175 } __attribute__((packed)); 176 177 struct ata_smart_thresholds { 178 u_int16_t data_structure_revision; 179 struct ata_smart_thresh thresholds[30]; 180 u_int8_t reserved[18]; 181 u_int8_t vendor_specific[131]; 182 int8_t checksum; 183 } __attribute__((packed)); 184 185 int wdc_downgrade_mode(struct ata_drive_datas *, int); 186 187 struct ataparams; 188 int ata_get_params(struct ata_drive_datas *, u_int8_t, struct ataparams *); 189 int ata_set_mode(struct ata_drive_datas *, u_int8_t, u_int8_t); 190 /* return code for these cmds */ 191 #define CMD_OK 0 192 #define CMD_ERR 1 193 #define CMD_AGAIN 2 194 195 void ata_dmaerr(struct ata_drive_datas *, int); 196
Indexes created Tue Sep 30 11:09:46 GMT 2025