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atavar.h revision 1.49
      1 /*	$NetBSD: atavar.h,v 1.49 2004/08/12 04:57:19 thorpej Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1998, 2001 Manuel Bouyer.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. All advertising materials mentioning features or use of this software
     15  *    must display the following acknowledgement:
     16  *	This product includes software developed by Manuel Bouyer.
     17  * 4. The name of the author may not be used to endorse or promote products
     18  *    derived from this software without specific prior written permission.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #ifndef _DEV_ATA_ATAVAR_H_
     33 #define	_DEV_ATA_ATAVAR_H_
     34 
     35 #include <sys/lock.h>
     36 #include <sys/queue.h>
     37 
     38 /*
     39  * Description of a command to be handled by an ATA controller.  These
     40  * commands are queued in a list.
     41  */
     42 struct ata_xfer {
     43 	__volatile u_int c_flags;	/* command state flags */
     44 
     45 	/* Channel and drive that are to process the request. */
     46 	struct wdc_channel *c_chp;
     47 	int	c_drive;
     48 
     49 	void	*c_cmd;			/* private request structure pointer */
     50 	void	*c_databuf;		/* pointer to data buffer */
     51 	int	c_bcount;		/* byte count left */
     52 	int	c_skip;			/* bytes already transferred */
     53 	int	c_dscpoll;		/* counter for dsc polling (ATAPI) */
     54 
     55 	/* Link on the command queue. */
     56 	TAILQ_ENTRY(ata_xfer) c_xferchain;
     57 
     58 	/* Low-level protocol handlers. */
     59 	void	(*c_start)(struct wdc_channel *, struct ata_xfer *);
     60 	int	(*c_intr)(struct wdc_channel *, struct ata_xfer *, int);
     61 	void	(*c_kill_xfer)(struct wdc_channel *, struct ata_xfer *, int);
     62 };
     63 
     64 /* vlags in c_flags */
     65 #define	C_ATAPI		0x0001		/* xfer is ATAPI request */
     66 #define	C_TIMEOU	0x0002		/* xfer processing timed out */
     67 #define	C_POLL		0x0004		/* command is polled */
     68 #define	C_DMA		0x0008		/* command uses DMA */
     69 
     70 /* reasons for c_kill_xfer() */
     71 #define KILL_GONE 1 /* device is gone */
     72 #define KILL_RESET 2 /* xfer was reset */
     73 
     74 /* Per-channel queue of ata_xfers.  May be shared by multiple channels. */
     75 struct ata_queue {
     76 	TAILQ_HEAD(, ata_xfer) queue_xfer; /* queue of pending commands */
     77 	int queue_freeze; /* freeze count for the queue */
     78 	struct ata_xfer *active_xfer; /* active command */
     79 };
     80 
     81 /* ATA bus instance state information. */
     82 struct atabus_softc {
     83 	struct device sc_dev;
     84 	struct wdc_channel *sc_chan;	/* XXXwdc */
     85 	int sc_flags;
     86 #define ATABUSCF_OPEN	0x01
     87 };
     88 
     89 /*
     90  * A queue of atabus instances, used to ensure the same bus probe order
     91  * for a given hardware configuration at each boot.
     92  */
     93 struct atabus_initq {
     94 	TAILQ_ENTRY(atabus_initq) atabus_initq;
     95 	struct atabus_softc *atabus_sc;
     96 };
     97 
     98 #ifdef _KERNEL
     99 TAILQ_HEAD(atabus_initq_head, atabus_initq);
    100 extern struct atabus_initq_head atabus_initq_head;
    101 extern struct simplelock atabus_interlock;
    102 #endif /* _KERNEL */
    103 
    104 /* High-level functions and structures used by both ATA and ATAPI devices */
    105 struct ataparams;
    106 
    107 /* Datas common to drives and controller drivers */
    108 struct ata_drive_datas {
    109 	u_int8_t drive;		/* drive number */
    110 	int8_t ata_vers;	/* ATA version supported */
    111 	u_int16_t drive_flags;	/* bitmask for drives present/absent and cap */
    112 
    113 #define	DRIVE_ATA	0x0001
    114 #define	DRIVE_ATAPI	0x0002
    115 #define	DRIVE_OLD	0x0004
    116 #define	DRIVE		(DRIVE_ATA|DRIVE_ATAPI|DRIVE_OLD)
    117 #define	DRIVE_CAP32	0x0008
    118 #define	DRIVE_DMA	0x0010
    119 #define	DRIVE_UDMA	0x0020
    120 #define	DRIVE_MODE	0x0040	/* the drive reported its mode */
    121 #define	DRIVE_RESET	0x0080	/* reset the drive state at next xfer */
    122 #define	DRIVE_WAITDRAIN	0x0100	/* device is waiting for the queue to drain */
    123 #define	DRIVE_ATAPIST	0x0200	/* device is an ATAPI tape drive */
    124 #define	DRIVE_NOSTREAM	0x0400	/* no stream methods on this drive */
    125 
    126 	/*
    127 	 * Current setting of drive's PIO, DMA and UDMA modes.
    128 	 * Is initialised by the disks drivers at attach time, and may be
    129 	 * changed later by the controller's code if needed
    130 	 */
    131 	u_int8_t PIO_mode;	/* Current setting of drive's PIO mode */
    132 	u_int8_t DMA_mode;	/* Current setting of drive's DMA mode */
    133 	u_int8_t UDMA_mode;	/* Current setting of drive's UDMA mode */
    134 
    135 	/* Supported modes for this drive */
    136 	u_int8_t PIO_cap;	/* supported drive's PIO mode */
    137 	u_int8_t DMA_cap;	/* supported drive's DMA mode */
    138 	u_int8_t UDMA_cap;	/* supported drive's UDMA mode */
    139 
    140 	/*
    141 	 * Drive state.
    142 	 * This is reset to 0 after a channel reset.
    143 	 */
    144 	u_int8_t state;
    145 
    146 #define RESET          0
    147 #define READY          1
    148 
    149 	/* numbers of xfers and DMA errs. Used by ata_dmaerr() */
    150 	u_int8_t n_dmaerrs;
    151 	u_int32_t n_xfers;
    152 
    153 	/* Downgrade after NERRS_MAX errors in at most NXFER xfers */
    154 #define NERRS_MAX 4
    155 #define NXFER 4000
    156 
    157 	/* Callbacks into the drive's driver. */
    158 	void	(*drv_done)(void *);	/* transfer is done */
    159 
    160 	struct device *drv_softc;	/* ATA drives softc, if any */
    161 	void *chnl_softc;		/* channel softc */
    162 };
    163 
    164 /* User config flags that force (or disable) the use of a mode */
    165 #define ATA_CONFIG_PIO_MODES	0x0007
    166 #define ATA_CONFIG_PIO_SET	0x0008
    167 #define ATA_CONFIG_PIO_OFF	0
    168 #define ATA_CONFIG_DMA_MODES	0x0070
    169 #define ATA_CONFIG_DMA_SET	0x0080
    170 #define ATA_CONFIG_DMA_DISABLE	0x0070
    171 #define ATA_CONFIG_DMA_OFF	4
    172 #define ATA_CONFIG_UDMA_MODES	0x0700
    173 #define ATA_CONFIG_UDMA_SET	0x0800
    174 #define ATA_CONFIG_UDMA_DISABLE	0x0700
    175 #define ATA_CONFIG_UDMA_OFF	8
    176 
    177 /*
    178  * Parameters/state needed by the controller to perform an ATA bio.
    179  */
    180 struct ata_bio {
    181 	volatile u_int16_t flags;/* cmd flags */
    182 #define	ATA_NOSLEEP	0x0001	/* Can't sleep */
    183 #define	ATA_POLL	0x0002	/* poll for completion */
    184 #define	ATA_ITSDONE	0x0004	/* the transfer is as done as it gets */
    185 #define	ATA_SINGLE	0x0008	/* transfer must be done in singlesector mode */
    186 #define	ATA_LBA		0x0010	/* transfer uses LBA addressing */
    187 #define	ATA_READ	0x0020	/* transfer is a read (otherwise a write) */
    188 #define	ATA_CORR	0x0040	/* transfer had a corrected error */
    189 #define	ATA_LBA48	0x0080	/* transfer uses 48-bit LBA addressing */
    190 	int		multi;	/* # of blocks to transfer in multi-mode */
    191 	struct disklabel *lp;	/* pointer to drive's label info */
    192 	daddr_t		blkno;	/* block addr */
    193 	daddr_t		blkdone;/* number of blks transferred */
    194 	daddr_t		nblks;	/* number of block currently transferring */
    195 	int		nbytes;	/* number of bytes currently transferring */
    196 	long		bcount;	/* total number of bytes */
    197 	char		*databuf;/* data buffer address */
    198 	volatile int	error;
    199 #define	NOERROR 	0	/* There was no error (r_error invalid) */
    200 #define	ERROR		1	/* check r_error */
    201 #define	ERR_DF		2	/* Drive fault */
    202 #define	ERR_DMA		3	/* DMA error */
    203 #define	TIMEOUT		4	/* device timed out */
    204 #define	ERR_NODEV	5	/* device has been gone */
    205 #define ERR_RESET	6	/* command was terminated by channel reset */
    206 	u_int8_t	r_error;/* copy of error register */
    207 	daddr_t		badsect[127];/* 126 plus trailing -1 marker */
    208 };
    209 
    210 /*
    211  * ATA/ATAPI commands description
    212  *
    213  * This structure defines the interface between the ATA/ATAPI device driver
    214  * and the controller for short commands. It contains the command's parameter,
    215  * the len of data's to read/write (if any), and a function to call upon
    216  * completion.
    217  * If no sleep is allowed, the driver can poll for command completion.
    218  * Once the command completed, if the error registed is valid, the flag
    219  * AT_ERROR is set and the error register value is copied to r_error .
    220  * A separate interface is needed for read/write or ATAPI packet commands
    221  * (which need multiple interrupts per commands).
    222  */
    223 struct ata_command {
    224 	u_int8_t r_command;	/* Parameters to upload to registers */
    225 	u_int8_t r_head;
    226 	u_int16_t r_cyl;
    227 	u_int8_t r_sector;
    228 	u_int8_t r_count;
    229 	u_int8_t r_features;
    230 	u_int8_t r_st_bmask;	/* status register mask to wait for before
    231 				   command */
    232 	u_int8_t r_st_pmask;	/* status register mask to wait for after
    233 				   command */
    234 	u_int8_t r_error;	/* error register after command done */
    235 	volatile u_int16_t flags;
    236 
    237 #define AT_READ     0x0001 /* There is data to read */
    238 #define AT_WRITE    0x0002 /* There is data to write (excl. with AT_READ) */
    239 #define AT_WAIT     0x0008 /* wait in controller code for command completion */
    240 #define AT_POLL     0x0010 /* poll for command completion (no interrupts) */
    241 #define AT_DONE     0x0020 /* command is done */
    242 #define AT_XFDONE   0x0040 /* data xfer is done */
    243 #define AT_ERROR    0x0080 /* command is done with error */
    244 #define AT_TIMEOU   0x0100 /* command timed out */
    245 #define AT_DF       0x0200 /* Drive fault */
    246 #define AT_RESET    0x0400 /* command terminated by channel reset */
    247 #define AT_GONE     0x0800 /* command terminated because device is gone */
    248 #define AT_READREG  0x1000 /* Read registers on completion */
    249 
    250 	int timeout;		/* timeout (in ms) */
    251 	void *data;		/* Data buffer address */
    252 	int bcount;		/* number of bytes to transfer */
    253 	void (*callback)(void *); /* command to call once command completed */
    254 	void *callback_arg;	/* argument passed to *callback() */
    255 };
    256 
    257 /*
    258  * ata_bustype.  The first field must be compatible with scsipi_bustype,
    259  * as it's used for autoconfig by both ata and atapi drivers.
    260  */
    261 struct ata_bustype {
    262 	int	bustype_type;	/* symbolic name of type */
    263 	int	(*ata_bio)(struct ata_drive_datas *, struct ata_bio *);
    264 	void	(*ata_reset_channel)(struct ata_drive_datas *, int);
    265 /* extra flags for ata_reset_channel(), in addition to AT_* */
    266 #define AT_RST_EMERG 0x10000 /* emergency - e.g. for a dump */
    267 #define	AT_RST_NOCMD 0x20000 /* XXX has to go - temporary until we have tagged queuing */
    268 
    269 	int	(*ata_exec_command)(struct ata_drive_datas *,
    270 				    struct ata_command *);
    271 
    272 #define	WDC_COMPLETE	0x01
    273 #define	WDC_QUEUED	0x02
    274 #define	WDC_TRY_AGAIN	0x03
    275 
    276 	int	(*ata_get_params)(struct ata_drive_datas *, u_int8_t,
    277 				  struct ataparams *);
    278 	int	(*ata_addref)(struct ata_drive_datas *);
    279 	void	(*ata_delref)(struct ata_drive_datas *);
    280 	void	(*ata_killpending)(struct ata_drive_datas *);
    281 };
    282 
    283 /* bustype_type */	/* XXX XXX XXX */
    284 /* #define SCSIPI_BUSTYPE_SCSI	0 */
    285 /* #define SCSIPI_BUSTYPE_ATAPI	1 */
    286 #define	SCSIPI_BUSTYPE_ATA	2
    287 
    288 /*
    289  * Describe an ATA device.  Has to be compatible with scsipi_channel, so
    290  * start with a pointer to ata_bustype.
    291  */
    292 struct ata_device {
    293 	const struct ata_bustype *adev_bustype;
    294 	int adev_channel;
    295 	int adev_openings;
    296 	struct ata_drive_datas *adev_drv_data;
    297 };
    298 
    299 #ifdef _KERNEL
    300 int	atabusprint(void *aux, const char *);
    301 int	ataprint(void *aux, const char *);
    302 
    303 int	wdc_downgrade_mode(struct ata_drive_datas *, int);
    304 
    305 struct ataparams;
    306 int	ata_get_params(struct ata_drive_datas *, u_int8_t, struct ataparams *);
    307 int	ata_set_mode(struct ata_drive_datas *, u_int8_t, u_int8_t);
    308 /* return code for these cmds */
    309 #define CMD_OK    0
    310 #define CMD_ERR   1
    311 #define CMD_AGAIN 2
    312 
    313 void	ata_dmaerr(struct ata_drive_datas *, int);
    314 #endif /* _KERNEL */
    315 
    316 #endif /* _DEV_ATA_ATAVAR_H_ */
    317