if_ni.c revision 1.30 1 /* $NetBSD: if_ni.c,v 1.30 2007/03/08 23:17:56 he Exp $ */
2 /*
3 * Copyright (c) 2000 Ludd, University of Lule}, Sweden. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed at Ludd, University of
16 * Lule}, Sweden and its contributors.
17 * 4. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Driver for DEBNA/DEBNT/DEBNK ethernet cards.
34 * Things that is still to do:
35 * Collect statistics.
36 */
37
38 #include <sys/cdefs.h>
39 __KERNEL_RCSID(0, "$NetBSD: if_ni.c,v 1.30 2007/03/08 23:17:56 he Exp $");
40
41 #include "opt_inet.h"
42 #include "bpfilter.h"
43
44 #include <sys/param.h>
45 #include <sys/mbuf.h>
46 #include <sys/socket.h>
47 #include <sys/device.h>
48 #include <sys/systm.h>
49 #include <sys/sockio.h>
50 #include <sys/sched.h>
51
52 #include <uvm/uvm_extern.h>
53
54 #include <net/if.h>
55 #include <net/if_ether.h>
56 #include <net/if_dl.h>
57
58 #include <netinet/in.h>
59 #include <netinet/if_inarp.h>
60
61 #if NBPFILTER > 0
62 #include <net/bpf.h>
63 #include <net/bpfdesc.h>
64 #endif
65
66 #include <machine/bus.h>
67 #ifdef __vax__
68 #include <machine/mtpr.h>
69 #include <machine/pte.h>
70 #endif
71
72 #include <dev/bi/bireg.h>
73 #include <dev/bi/bivar.h>
74
75 #include "ioconf.h"
76 #include "locators.h"
77
78 /*
79 * Tunable buffer parameters. Good idea to have them as power of 8; then
80 * they will fit into a logical VAX page.
81 */
82 #define NMSGBUF 8 /* Message queue entries */
83 #define NTXBUF 16 /* Transmit queue entries */
84 #define NTXFRAGS 8 /* Number of transmit buffer fragments */
85 #define NRXBUF 24 /* Receive queue entries */
86 #define NBDESCS (NTXBUF * NTXFRAGS + NRXBUF)
87 #define NQUEUES 3 /* RX + TX + MSG */
88 #define PKTHDR 18 /* Length of (control) packet header */
89 #define RXADD 18 /* Additional length of receive datagram */
90 #define TXADD (10+NTXFRAGS*8) /* "" transmit "" */
91 #define MSGADD 134 /* "" message "" */
92
93 #include <dev/bi/if_nireg.h> /* XXX include earlier */
94
95 /*
96 * Macros for (most cases of) insqti/remqhi.
97 * Retry NRETRIES times to do the operation, if it still fails assume
98 * a lost lock and panic.
99 */
100 #define NRETRIES 100
101 #define INSQTI(e, h) ({ \
102 int ret = 0, __i; \
103 for (__i = 0; __i < NRETRIES; __i++) { \
104 if ((ret = insqti(e, h)) != ILCK_FAILED) \
105 break; \
106 } \
107 if (__i == NRETRIES) \
108 panic("ni: insqti failed at %d", __LINE__); \
109 ret; \
110 })
111 #define REMQHI(h) ({ \
112 int __i; void *ret = NULL; \
113 for (__i = 0; __i < NRETRIES; __i++) { \
114 if ((ret = remqhi(h)) != (void *)ILCK_FAILED) \
115 break; \
116 } \
117 if (__i == NRETRIES) \
118 panic("ni: remqhi failed at %d", __LINE__); \
119 ret; \
120 })
121
122
123 #define nipqb (&sc->sc_gvppqb->nc_pqb)
124 #define gvp sc->sc_gvppqb
125 #define fqb sc->sc_fqb
126 #define bbd sc->sc_bbd
127
128 struct ni_softc {
129 struct device sc_dev; /* Configuration common part */
130 struct evcnt sc_intrcnt; /* Interrupt coounting */
131 struct ethercom sc_ec; /* Ethernet common part */
132 #define sc_if sc_ec.ec_if /* network-visible interface */
133 bus_space_tag_t sc_iot;
134 bus_addr_t sc_ioh;
135 bus_dma_tag_t sc_dmat;
136 struct ni_gvppqb *sc_gvppqb; /* Port queue block */
137 struct ni_gvppqb *sc_pgvppqb; /* Phys address of PQB */
138 struct ni_fqb *sc_fqb; /* Free Queue block */
139 struct ni_bbd *sc_bbd; /* Buffer descriptors */
140 u_int8_t sc_enaddr[ETHER_ADDR_LEN];
141 };
142
143 static int nimatch(struct device *, struct cfdata *, void *);
144 static void niattach(struct device *, struct device *, void *);
145 static void niinit(struct ni_softc *);
146 static void nistart(struct ifnet *);
147 static void niintr(void *);
148 static int niioctl(struct ifnet *, u_long, void *);
149 static int ni_add_rxbuf(struct ni_softc *, struct ni_dg *, int);
150 static void ni_setup(struct ni_softc *);
151 static void nitimeout(struct ifnet *);
152 static void ni_shutdown(void *);
153 static void ni_getpgs(struct ni_softc *sc, int size, void **v, paddr_t *p);
154 static int failtest(struct ni_softc *, int, int, int, const char *);
155
156 volatile int endwait, retry; /* Used during autoconfig */
157
158 CFATTACH_DECL(ni, sizeof(struct ni_softc),
159 nimatch, niattach, NULL, NULL);
160
161 #define NI_WREG(csr, val) \
162 bus_space_write_4(sc->sc_iot, sc->sc_ioh, csr, val)
163 #define NI_RREG(csr) \
164 bus_space_read_4(sc->sc_iot, sc->sc_ioh, csr)
165
166 #define WAITREG(csr,val) while (NI_RREG(csr) & val);
167 /*
168 * Check for present device.
169 */
170 int
171 nimatch(parent, cf, aux)
172 struct device *parent;
173 struct cfdata *cf;
174 void *aux;
175 {
176 struct bi_attach_args *ba = aux;
177 u_short type;
178
179 type = bus_space_read_2(ba->ba_iot, ba->ba_ioh, BIREG_DTYPE);
180 if (type != BIDT_DEBNA && type != BIDT_DEBNT && type != BIDT_DEBNK)
181 return 0;
182
183 if (cf->cf_loc[BICF_NODE] != BICF_NODE_DEFAULT &&
184 cf->cf_loc[BICF_NODE] != ba->ba_nodenr)
185 return 0;
186
187 return 1;
188 }
189
190 /*
191 * Allocate a bunch of descriptor-safe memory.
192 * We need to get the structures from the beginning of its own pages.
193 */
194 static void
195 ni_getpgs(struct ni_softc *sc, int size, void **v, paddr_t *p)
196 {
197 bus_dma_segment_t seg;
198 int nsegs, error;
199
200 if ((error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &seg, 1,
201 &nsegs, BUS_DMA_NOWAIT)) != 0)
202 panic(" unable to allocate memory: error %d", error);
203
204 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, nsegs, size, v,
205 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0)
206 panic(" unable to map memory: error %d", error);
207
208 if (p)
209 *p = seg.ds_addr;
210 memset(*v, 0, size);
211 }
212
213 static int
214 failtest(struct ni_softc *sc, int reg, int mask, int test, const char *str)
215 {
216 int i = 100;
217
218 do {
219 DELAY(100000);
220 } while (((NI_RREG(reg) & mask) != test) && --i);
221
222 if (i == 0) {
223 printf("%s: %s\n", sc->sc_dev.dv_xname, str);
224 return 1;
225 }
226 return 0;
227 }
228
229
230 /*
231 * Interface exists: make available by filling in network interface
232 * record. System will initialize the interface when it is ready
233 * to accept packets.
234 */
235 void
236 niattach(parent, self, aux)
237 struct device *parent, *self;
238 void *aux;
239 {
240 struct bi_attach_args *ba = aux;
241 struct ni_softc *sc = (struct ni_softc *)self;
242 struct ifnet *ifp = (struct ifnet *)&sc->sc_if;
243 struct ni_msg *msg;
244 struct ni_ptdb *ptdb;
245 void *va;
246 int i, j, s, res;
247 u_short type;
248
249 type = bus_space_read_2(ba->ba_iot, ba->ba_ioh, BIREG_DTYPE);
250 printf(": DEBN%c\n", type == BIDT_DEBNA ? 'A' : type == BIDT_DEBNT ?
251 'T' : 'K');
252 sc->sc_iot = ba->ba_iot;
253 sc->sc_ioh = ba->ba_ioh;
254 sc->sc_dmat = ba->ba_dmat;
255
256 bi_intr_establish(ba->ba_icookie, ba->ba_ivec,
257 niintr, sc, &sc->sc_intrcnt);
258 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
259 sc->sc_dev.dv_xname, "intr");
260
261 ni_getpgs(sc, sizeof(struct ni_gvppqb), (void **)&sc->sc_gvppqb,
262 (paddr_t *)&sc->sc_pgvppqb);
263 ni_getpgs(sc, sizeof(struct ni_fqb), (void **)&sc->sc_fqb, 0);
264 ni_getpgs(sc, NBDESCS * sizeof(struct ni_bbd),
265 (void **)&sc->sc_bbd, 0);
266 /*
267 * Zero the newly allocated memory.
268 */
269
270 nipqb->np_veclvl = (ba->ba_ivec << 2) + 2;
271 nipqb->np_node = ba->ba_intcpu;
272 nipqb->np_vpqb = (u_int32_t)gvp;
273 #ifdef __vax__
274 nipqb->np_spt = nipqb->np_gpt = mfpr(PR_SBR);
275 nipqb->np_sptlen = nipqb->np_gptlen = mfpr(PR_SLR);
276 #else
277 #error Must fix support for non-vax.
278 #endif
279 nipqb->np_bvplvl = 1;
280 nipqb->np_vfqb = (u_int32_t)fqb;
281 nipqb->np_vbdt = (u_int32_t)bbd;
282 nipqb->np_nbdr = NBDESCS;
283
284 /* Free queue block */
285 nipqb->np_freeq = NQUEUES;
286 fqb->nf_mlen = PKTHDR+MSGADD;
287 fqb->nf_dlen = PKTHDR+TXADD;
288 fqb->nf_rlen = PKTHDR+RXADD;
289
290 strcpy(ifp->if_xname, sc->sc_dev.dv_xname);
291 ifp->if_softc = sc;
292 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
293 ifp->if_start = nistart;
294 ifp->if_ioctl = niioctl;
295 ifp->if_watchdog = nitimeout;
296 IFQ_SET_READY(&ifp->if_snd);
297
298 /*
299 * Start init sequence.
300 */
301
302 /* Reset the node */
303 NI_WREG(BIREG_VAXBICSR, NI_RREG(BIREG_VAXBICSR) | BICSR_NRST);
304 DELAY(500000);
305 i = 20;
306 while ((NI_RREG(BIREG_VAXBICSR) & BICSR_BROKE) && --i)
307 DELAY(500000);
308 if (i == 0) {
309 printf("%s: BROKE bit set after reset\n", sc->sc_dev.dv_xname);
310 return;
311 }
312
313 /* Check state */
314 if (failtest(sc, NI_PSR, PSR_STATE, PSR_UNDEF, "not undefined state"))
315 return;
316
317 /* Clear owner bits */
318 NI_WREG(NI_PSR, NI_RREG(NI_PSR) & ~PSR_OWN);
319 NI_WREG(NI_PCR, NI_RREG(NI_PCR) & ~PCR_OWN);
320
321 /* kick off init */
322 NI_WREG(NI_PCR, (u_int32_t)sc->sc_pgvppqb | PCR_INIT | PCR_OWN);
323 while (NI_RREG(NI_PCR) & PCR_OWN)
324 DELAY(100000);
325
326 /* Check state */
327 if (failtest(sc, NI_PSR, PSR_INITED, PSR_INITED, "failed initialize"))
328 return;
329
330 NI_WREG(NI_PSR, NI_RREG(NI_PSR) & ~PSR_OWN);
331
332 WAITREG(NI_PCR, PCR_OWN);
333 NI_WREG(NI_PCR, PCR_OWN|PCR_ENABLE);
334 WAITREG(NI_PCR, PCR_OWN);
335 WAITREG(NI_PSR, PSR_OWN);
336
337 /* Check state */
338 if (failtest(sc, NI_PSR, PSR_STATE, PSR_ENABLED, "failed enable"))
339 return;
340
341 NI_WREG(NI_PSR, NI_RREG(NI_PSR) & ~PSR_OWN);
342
343 /*
344 * The message queue packets must be located on the beginning
345 * of a page. A VAX page is 512 bytes, but it clusters 8 pages.
346 * This knowledge is used here when allocating pages.
347 * !!! How should this be done on MIPS and Alpha??? !!!
348 */
349 #if NBPG < 4096
350 #error pagesize too small
351 #endif
352 s = splvm();
353 /* Set up message free queue */
354 ni_getpgs(sc, NMSGBUF * 512, &va, 0);
355 for (i = 0; i < NMSGBUF; i++) {
356 msg = (void *)((char *)va + i * 512);
357 res = INSQTI(msg, &fqb->nf_mforw);
358 }
359 WAITREG(NI_PCR, PCR_OWN);
360 NI_WREG(NI_PCR, PCR_FREEQNE|PCR_MFREEQ|PCR_OWN);
361 WAITREG(NI_PCR, PCR_OWN);
362
363 /* Set up xmit queue */
364 ni_getpgs(sc, NTXBUF * 512, &va, 0);
365 for (i = 0; i < NTXBUF; i++) {
366 struct ni_dg *data;
367
368 data = (void *)((char *)va + i * 512);
369 data->nd_status = 0;
370 data->nd_len = TXADD;
371 data->nd_ptdbidx = 1;
372 data->nd_opcode = BVP_DGRAM;
373 for (j = 0; j < NTXFRAGS; j++) {
374 data->bufs[j]._offset = 0;
375 data->bufs[j]._key = 1;
376 bbd[i * NTXFRAGS + j].nb_key = 1;
377 bbd[i * NTXFRAGS + j].nb_status = 0;
378 data->bufs[j]._index = i * NTXFRAGS + j;
379 }
380 res = INSQTI(data, &fqb->nf_dforw);
381 }
382 WAITREG(NI_PCR, PCR_OWN);
383 NI_WREG(NI_PCR, PCR_FREEQNE|PCR_DFREEQ|PCR_OWN);
384 WAITREG(NI_PCR, PCR_OWN);
385
386 /* recv buffers */
387 ni_getpgs(sc, NRXBUF * 512, &va, 0);
388 for (i = 0; i < NRXBUF; i++) {
389 struct ni_dg *data;
390 int idx;
391
392 data = (void *)((char *)va + i * 512);
393 data->nd_len = RXADD;
394 data->nd_opcode = BVP_DGRAMRX;
395 data->nd_ptdbidx = 2;
396 data->bufs[0]._key = 1;
397
398 idx = NTXBUF * NTXFRAGS + i;
399 if (ni_add_rxbuf(sc, data, idx))
400 panic("niattach: ni_add_rxbuf: out of mbufs");
401
402 res = INSQTI(data, &fqb->nf_rforw);
403 }
404 WAITREG(NI_PCR, PCR_OWN);
405 NI_WREG(NI_PCR, PCR_FREEQNE|PCR_RFREEQ|PCR_OWN);
406 WAITREG(NI_PCR, PCR_OWN);
407
408 splx(s);
409
410 /* Set initial parameters */
411 msg = REMQHI(&fqb->nf_mforw);
412
413 msg->nm_opcode = BVP_MSG;
414 msg->nm_status = 0;
415 msg->nm_len = sizeof(struct ni_param) + 6;
416 msg->nm_opcode2 = NI_WPARAM;
417 ((struct ni_param *)&msg->nm_text[0])->np_flags = NP_PAD;
418
419 endwait = retry = 0;
420 res = INSQTI(msg, &gvp->nc_forw0);
421
422 retry: WAITREG(NI_PCR, PCR_OWN);
423 NI_WREG(NI_PCR, PCR_CMDQNE|PCR_CMDQ0|PCR_OWN);
424 WAITREG(NI_PCR, PCR_OWN);
425 i = 1000;
426 while (endwait == 0 && --i)
427 DELAY(10000);
428
429 if (endwait == 0) {
430 if (++retry < 3)
431 goto retry;
432 printf("%s: no response to set params\n", sc->sc_dev.dv_xname);
433 return;
434 }
435
436 /* Clear counters */
437 msg = REMQHI(&fqb->nf_mforw);
438 msg->nm_opcode = BVP_MSG;
439 msg->nm_status = 0;
440 msg->nm_len = sizeof(struct ni_param) + 6;
441 msg->nm_opcode2 = NI_RCCNTR;
442
443 res = INSQTI(msg, &gvp->nc_forw0);
444
445 WAITREG(NI_PCR, PCR_OWN);
446 NI_WREG(NI_PCR, PCR_CMDQNE|PCR_CMDQ0|PCR_OWN);
447 WAITREG(NI_PCR, PCR_OWN);
448
449 /* Enable transmit logic */
450 msg = REMQHI(&fqb->nf_mforw);
451
452 msg->nm_opcode = BVP_MSG;
453 msg->nm_status = 0;
454 msg->nm_len = 18;
455 msg->nm_opcode2 = NI_STPTDB;
456 ptdb = (struct ni_ptdb *)&msg->nm_text[0];
457 memset(ptdb, 0, sizeof(struct ni_ptdb));
458 ptdb->np_index = 1;
459 ptdb->np_fque = 1;
460
461 res = INSQTI(msg, &gvp->nc_forw0);
462
463 WAITREG(NI_PCR, PCR_OWN);
464 NI_WREG(NI_PCR, PCR_CMDQNE|PCR_CMDQ0|PCR_OWN);
465 WAITREG(NI_PCR, PCR_OWN);
466
467 /* Wait for everything to finish */
468 WAITREG(NI_PSR, PSR_OWN);
469
470 printf("%s: hardware address %s\n", sc->sc_dev.dv_xname,
471 ether_sprintf(sc->sc_enaddr));
472
473 /*
474 * Attach the interface.
475 */
476 if_attach(ifp);
477 ether_ifattach(ifp, sc->sc_enaddr);
478 if (shutdownhook_establish(ni_shutdown, sc) == 0)
479 printf("%s: WARNING: unable to establish shutdown hook\n",
480 sc->sc_dev.dv_xname);
481 }
482
483 /*
484 * Initialization of interface.
485 */
486 void
487 niinit(sc)
488 struct ni_softc *sc;
489 {
490 struct ifnet *ifp = (struct ifnet *)&sc->sc_if;
491
492 /*
493 * Set flags (so ni_setup() do the right thing).
494 */
495 ifp->if_flags |= IFF_RUNNING;
496 ifp->if_flags &= ~IFF_OACTIVE;
497
498 /*
499 * Send setup messages so that the rx/tx locic starts.
500 */
501 ni_setup(sc);
502
503 }
504
505 /*
506 * Start output on interface.
507 */
508 void
509 nistart(ifp)
510 struct ifnet *ifp;
511 {
512 struct ni_softc *sc = ifp->if_softc;
513 struct ni_dg *data;
514 struct ni_bbd *bdp;
515 struct mbuf *m, *m0;
516 int i, cnt, res, mlen;
517
518 if (ifp->if_flags & IFF_OACTIVE)
519 return;
520 #ifdef DEBUG
521 if (ifp->if_flags & IFF_DEBUG)
522 printf("%s: nistart\n", sc->sc_dev.dv_xname);
523 #endif
524
525 while (fqb->nf_dforw) {
526 IFQ_POLL(&ifp->if_snd, m);
527 if (m == 0)
528 break;
529
530 data = REMQHI(&fqb->nf_dforw);
531 if ((int)data == Q_EMPTY) {
532 ifp->if_flags |= IFF_OACTIVE;
533 break;
534 }
535
536 IFQ_DEQUEUE(&ifp->if_snd, m);
537
538 /*
539 * Count number of mbufs in chain.
540 * Always do DMA directly from mbufs, therefore the transmit
541 * ring is really big.
542 */
543 for (m0 = m, cnt = 0; m0; m0 = m0->m_next)
544 if (m0->m_len)
545 cnt++;
546 if (cnt > NTXFRAGS)
547 panic("nistart"); /* XXX */
548
549 #if NBPFILTER > 0
550 if (ifp->if_bpf)
551 bpf_mtap(ifp->if_bpf, m);
552 #endif
553 bdp = &bbd[(data->bufs[0]._index & 0x7fff)];
554 for (m0 = m, i = 0, mlen = 0; m0; m0 = m0->m_next) {
555 if (m0->m_len == 0)
556 continue;
557 bdp->nb_status = (mtod(m0, u_int32_t) & NIBD_OFFSET) |
558 NIBD_VALID;
559 bdp->nb_pte = (u_int32_t)kvtopte(mtod(m0, void *));
560 bdp->nb_len = m0->m_len;
561 data->bufs[i]._offset = 0;
562 data->bufs[i]._len = bdp->nb_len;
563 data->bufs[i]._index |= NIDG_CHAIN;
564 mlen += bdp->nb_len;
565 bdp++;
566 i++;
567 }
568 data->nd_opcode = BVP_DGRAM;
569 data->nd_pad3 = 1;
570 data->nd_ptdbidx = 1;
571 data->nd_len = 10 + i * 8;
572 data->bufs[i - 1]._index &= ~NIDG_CHAIN;
573 data->nd_cmdref = (u_int32_t)m;
574 #ifdef DEBUG
575 if (ifp->if_flags & IFF_DEBUG)
576 printf("%s: sending %d bytes (%d segments)\n",
577 sc->sc_dev.dv_xname, mlen, i);
578 #endif
579
580 res = INSQTI(data, &gvp->nc_forw0);
581 if (res == Q_EMPTY) {
582 WAITREG(NI_PCR, PCR_OWN);
583 NI_WREG(NI_PCR, PCR_CMDQNE|PCR_CMDQ0|PCR_OWN);
584 }
585 }
586 }
587
588 void
589 niintr(void *arg)
590 {
591 struct ni_softc *sc = arg;
592 struct ni_dg *data;
593 struct ni_msg *msg;
594 struct ifnet *ifp = &sc->sc_if;
595 struct ni_bbd *bd;
596 struct mbuf *m;
597 int idx, res;
598
599 if ((NI_RREG(NI_PSR) & PSR_STATE) != PSR_ENABLED)
600 return;
601
602 if ((NI_RREG(NI_PSR) & PSR_ERR))
603 printf("%s: PSR %x\n", sc->sc_dev.dv_xname, NI_RREG(NI_PSR));
604
605 KERNEL_LOCK(1, NULL);
606 /* Got any response packets? */
607 while ((NI_RREG(NI_PSR) & PSR_RSQ) && (data = REMQHI(&gvp->nc_forwr))) {
608
609 switch (data->nd_opcode) {
610 case BVP_DGRAMRX: /* Receive datagram */
611 idx = data->bufs[0]._index;
612 bd = &bbd[idx];
613 m = (void *)data->nd_cmdref;
614 m->m_pkthdr.len = m->m_len =
615 data->bufs[0]._len - ETHER_CRC_LEN;
616 m->m_pkthdr.rcvif = ifp;
617 if (ni_add_rxbuf(sc, data, idx)) {
618 bd->nb_len = (m->m_ext.ext_size - 2);
619 bd->nb_pte =
620 (long)kvtopte(m->m_ext.ext_buf);
621 bd->nb_status = 2 | NIBD_VALID;
622 bd->nb_key = 1;
623 }
624 data->nd_len = RXADD;
625 data->nd_status = 0;
626 res = INSQTI(data, &fqb->nf_rforw);
627 if (res == Q_EMPTY) {
628 WAITREG(NI_PCR, PCR_OWN);
629 NI_WREG(NI_PCR, PCR_FREEQNE|PCR_RFREEQ|PCR_OWN);
630 }
631 if (m == (void *)data->nd_cmdref)
632 break; /* Out of mbufs */
633
634 #if NBPFILTER > 0
635 if (ifp->if_bpf)
636 bpf_mtap(ifp->if_bpf, m);
637 #endif
638 (*ifp->if_input)(ifp, m);
639 break;
640
641 case BVP_DGRAM:
642 m = (struct mbuf *)data->nd_cmdref;
643 ifp->if_flags &= ~IFF_OACTIVE;
644 m_freem(m);
645 res = INSQTI(data, &fqb->nf_dforw);
646 if (res == Q_EMPTY) {
647 WAITREG(NI_PCR, PCR_OWN);
648 NI_WREG(NI_PCR, PCR_FREEQNE|PCR_DFREEQ|PCR_OWN);
649 }
650 break;
651
652 case BVP_MSGRX:
653 msg = (struct ni_msg *)data;
654 switch (msg->nm_opcode2) {
655 case NI_WPARAM:
656 memcpy(sc->sc_enaddr, ((struct ni_param *)&msg->nm_text[0])->np_dpa, ETHER_ADDR_LEN);
657 endwait = 1;
658 break;
659
660 case NI_RCCNTR:
661 case NI_CLPTDB:
662 case NI_STPTDB:
663 break;
664
665 default:
666 printf("Unkn resp %d\n",
667 msg->nm_opcode2);
668 break;
669 }
670 res = INSQTI(data, &fqb->nf_mforw);
671 if (res == Q_EMPTY) {
672 WAITREG(NI_PCR, PCR_OWN);
673 NI_WREG(NI_PCR, PCR_FREEQNE|PCR_MFREEQ|PCR_OWN);
674 }
675 break;
676
677 default:
678 printf("Unknown opcode %d\n", data->nd_opcode);
679 res = INSQTI(data, &fqb->nf_mforw);
680 if (res == Q_EMPTY) {
681 WAITREG(NI_PCR, PCR_OWN);
682 NI_WREG(NI_PCR, PCR_FREEQNE|PCR_MFREEQ|PCR_OWN);
683 }
684 }
685 }
686
687 /* Try to kick on the start routine again */
688 nistart(ifp);
689
690 NI_WREG(NI_PSR, NI_RREG(NI_PSR) & ~(PSR_OWN|PSR_RSQ));
691 KERNEL_UNLOCK_ONE(NULL);
692 }
693
694 /*
695 * Process an ioctl request.
696 */
697 int
698 niioctl(ifp, cmd, data)
699 register struct ifnet *ifp;
700 u_long cmd;
701 void *data;
702 {
703 struct ni_softc *sc = ifp->if_softc;
704 struct ifreq *ifr = (struct ifreq *)data;
705 struct ifaddr *ifa = (struct ifaddr *)data;
706 int s = splnet(), error = 0;
707
708 switch (cmd) {
709
710 case SIOCSIFADDR:
711 ifp->if_flags |= IFF_UP;
712 switch(ifa->ifa_addr->sa_family) {
713 #ifdef INET
714 case AF_INET:
715 niinit(sc);
716 arp_ifinit(ifp, ifa);
717 break;
718 #endif
719 }
720 break;
721
722 case SIOCSIFFLAGS:
723 if ((ifp->if_flags & IFF_UP) == 0 &&
724 (ifp->if_flags & IFF_RUNNING) != 0) {
725 /*
726 * If interface is marked down and it is running,
727 * stop it.
728 */
729 ifp->if_flags &= ~IFF_RUNNING;
730 ni_setup(sc);
731 } else if ((ifp->if_flags & IFF_UP) != 0 &&
732 (ifp->if_flags & IFF_RUNNING) == 0) {
733 /*
734 * If interface it marked up and it is stopped, then
735 * start it.
736 */
737 niinit(sc);
738 } else if ((ifp->if_flags & IFF_UP) != 0) {
739 /*
740 * Send a new setup packet to match any new changes.
741 * (Like IFF_PROMISC etc)
742 */
743 ni_setup(sc);
744 }
745 break;
746
747 case SIOCADDMULTI:
748 case SIOCDELMULTI:
749 /*
750 * Update our multicast list.
751 */
752 error = (cmd == SIOCADDMULTI) ?
753 ether_addmulti(ifr, &sc->sc_ec):
754 ether_delmulti(ifr, &sc->sc_ec);
755
756 if (error == ENETRESET) {
757 /*
758 * Multicast list has changed; set the hardware filter
759 * accordingly.
760 */
761 if (ifp->if_flags & IFF_RUNNING)
762 ni_setup(sc);
763 error = 0;
764 }
765 break;
766
767 default:
768 error = EINVAL;
769
770 }
771 splx(s);
772 return (error);
773 }
774
775 /*
776 * Add a receive buffer to the indicated descriptor.
777 */
778 int
779 ni_add_rxbuf(struct ni_softc *sc, struct ni_dg *data, int idx)
780 {
781 struct ni_bbd *bd = &bbd[idx];
782 struct mbuf *m;
783
784 MGETHDR(m, M_DONTWAIT, MT_DATA);
785 if (m == NULL)
786 return (ENOBUFS);
787
788 MCLGET(m, M_DONTWAIT);
789 if ((m->m_flags & M_EXT) == 0) {
790 m_freem(m);
791 return (ENOBUFS);
792 }
793
794 m->m_data += 2;
795 bd->nb_len = (m->m_ext.ext_size - 2);
796 bd->nb_pte = (long)kvtopte(m->m_ext.ext_buf);
797 bd->nb_status = 2 | NIBD_VALID;
798 bd->nb_key = 1;
799
800 data->bufs[0]._offset = 0;
801 data->bufs[0]._len = bd->nb_len;
802 data->bufs[0]._index = idx;
803 data->nd_cmdref = (long)m;
804
805 return (0);
806 }
807
808 /*
809 * Create setup packet and put in queue for sending.
810 */
811 void
812 ni_setup(struct ni_softc *sc)
813 {
814 struct ifnet *ifp = &sc->sc_if;
815 struct ni_msg *msg;
816 struct ni_ptdb *ptdb;
817 struct ether_multi *enm;
818 struct ether_multistep step;
819 int i, res;
820
821 msg = REMQHI(&fqb->nf_mforw);
822 if ((int)msg == Q_EMPTY)
823 return; /* What to do? */
824
825 ptdb = (struct ni_ptdb *)&msg->nm_text[0];
826 memset(ptdb, 0, sizeof(struct ni_ptdb));
827
828 msg->nm_opcode = BVP_MSG;
829 msg->nm_len = 18;
830 ptdb->np_index = 2; /* definition type index */
831 ptdb->np_fque = 2; /* Free queue */
832 if (ifp->if_flags & IFF_RUNNING) {
833 msg->nm_opcode2 = NI_STPTDB;
834 ptdb->np_type = ETHERTYPE_IP;
835 ptdb->np_flags = PTDB_UNKN|PTDB_BDC;
836 if (ifp->if_flags & IFF_PROMISC)
837 ptdb->np_flags |= PTDB_PROMISC;
838 memset(ptdb->np_mcast[0], 0xff, ETHER_ADDR_LEN); /* Broadcast */
839 ptdb->np_adrlen = 1;
840 msg->nm_len += 8;
841 ifp->if_flags &= ~IFF_ALLMULTI;
842 if ((ifp->if_flags & IFF_PROMISC) == 0) {
843 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm);
844 i = 1;
845 while (enm != NULL) {
846 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6)) {
847 ifp->if_flags |= IFF_ALLMULTI;
848 ptdb->np_flags |= PTDB_AMC;
849 break;
850 }
851 msg->nm_len += 8;
852 ptdb->np_adrlen++;
853 memcpy(ptdb->np_mcast[i++], enm->enm_addrlo,
854 ETHER_ADDR_LEN);
855 ETHER_NEXT_MULTI(step, enm);
856 }
857 }
858 } else
859 msg->nm_opcode2 = NI_CLPTDB;
860
861 res = INSQTI(msg, &gvp->nc_forw0);
862 if (res == Q_EMPTY) {
863 WAITREG(NI_PCR, PCR_OWN);
864 NI_WREG(NI_PCR, PCR_CMDQNE|PCR_CMDQ0|PCR_OWN);
865 }
866 }
867
868 /*
869 * Check for dead transmit logic. Not uncommon.
870 */
871 void
872 nitimeout(ifp)
873 struct ifnet *ifp;
874 {
875 #if 0
876 struct ni_softc *sc = ifp->if_softc;
877
878 if (sc->sc_inq == 0)
879 return;
880
881 printf("%s: xmit logic died, resetting...\n", sc->sc_dev.dv_xname);
882 /*
883 * Do a reset of interface, to get it going again.
884 * Will it work by just restart the transmit logic?
885 */
886 niinit(sc);
887 #endif
888 }
889
890 /*
891 * Shutdown hook. Make sure the interface is stopped at reboot.
892 */
893 void
894 ni_shutdown(arg)
895 void *arg;
896 {
897 struct ni_softc *sc = arg;
898
899 WAITREG(NI_PCR, PCR_OWN);
900 NI_WREG(NI_PCR, PCR_OWN|PCR_SHUTDOWN);
901 WAITREG(NI_PCR, PCR_OWN);
902 WAITREG(NI_PSR, PSR_OWN);
903
904 }
905
906