cemacreg.h revision 1.7
1 /* $NetBSD: cemacreg.h,v 1.7 2024/08/29 07:22:36 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Copyright (c) 2007 Embedtronics Oy 8 * All rights reserved 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 #ifndef _IF_CEMACREG_H_ 34 #define _IF_CEMACREG_H_ 35 36 /* Ethernet MAC (EMAC), 37 * at91rm9200.pdf, page 573 */ 38 39 #define ETH_CTL 0x00U /* Control Register */ 40 #define ETH_CFG 0x04U /* Configuration Register */ 41 #define ETH_SR 0x08U /* Status Register */ 42 #define ETH_TAR 0x0CU /* Transmit Address Register (at91rm9200 only) */ 43 #define ETH_TCR 0x10U /* Transmit Control Register (at91rm9200 only) */ 44 #define ETH_TSR 0x14U /* Transmit Status Register */ 45 #define ETH_RBQP 0x18U /* Receive Buffer Queue Pointer */ 46 #define ETH_TBQP 0x1CU /* Transmit Buffer Queue Pointer */ 47 #define ETH_RSR 0x20U /* Receive Status Register */ 48 #define ETH_ISR 0x24U /* Interrupt Status Register */ 49 #define ETH_IER 0x28U /* Interrupt Enable Register */ 50 #define ETH_IDR 0x2CU /* Interrupt Disable Register */ 51 #define ETH_IMR 0x30U /* Interrupt Mask Register */ 52 #define ETH_MAN 0x34U /* PHY Maintenance Register */ 53 54 #define ETH_FRA 0x40U /* Frames Transmitted OK */ 55 #define ETH_SCOL 0x44U /* Single Collision Frames */ 56 #define ETH_MCOL 0x48U /* Multiple Collision Frames */ 57 #define ETH_OK 0x4CU /* Frames Received OK */ 58 #define ETH_SEQE 0x50U /* Frame Check Sequence Errors */ 59 #define ETH_ALE 0x54U /* Alignment Errors */ 60 #define ETH_DTE 0x58U /* Deferred Transmission Frame */ 61 #define ETH_LCOL 0x5CU /* Late Collisions */ 62 #define ETH_ECOL 0x60U /* Excessive Collisions */ 63 #define ETH_CSE 0x64U /* Carrier Sense Errors */ 64 #define ETH_TUE 0x68U /* Transmit Underrun Errors */ 65 #define ETH_CDE 0x6CU /* Code Errors */ 66 #define ETH_ELR 0x70U /* Excessive Length Errors */ 67 #define ETH_RJB 0x74U /* Receive Jabbers */ 68 #define ETH_USF 0x78U /* Undersize Frames */ 69 #define ETH_SQEE 0x7CU /* SQE Test Errors */ 70 #define ETH_DRFC 0x80U /* Discarded RX Frames */ 71 72 #define ETH_HSH 0x90U /* Hash Address High */ 73 #define ETH_HSL 0x94U /* Hash Address Low */ 74 75 #define ETH_SA1L 0x98U /* Specific Address 1 Low */ 76 #define ETH_SA1H 0x9CU /* Specific Address 1 High */ 77 78 #define ETH_SA2L 0xA0U /* Specific Address 2 Low */ 79 #define ETH_SA2H 0xA4U /* Specific Address 2 High */ 80 81 #define ETH_SA3L 0xA8U /* Specific Address 3 Low */ 82 #define ETH_SA3H 0xACU /* Specific Address 3 High */ 83 84 #define ETH_SA4L 0xB0U /* Specific Address 4 Low */ 85 #define ETH_SA4H 0xB4U /* Specific Address 4 High */ 86 87 /* 88 * Gigabit Ethernet Controller (GEM) 89 * ug585-Zynq-7000-TRM.pdf 90 */ 91 92 #define GEM_USER_IO 0x000C 93 #define GEM_DMA_CFG 0x0010 /* DMA Configuration */ 94 #define GEM_DMA_CFG_DISC_WHEN_NO_AHB __BIT(24) 95 #define GEM_DMA_CFG_RX_BUF_SIZE __BITS(23, 16) 96 #define GEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN __BIT(11) 97 #define GEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL __BIT(10) 98 #define GEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL __BITS(9, 8) 99 #define GEM_DMA_CFG_AHB_ENDIAN_SWAP_PKT_EN __BIT(7) 100 #define GEM_DMA_CFG_AHB_ENDIAN_SWAP_MGMT_EN __BIT(6) 101 #define GEM_DMA_CFG_AHB_FIXED_BURST_LEN __BITS(4, 0) 102 #define GEM_HSH 0x0080 103 #define GEM_HSL 0x0084 104 #define GEM_SA1L 0x0088 105 #define GEM_SA1H 0x008C 106 #define GEM_SA2L 0x0090 107 #define GEM_SA2H 0x0094 108 #define GEM_SA3L 0x0098 109 #define GEM_SA3H 0x009C 110 #define GEM_SA4L 0x0090 111 #define GEM_SA4H 0x0094 112 #define GEM_SCOL 0x0138 113 #define GEM_MCOL 0x013C 114 #define GEM_DCFG2 0x0284 115 #define GEM_DCFG3 0x0288 116 #define GEM_DCFG4 0x028C 117 #define GEM_DCFG5 0x0290 118 119 #define ETH_SIZE 0x1000 120 121 /* Control Register bits: */ 122 #define GEM_CTL_ZEROPAUSETX __BIT(12) 123 #define GEM_CTL_PAUSETX __BIT(11) 124 #define GEM_CTL_HALTTX __BIT(10) 125 #define GEM_CTL_STARTTX __BIT(9) 126 127 #define ETH_CTL_BP __BIT(8) /* 1 = back pressure enabled */ 128 #define ETH_CTL_WES __BIT(7) /* 1 = statistics registers writeable */ 129 #define ETH_CTL_ISR __BIT(6) /* 1 = increment statistics registers */ 130 #define ETH_CTL_CSR __BIT(5) /* 1 = clear statistics registers */ 131 #define ETH_CTL_MPE __BIT(4) /* 1 = management port enabled */ 132 #define ETH_CTL_TE __BIT(3) /* 1 = transmit enable */ 133 #define ETH_CTL_RE __BIT(2) /* 1 = receive enable */ 134 #define ETH_CTL_LBL __BIT(1) /* 1 = local loopback enabled */ 135 #define ETH_CTL_LB __BIT(0) /* 1 = loopback signal is at high level */ 136 137 138 /* Configuration Register bits: */ 139 #define ETH_CFG_RMII __BIT(13) /* 1 = enable RMII (Reduce MII) (AT91RM9200 only) */ 140 #define ETH_CFG_RTY __BIT(12) /* 1 = retry test enabled */ 141 #define ETH_CFG_CLK __BITS(11, 10) /* clock */ 142 #define ETH_CFG_CLK_8 __SHIFTIN(0, ETH_CFG_CLK) 143 #define ETH_CFG_CLK_16 __SHIFTIN(1, ETH_CFG_CLK) 144 #define ETH_CFG_CLK_32 __SHIFTIN(2, ETH_CFG_CLK) 145 #define ETH_CFG_CLK_64 __SHIFTIN(3, ETH_CFG_CLK) 146 #define ETH_CFG_EAE __BIT(9) /* 1 = external address match enable */ 147 #define ETH_CFG_BIG __BIT(8) /* 1 = receive up to 1522 bytes (VLAN) */ 148 #define ETH_CFG_UNI __BIT(7) /* 1 = enable unicast hash */ 149 #define ETH_CFG_MTI __BIT(6) /* 1 = enable multicast hash */ 150 #define ETH_CFG_NBC __BIT(5) /* 1 = ignore received broadcasts */ 151 #define ETH_CFG_CAF __BIT(4) /* 1 = receive all valid frames */ 152 #define ETH_CFG_BR __BIT(2) 153 #define ETH_CFG_FD __BIT(1) /* 1 = force full duplex */ 154 #define ETH_CFG_SPD __BIT(0) /* 1 = 100 Mbps */ 155 156 #define GEM_CFG_GEN __BIT(10) 157 #define GEM_CFG_CLK __BITS(20, 18) 158 #define GEM_CFG_CLK_8 __SHIFTIN(0, GEM_CFG_CLK) 159 #define GEM_CFG_CLK_16 __SHIFTIN(1, GEM_CFG_CLK) 160 #define GEM_CFG_CLK_32 __SHIFTIN(2, GEM_CFG_CLK) 161 #define GEM_CFG_CLK_48 __SHIFTIN(3, GEM_CFG_CLK) 162 #define GEM_CFG_CLK_64 __SHIFTIN(4, GEM_CFG_CLK) 163 #define GEM_CFG_CLK_96 __SHIFTIN(5, GEM_CFG_CLK) 164 #define GEM_CFG_DBW __BITS(22, 21) 165 #define GEM_CFG_RXCOEN __BIT(24) 166 167 /* Status Register bits: */ 168 #define ETH_SR_IDLE __BIT(2) /* 1 = PHY logic is running */ 169 #define ETH_SR_MDIO __BIT(1) /* 1 = MDIO pin set */ 170 #define ETH_SR_LINK __BIT(0) 171 172 173 /* Transmit Control Register bits: */ 174 #define ETH_TCR_NCRC 0x8000U /* 1 = don't append CRC */ 175 #define ETH_TCR_LEN 0x07FFU /* transmit frame length */ 176 177 178 /* Transmit Status Register bits: */ 179 #define ETH_TSR_UND __BIT(6) /* 1 = transmit underrun detected */ 180 #define ETH_TSR_COMP __BIT(5) /* 1 = transmit complete */ 181 #define ETH_TSR_BNQ __BIT(4) /* 1 = transmit buffer not queued (at91rm9200 only) */ 182 #define ETH_TSR_IDLE __BIT(3) /* 1 = transmitter idle */ 183 #define ETH_TSR_RLE __BIT(2) /* 1 = retry limit exceeded */ 184 #define ETH_TSR_COL __BIT(1) /* 1 = collision occurred */ 185 #define ETH_TSR_OVR __BIT(0) /* 1 = transmit buffer overrun */ 186 187 #define GEM_TSR_TXGO __BIT(3) 188 189 /* Receive Status Register bits: */ 190 #define ETH_RSR_OVR __BIT(2) /* 1 = RX overrun */ 191 #define ETH_RSR_REC __BIT(1) /* 1 = frame received */ 192 #define ETH_RSR_BNA __BIT(0) /* 1 = buffer not available */ 193 194 195 /* Interrupt bits: */ 196 #define ETH_ISR_ABT __BIT(11) /* 1 = abort during DMA transfer */ 197 #define ETH_ISR_ROVR __BIT(10) /* 1 = RX overrun */ 198 #define ETH_ISR_LINK __BIT(9) /* 1 = link pin changed */ 199 #define ETH_ISR_TIDLE __BIT(8) /* 1 = transmitter idle */ 200 #define ETH_ISR_TCOM __BIT(7) /* 1 = transmit complete */ 201 #define ETH_ISR_TBRE __BIT(6) /* 1 = transmit buffer register empty */ 202 #define ETH_ISR_RTRY __BIT(5) /* 1 = retry limit exceeded */ 203 #define ETH_ISR_TUND __BIT(4) /* 1 = transmit buffer underrun */ 204 #define ETH_ISR_TOVR __BIT(3) /* 1 = transmit buffer overrun */ 205 #define ETH_ISR_RBNA __BIT(2) /* 1 = receive buffer not available */ 206 #define ETH_ISR_RCOM __BIT(1) /* 1 = receive complete */ 207 #define ETH_ISR_DONE __BIT(0) /* 1 = management done */ 208 209 210 /* PHY Maintenance Register bits: */ 211 #define ETH_MAN_LOW __BIT(31) /* must not be set */ 212 #define ETH_MAN_HIGH __BIT(30) /* must be set */ 213 214 #define ETH_MAN_RW __BITS(29, 28) 215 #define ETH_MAN_RW_RD __BIT(29) 216 #define ETH_MAN_RW_WR __BIT(28) 217 218 #define ETH_MAN_PHYA 0x0F800000U /* PHY address (normally 0) */ 219 #define ETH_MAN_PHYA_SHIFT 23U 220 #define ETH_MAN_REGA 0x007C0000U 221 #define ETH_MAN_REGA_SHIFT 18U 222 #define ETH_MAN_CODE 0x00030000U /* must be 10 */ 223 #define ETH_MAN_CODE_IEEE802_3 \ 224 0x00020000U 225 #define ETH_MAN_DATA 0x0000FFFFU /* data to be written to the PHY */ 226 227 #define ETH_MAN_VAL (ETH_MAN_HIGH | ETH_MAN_CODE_IEEE802_3) 228 229 230 /* received buffer descriptor: */ 231 #define ETH_DSC_ADDR 0x00U 232 #define ETH_DSC_FLAGS 0x00U 233 #define ETH_DSC_INFO 0x04U 234 #define ETH_DSC_SIZE 0x08U 235 236 typedef struct eth_dsc { 237 volatile uint32_t Addr; 238 volatile uint32_t Info; 239 } __attribute__ ((aligned(4))) eth_dsc_t; 240 241 /* flags: */ 242 #define ETH_RDSC_F_WRAP __BIT(1) 243 #define ETH_RDSC_F_USED __BIT(0) 244 245 /* frame info bits: */ 246 #define ETH_RDSC_I_BCAST __BIT(31) 247 #define ETH_RDSC_I_MULTICAST __BIT(30) 248 #define ETH_RDSC_I_UNICAST __BIT(29) 249 #define ETH_RDSC_I_VLAN __BIT(28) 250 #define ETH_RDSC_I_UNKNOWN_SRC __BIT(27) 251 #define ETH_RDSC_I_MATCH1 __BIT(26) 252 #define ETH_RDSC_I_MATCH2 __BIT(25) 253 #define ETH_RDSC_I_MATCH3 __BIT(24) 254 #define ETH_RDSC_I_MATCH4 __BIT(23) 255 #define ETH_RDSC_I_CHKSUM __BITS(23, 22) 256 #define ETH_RDSC_I_CHKSUM_NONE __SHIFTIN(0, ETH_RDSC_I_CHKSUM) 257 #define ETH_RDSC_I_CHKSUM_IP __SHIFTIN(1, ETH_RDSC_I_CHKSUM) 258 #define ETH_RDSC_I_CHKSUM_TCP __SHIFTIN(2, ETH_RDSC_I_CHKSUM) 259 #define ETH_RDSC_I_CHKSUM_UDP __SHIFTIN(3, ETH_RDSC_I_CHKSUM) 260 #define ETH_RDSC_I_LEN __BITS(13, 0) 261 262 #define ETH_TDSC_I_USED __BIT(31) /* done transmitting */ 263 #define ETH_TDSC_I_WRAP __BIT(30) /* end of descr ring */ 264 #define ETH_TDSC_I_RETRY_ERR __BIT(29) 265 #define ETH_TDSC_I_AHB_ERR __BIT(27) 266 #define ETH_TDSC_I_LATE_COLL __BIT(26) 267 #define ETH_TDSC_I_CHKSUM __BITS(22, 20) 268 #define ETH_TDSC_I_CHKSUM_GEN_STAT_NO_ERR __SHIFTIN(0, ETH_TDSC_I_CHKSUM) 269 #define ETH_TDSC_I_CHKSUM_GEN_STAT_VLAN_HDR_ERR __SHIFTIN(1, ETH_TDSC_I_CHKSUM) 270 #define ETH_TDSC_I_CHKSUM_GEN_STAT_SNAP_HDR_ERR __SHIFTIN(2, ETH_TDSC_I_CHKSUM) 271 #define ETH_TDSC_I_CHKSUM_GEN_STAT_IP_HDR_ERR __SHIFTIN(3, ETH_TDSC_I_CHKSUM) 272 #define ETH_TDSC_I_CHKSUM_GEN_STAT_UNKNOWN_TYPE __SHIFTIN(4, ETH_TDSC_I_CHKSUM) 273 #define ETH_TDSC_I_CHKSUM_GEN_STAT_UNSUPP_FRAG __SHIFTIN(5, ETH_TDSC_I_CHKSUM) 274 #define ETH_TDSC_I_CHKSUM_GEN_STAT_NOT_TCPUDP __SHIFTIN(6, ETH_TDSC_I_CHKSUM) 275 #define ETH_TDSC_I_CHKSUM_GEN_STAT_SHORT_PKT __SHIFTIN(7, ETH_TDSC_I_CHKSUM) 276 #define ETH_TDSC_I_NO_CRC_APPENDED __BIT(16) 277 #define ETH_TDSC_I_LAST_BUF __BIT(15) /* last buf in frame */ 278 #define ETH_TDSC_I_LEN __BITS(13, 0) 279 280 #endif /* !_IF_CEMACREG_H_ */ 281
Indexes created Wed Oct 22 06:10:02 GMT 2025