11.31Sthorpej/*	$NetBSD: adv_cardbus.c,v 1.31 2022/09/25 17:33:19 thorpej Exp $	*/
21.1Sthorpej
31.1Sthorpej/*-
41.1Sthorpej * Copyright (c) 2000 The NetBSD Foundation, Inc.
51.1Sthorpej * All rights reserved.
61.1Sthorpej *
71.1Sthorpej * This code is derived from software contributed to The NetBSD Foundation
81.1Sthorpej * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
91.1Sthorpej * NASA Ames Research Center.
101.1Sthorpej *
111.1Sthorpej * Redistribution and use in source and binary forms, with or without
121.1Sthorpej * modification, are permitted provided that the following conditions
131.1Sthorpej * are met:
141.1Sthorpej * 1. Redistributions of source code must retain the above copyright
151.1Sthorpej *    notice, this list of conditions and the following disclaimer.
161.1Sthorpej * 2. Redistributions in binary form must reproduce the above copyright
171.1Sthorpej *    notice, this list of conditions and the following disclaimer in the
181.1Sthorpej *    documentation and/or other materials provided with the distribution.
191.1Sthorpej *
201.1Sthorpej * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
211.1Sthorpej * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
221.1Sthorpej * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
231.1Sthorpej * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
241.1Sthorpej * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
251.1Sthorpej * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
261.1Sthorpej * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
271.1Sthorpej * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
281.1Sthorpej * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
291.1Sthorpej * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
301.1Sthorpej * POSSIBILITY OF SUCH DAMAGE.
311.1Sthorpej */
321.1Sthorpej
331.1Sthorpej/*
341.1Sthorpej * this file was brought from ahc_cardbus.c and adv_pci.c
351.1Sthorpej * and modified by YAMAMOTO Takashi.
361.1Sthorpej */
371.5Slukem
381.5Slukem#include <sys/cdefs.h>
391.31Sthorpej__KERNEL_RCSID(0, "$NetBSD: adv_cardbus.c,v 1.31 2022/09/25 17:33:19 thorpej Exp $");
401.1Sthorpej
411.1Sthorpej#include <sys/param.h>
421.1Sthorpej#include <sys/systm.h>
431.1Sthorpej#include <sys/kernel.h>
441.1Sthorpej#include <sys/queue.h>
451.1Sthorpej#include <sys/device.h>
461.1Sthorpej
471.16Sad#include <sys/bus.h>
481.16Sad#include <sys/intr.h>
491.1Sthorpej
501.11Sperry#include <dev/scsipi/scsi_all.h>
511.1Sthorpej#include <dev/scsipi/scsipi_all.h>
521.1Sthorpej#include <dev/scsipi/scsiconf.h>
531.1Sthorpej
541.1Sthorpej#include <dev/pci/pcireg.h>
551.1Sthorpej#include <dev/pci/pcidevs.h>
561.1Sthorpej
571.1Sthorpej#include <dev/cardbus/cardbusvar.h>
581.9Smycroft#include <dev/pci/pcidevs.h>
591.1Sthorpej
601.1Sthorpej#include <dev/ic/advlib.h>
611.1Sthorpej#include <dev/ic/adv.h>
621.1Sthorpej
631.26Sdyoung#define ADV_CARDBUS_IOBA PCI_BAR0
641.26Sdyoung#define ADV_CARDBUS_MMBA PCI_BAR1
651.1Sthorpej
661.3Syamt#define ADV_CARDBUS_DEBUG
671.3Syamt#define ADV_CARDBUS_ALLOW_MEMIO
681.3Syamt
691.29Schs#define DEVNAME(sc) device_xname((sc)->sc_dev)
701.1Sthorpej
711.1Sthorpejstruct adv_cardbus_softc {
721.1Sthorpej	struct asc_softc sc_adv;	/* real ADV */
731.1Sthorpej
741.1Sthorpej	/* CardBus-specific goo. */
751.1Sthorpej	cardbus_devfunc_t sc_ct;	/* our CardBus devfuncs */
761.23Sdyoung	pcitag_t sc_tag;
771.1Sthorpej
781.24Sdyoung	int	sc_bar;
791.25Sdyoung	pcireg_t	sc_csr;
801.1Sthorpej	bus_size_t sc_size;
811.1Sthorpej};
821.1Sthorpej
831.22Sceggerint	adv_cardbus_match(device_t, cfdata_t, void *);
841.22Sceggervoid	adv_cardbus_attach(device_t, device_t, void *);
851.22Sceggerint	adv_cardbus_detach(device_t, int);
861.1Sthorpej
871.29SchsCFATTACH_DECL_NEW(adv_cardbus, sizeof(struct adv_cardbus_softc),
881.8Sthorpej    adv_cardbus_match, adv_cardbus_attach, adv_cardbus_detach, NULL);
891.1Sthorpej
901.1Sthorpejint
911.29Schsadv_cardbus_match(device_t parent, cfdata_t match, void *aux)
921.1Sthorpej{
931.1Sthorpej	struct cardbus_attach_args *ca = aux;
941.1Sthorpej
951.26Sdyoung	if (PCI_VENDOR(ca->ca_id) == PCI_VENDOR_ADVSYS &&
961.26Sdyoung	    PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ADVSYS_ULTRA)
971.1Sthorpej		return (1);
981.1Sthorpej
991.1Sthorpej	return (0);
1001.1Sthorpej}
1011.1Sthorpej
1021.1Sthorpejvoid
1031.29Schsadv_cardbus_attach(device_t parent, device_t self, void *aux)
1041.1Sthorpej{
1051.1Sthorpej	struct cardbus_attach_args *ca = aux;
1061.13Sthorpej	struct adv_cardbus_softc *csc = device_private(self);
1071.1Sthorpej	struct asc_softc *sc = &csc->sc_adv;
1081.1Sthorpej	cardbus_devfunc_t ct = ca->ca_ct;
1091.1Sthorpej	bus_space_tag_t iot;
1101.1Sthorpej	bus_space_handle_t ioh;
1111.1Sthorpej	pcireg_t reg;
1121.1Sthorpej	u_int8_t latency = 0x20;
1131.1Sthorpej
1141.29Schs	sc->sc_dev = self;
1151.1Sthorpej	sc->sc_flags = 0;
1161.1Sthorpej
1171.1Sthorpej	if (PCI_VENDOR(ca->ca_id) == PCI_VENDOR_ADVSYS) {
1181.1Sthorpej		switch (PCI_PRODUCT(ca->ca_id)) {
1191.1Sthorpej		case PCI_PRODUCT_ADVSYS_1200A:
1201.30Smsaitoh			aprint_normal(": AdvanSys ASC1200A SCSI adapter\n");
1211.1Sthorpej			latency = 0;
1221.1Sthorpej			break;
1231.1Sthorpej
1241.1Sthorpej		case PCI_PRODUCT_ADVSYS_1200B:
1251.30Smsaitoh			aprint_normal(": AdvanSys ASC1200B SCSI adapter\n");
1261.1Sthorpej			latency = 0;
1271.1Sthorpej			break;
1281.1Sthorpej
1291.1Sthorpej		case PCI_PRODUCT_ADVSYS_ULTRA:
1301.1Sthorpej			switch (PCI_REVISION(ca->ca_class)) {
1311.1Sthorpej			case ASC_PCI_REVISION_3050:
1321.30Smsaitoh				aprint_normal(": AdvanSys ABP-9xxUA "
1331.30Smsaitoh				    "SCSI adapter\n");
1341.1Sthorpej				break;
1351.1Sthorpej
1361.1Sthorpej			case ASC_PCI_REVISION_3150:
1371.30Smsaitoh				aprint_normal(": AdvanSys ABP-9xxU "
1381.30Smsaitoh				    "SCSI adapter\n");
1391.1Sthorpej				break;
1401.1Sthorpej			}
1411.1Sthorpej			break;
1421.1Sthorpej
1431.1Sthorpej		default:
1441.30Smsaitoh			aprint_error(": unknown model!\n");
1451.1Sthorpej			return;
1461.1Sthorpej		}
1471.1Sthorpej	}
1481.1Sthorpej
1491.1Sthorpej	csc->sc_ct = ct;
1501.1Sthorpej	csc->sc_tag = ca->ca_tag;
1511.1Sthorpej
1521.1Sthorpej	/*
1531.1Sthorpej	 * Map the device.
1541.1Sthorpej	 */
1551.1Sthorpej	csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
1561.11Sperry
1571.3Syamt#ifdef ADV_CARDBUS_ALLOW_MEMIO
1581.1Sthorpej	if (Cardbus_mapreg_map(csc->sc_ct, ADV_CARDBUS_MMBA,
1591.1Sthorpej	    PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
1601.1Sthorpej	    &iot, &ioh, NULL, &csc->sc_size) == 0) {
1611.3Syamt#ifdef ADV_CARDBUS_DEBUG
1621.3Syamt		printf("%s: memio enabled\n", DEVNAME(sc));
1631.3Syamt#endif
1641.24Sdyoung		csc->sc_bar = ADV_CARDBUS_MMBA;
1651.1Sthorpej		csc->sc_csr |= PCI_COMMAND_MEM_ENABLE;
1661.1Sthorpej	} else
1671.1Sthorpej#endif
1681.1Sthorpej	if (Cardbus_mapreg_map(csc->sc_ct, ADV_CARDBUS_IOBA,
1691.1Sthorpej	    PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, &csc->sc_size) == 0) {
1701.3Syamt#ifdef ADV_CARDBUS_DEBUG
1711.1Sthorpej		printf("%s: io enabled\n", DEVNAME(sc));
1721.3Syamt#endif
1731.24Sdyoung		csc->sc_bar = ADV_CARDBUS_IOBA;
1741.1Sthorpej		csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
1751.1Sthorpej	} else {
1761.24Sdyoung		csc->sc_bar = 0;
1771.30Smsaitoh		aprint_error_dev(self, "unable to map device registers\n");
1781.1Sthorpej		return;
1791.1Sthorpej	}
1801.3Syamt
1811.1Sthorpej	/* Enable the appropriate bits in the PCI CSR. */
1821.27Sdyoung	reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);
1831.1Sthorpej	reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
1841.1Sthorpej	reg |= csc->sc_csr;
1851.27Sdyoung	Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);
1861.1Sthorpej
1871.1Sthorpej	/*
1881.1Sthorpej	 * Make sure the latency timer is set to some reasonable
1891.1Sthorpej	 * value.
1901.1Sthorpej	 */
1911.27Sdyoung	reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_BHLC_REG);
1921.1Sthorpej	if (PCI_LATTIMER(reg) < latency) {
1931.1Sthorpej		reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
1941.1Sthorpej		reg |= (latency << PCI_LATTIMER_SHIFT);
1951.27Sdyoung		Cardbus_conf_write(ct, ca->ca_tag, PCI_BHLC_REG, reg);
1961.1Sthorpej	}
1971.1Sthorpej
1981.1Sthorpej	ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT);
1991.1Sthorpej	ASC_SET_CHIP_STATUS(iot, ioh, 0);
2001.1Sthorpej
2011.1Sthorpej	sc->sc_iot = iot;
2021.1Sthorpej	sc->sc_ioh = ioh;
2031.1Sthorpej	sc->sc_dmat = ca->ca_dmat;
2041.1Sthorpej	sc->pci_device_id = ca->ca_id;
2051.1Sthorpej	sc->bus_type = ASC_IS_PCI;
2061.1Sthorpej	sc->chip_version = ASC_GET_CHIP_VER_NO(iot, ioh);
2071.3Syamt
2081.1Sthorpej	/*
2091.2Swiz	 * Initialize the board
2101.1Sthorpej	 */
2111.1Sthorpej	if (adv_init(sc)) {
2121.30Smsaitoh		aprint_error_dev(self, "adv_init failed\n");
2131.1Sthorpej		return;
2141.1Sthorpej	}
2151.1Sthorpej
2161.1Sthorpej	/*
2171.1Sthorpej	 * Establish the interrupt.
2181.1Sthorpej	 */
2191.28Sdrochner	sc->sc_ih = Cardbus_intr_establish(ct, IPL_BIO, adv_intr, sc);
2201.1Sthorpej	if (sc->sc_ih == NULL) {
2211.30Smsaitoh		aprint_error_dev(self, "unable to establish interrupt\n");
2221.1Sthorpej		return;
2231.1Sthorpej	}
2241.1Sthorpej
2251.1Sthorpej	/*
2261.1Sthorpej	 * Attach.
2271.1Sthorpej	 */
2281.1Sthorpej	adv_attach(sc);
2291.1Sthorpej}
2301.1Sthorpej
2311.1Sthorpejint
2321.22Sceggeradv_cardbus_detach(device_t self, int flags)
2331.1Sthorpej{
2341.13Sthorpej	struct adv_cardbus_softc *csc = device_private(self);
2351.1Sthorpej	struct asc_softc *sc = &csc->sc_adv;
2361.1Sthorpej
2371.1Sthorpej	int rv;
2381.1Sthorpej
2391.1Sthorpej	rv = adv_detach(sc, flags);
2401.1Sthorpej	if (rv)
2411.1Sthorpej		return rv;
2421.1Sthorpej
2431.1Sthorpej	if (sc->sc_ih) {
2441.27Sdyoung		Cardbus_intr_disestablish(csc->sc_ct, sc->sc_ih);
2451.1Sthorpej		sc->sc_ih = 0;
2461.1Sthorpej	}
2471.1Sthorpej
2481.24Sdyoung	if (csc->sc_bar != 0) {
2491.24Sdyoung		Cardbus_mapreg_unmap(csc->sc_ct, csc->sc_bar,
2501.24Sdyoung		    sc->sc_iot, sc->sc_ioh, csc->sc_size);
2511.24Sdyoung		csc->sc_bar = 0;
2521.1Sthorpej	}
2531.1Sthorpej
2541.1Sthorpej	return 0;
2551.1Sthorpej}
256