adv_cardbus.c revision 1.23 
1/*	$NetBSD: adv_cardbus.c,v 1.23 2010/02/24 19:52:51 dyoung Exp $	*/
2
3/*-
4 * Copyright (c) 2000 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 *    notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 *    notice, this list of conditions and the following disclaimer in the
18 *    documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/*
34 * this file was brought from ahc_cardbus.c and adv_pci.c
35 * and modified by YAMAMOTO Takashi.
36 */
37
38#include <sys/cdefs.h>
39__KERNEL_RCSID(0, "$NetBSD: adv_cardbus.c,v 1.23 2010/02/24 19:52:51 dyoung Exp $");
40
41#include <sys/param.h>
42#include <sys/systm.h>
43#include <sys/malloc.h>
44#include <sys/kernel.h>
45#include <sys/queue.h>
46#include <sys/device.h>
47
48#include <sys/bus.h>
49#include <sys/intr.h>
50
51#include <dev/scsipi/scsi_all.h>
52#include <dev/scsipi/scsipi_all.h>
53#include <dev/scsipi/scsiconf.h>
54
55#include <dev/pci/pcireg.h>
56#include <dev/pci/pcidevs.h>
57
58#include <dev/cardbus/cardbusvar.h>
59#include <dev/pci/pcidevs.h>
60
61#include <dev/ic/advlib.h>
62#include <dev/ic/adv.h>
63
64#define ADV_CARDBUS_IOBA CARDBUS_BASE0_REG
65#define ADV_CARDBUS_MMBA CARDBUS_BASE1_REG
66
67#define ADV_CARDBUS_DEBUG
68#define ADV_CARDBUS_ALLOW_MEMIO
69
70#define DEVNAME(sc) device_xname(&(sc)->sc_dev)
71
72struct adv_cardbus_softc {
73	struct asc_softc sc_adv;	/* real ADV */
74
75	/* CardBus-specific goo. */
76	cardbus_devfunc_t sc_ct;	/* our CardBus devfuncs */
77	pcitag_t sc_tag;
78
79	int	sc_cbenable;		/* what CardBus access type to enable */
80	int	sc_csr;			/* CSR bits */
81	bus_size_t sc_size;
82};
83
84int	adv_cardbus_match(device_t, cfdata_t, void *);
85void	adv_cardbus_attach(device_t, device_t, void *);
86int	adv_cardbus_detach(device_t, int);
87
88CFATTACH_DECL(adv_cardbus, sizeof(struct adv_cardbus_softc),
89    adv_cardbus_match, adv_cardbus_attach, adv_cardbus_detach, NULL);
90
91int
92adv_cardbus_match(device_t parent, cfdata_t match,
93    void *aux)
94{
95	struct cardbus_attach_args *ca = aux;
96
97	if (CARDBUS_VENDOR(ca->ca_id) == PCI_VENDOR_ADVSYS &&
98	    CARDBUS_PRODUCT(ca->ca_id) == PCI_PRODUCT_ADVSYS_ULTRA)
99		return (1);
100
101	return (0);
102}
103
104void
105adv_cardbus_attach(device_t parent, device_t self,
106    void *aux)
107{
108	struct cardbus_attach_args *ca = aux;
109	struct adv_cardbus_softc *csc = device_private(self);
110	struct asc_softc *sc = &csc->sc_adv;
111	cardbus_devfunc_t ct = ca->ca_ct;
112	cardbus_chipset_tag_t cc = ct->ct_cc;
113	cardbus_function_tag_t cf = ct->ct_cf;
114	bus_space_tag_t iot;
115	bus_space_handle_t ioh;
116	pcireg_t reg;
117	u_int8_t latency = 0x20;
118
119	sc->sc_flags = 0;
120
121	if (PCI_VENDOR(ca->ca_id) == PCI_VENDOR_ADVSYS) {
122		switch (PCI_PRODUCT(ca->ca_id)) {
123		case PCI_PRODUCT_ADVSYS_1200A:
124			printf(": AdvanSys ASC1200A SCSI adapter\n");
125			latency = 0;
126			break;
127
128		case PCI_PRODUCT_ADVSYS_1200B:
129			printf(": AdvanSys ASC1200B SCSI adapter\n");
130			latency = 0;
131			break;
132
133		case PCI_PRODUCT_ADVSYS_ULTRA:
134			switch (PCI_REVISION(ca->ca_class)) {
135			case ASC_PCI_REVISION_3050:
136				printf(": AdvanSys ABP-9xxUA SCSI adapter\n");
137				break;
138
139			case ASC_PCI_REVISION_3150:
140				printf(": AdvanSys ABP-9xxU SCSI adapter\n");
141				break;
142			}
143			break;
144
145		default:
146			printf(": unknown model!\n");
147			return;
148		}
149	}
150
151	csc->sc_ct = ct;
152	csc->sc_tag = ca->ca_tag;
153	csc->sc_cbenable = 0;
154
155	/*
156	 * Map the device.
157	 */
158	csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
159
160#ifdef ADV_CARDBUS_ALLOW_MEMIO
161	if (Cardbus_mapreg_map(csc->sc_ct, ADV_CARDBUS_MMBA,
162	    PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
163	    &iot, &ioh, NULL, &csc->sc_size) == 0) {
164#ifdef ADV_CARDBUS_DEBUG
165		printf("%s: memio enabled\n", DEVNAME(sc));
166#endif
167		csc->sc_cbenable = CARDBUS_MEM_ENABLE;
168		csc->sc_csr |= PCI_COMMAND_MEM_ENABLE;
169	} else
170#endif
171	if (Cardbus_mapreg_map(csc->sc_ct, ADV_CARDBUS_IOBA,
172	    PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, &csc->sc_size) == 0) {
173#ifdef ADV_CARDBUS_DEBUG
174		printf("%s: io enabled\n", DEVNAME(sc));
175#endif
176		csc->sc_cbenable = CARDBUS_IO_ENABLE;
177		csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
178	} else {
179		aprint_error_dev(&sc->sc_dev, "unable to map device registers\n");
180		return;
181	}
182
183	/* Make sure the right access type is on the CardBus bridge. */
184	(*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cbenable);
185	(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
186
187	/* Enable the appropriate bits in the PCI CSR. */
188	reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG);
189	reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
190	reg |= csc->sc_csr;
191	cardbus_conf_write(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);
192
193	/*
194	 * Make sure the latency timer is set to some reasonable
195	 * value.
196	 */
197	reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_BHLC_REG);
198	if (PCI_LATTIMER(reg) < latency) {
199		reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
200		reg |= (latency << PCI_LATTIMER_SHIFT);
201		cardbus_conf_write(cc, cf, ca->ca_tag, PCI_BHLC_REG, reg);
202	}
203
204	ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT);
205	ASC_SET_CHIP_STATUS(iot, ioh, 0);
206
207	sc->sc_iot = iot;
208	sc->sc_ioh = ioh;
209	sc->sc_dmat = ca->ca_dmat;
210	sc->pci_device_id = ca->ca_id;
211	sc->bus_type = ASC_IS_PCI;
212	sc->chip_version = ASC_GET_CHIP_VER_NO(iot, ioh);
213
214	/*
215	 * Initialize the board
216	 */
217	if (adv_init(sc)) {
218		printf("adv_init failed\n");
219		return;
220	}
221
222	/*
223	 * Establish the interrupt.
224	 */
225	sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_BIO,
226	    adv_intr, sc);
227	if (sc->sc_ih == NULL) {
228		aprint_error_dev(&sc->sc_dev,
229				 "unable to establish interrupt\n");
230		return;
231	}
232
233	/*
234	 * Attach.
235	 */
236	adv_attach(sc);
237}
238
239int
240adv_cardbus_detach(device_t self, int flags)
241{
242	struct adv_cardbus_softc *csc = device_private(self);
243	struct asc_softc *sc = &csc->sc_adv;
244
245	int rv;
246
247	rv = adv_detach(sc, flags);
248	if (rv)
249		return rv;
250
251	if (sc->sc_ih) {
252		cardbus_intr_disestablish(csc->sc_ct->ct_cc,
253		    csc->sc_ct->ct_cf, sc->sc_ih);
254		sc->sc_ih = 0;
255	}
256
257	if (csc->sc_cbenable) {
258#ifdef ADV_CARDBUS_ALLOW_MEMIO
259		if (csc->sc_cbenable == CARDBUS_MEM_ENABLE) {
260			Cardbus_mapreg_unmap(csc->sc_ct, ADV_CARDBUS_MMBA,
261			    sc->sc_iot, sc->sc_ioh, csc->sc_size);
262		} else {
263#endif
264			Cardbus_mapreg_unmap(csc->sc_ct, ADV_CARDBUS_IOBA,
265			    sc->sc_iot, sc->sc_ioh, csc->sc_size);
266#ifdef ADV_CARDBUS_ALLOW_MEMIO
267		}
268#endif
269		csc->sc_cbenable = 0;
270	}
271
272	return 0;
273}
274