cardbus.c revision 1.101
1 /* $NetBSD: cardbus.c,v 1.101 2010/02/24 22:37:57 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: cardbus.c,v 1.101 2010/02/24 22:37:57 dyoung Exp $"); 31 32 #include "opt_cardbus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/syslog.h> 40 #include <sys/proc.h> 41 #include <sys/reboot.h> /* for AB_* needed by bootverbose */ 42 43 #include <sys/bus.h> 44 45 #include <dev/cardbus/cardbusvar.h> 46 #include <dev/pci/pcidevs.h> 47 48 #include <dev/cardbus/cardbus_exrom.h> 49 50 #include <dev/pci/pcivar.h> /* XXX */ 51 #include <dev/pci/pcireg.h> /* XXX */ 52 53 #include <dev/pcmcia/pcmciareg.h> 54 55 #include "locators.h" 56 57 #if defined CARDBUS_DEBUG 58 #define STATIC 59 #define DPRINTF(a) printf a 60 #else 61 #define STATIC static 62 #define DPRINTF(a) 63 #endif 64 65 66 STATIC void cardbusattach(device_t, device_t, void *); 67 STATIC int cardbusdetach(device_t, int); 68 STATIC int cardbusmatch(device_t, cfdata_t, void *); 69 int cardbus_rescan(device_t, const char *, const int *); 70 void cardbus_childdetached(device_t, device_t); 71 static int cardbusprint(void *, const char *); 72 73 typedef void (*tuple_decode_func)(u_int8_t*, int, void*); 74 75 static int decode_tuples(u_int8_t *, int, tuple_decode_func, void*); 76 #ifdef CARDBUS_DEBUG 77 static void print_tuple(u_int8_t*, int, void*); 78 #endif 79 80 static int cardbus_read_tuples(struct cardbus_attach_args *, 81 cardbusreg_t, u_int8_t *, size_t); 82 83 static void enable_function(struct cardbus_softc *, int, int); 84 static void disable_function(struct cardbus_softc *, int); 85 86 static bool cardbus_child_register(device_t); 87 88 CFATTACH_DECL3_NEW(cardbus, sizeof(struct cardbus_softc), 89 cardbusmatch, cardbusattach, cardbusdetach, NULL, 90 cardbus_rescan, cardbus_childdetached, DVF_DETACH_SHUTDOWN); 91 92 #ifndef __NetBSD_Version__ 93 struct cfdriver cardbus_cd = { 94 NULL, "cardbus", DV_DULL 95 }; 96 #endif 97 98 99 STATIC int 100 cardbusmatch(device_t parent, cfdata_t cf, void *aux) 101 { 102 103 return (1); 104 } 105 106 STATIC void 107 cardbusattach(device_t parent, device_t self, void *aux) 108 { 109 struct cardbus_softc *sc = device_private(self); 110 struct cbslot_attach_args *cba = aux; 111 112 sc->sc_dev = self; 113 114 sc->sc_bus = cba->cba_bus; 115 sc->sc_intrline = cba->cba_intrline; 116 sc->sc_cacheline = cba->cba_cacheline; 117 sc->sc_max_lattimer = MIN(0xf8, cba->cba_max_lattimer); 118 119 aprint_naive("\n"); 120 aprint_normal(": bus %d", sc->sc_bus); 121 if (bootverbose) 122 aprint_normal(" cacheline 0x%x, lattimer 0x%x", 123 sc->sc_cacheline, sc->sc_max_lattimer); 124 aprint_normal("\n"); 125 126 sc->sc_iot = cba->cba_iot; /* CardBus I/O space tag */ 127 sc->sc_memt = cba->cba_memt; /* CardBus MEM space tag */ 128 sc->sc_dmat = cba->cba_dmat; /* DMA tag */ 129 sc->sc_cc = cba->cba_cc; 130 sc->sc_cf = cba->cba_cf; 131 132 #if rbus 133 sc->sc_rbus_iot = cba->cba_rbus_iot; 134 sc->sc_rbus_memt = cba->cba_rbus_memt; 135 #endif 136 137 if (!pmf_device_register(self, NULL, NULL)) 138 aprint_error_dev(self, "couldn't establish power handler\n"); 139 } 140 141 STATIC int 142 cardbusdetach(device_t self, int flags) 143 { 144 int rc; 145 146 if ((rc = config_detach_children(self, flags)) != 0) 147 return rc; 148 149 pmf_device_deregister(self); 150 return 0; 151 } 152 153 static int 154 cardbus_read_tuples(struct cardbus_attach_args *ca, cardbusreg_t cis_ptr, 155 u_int8_t *tuples, size_t len) 156 { 157 struct cardbus_softc *sc = ca->ca_ct->ct_sc; 158 cardbus_chipset_tag_t cc = ca->ca_ct->ct_cc; 159 cardbus_function_tag_t cf = ca->ca_ct->ct_cf; 160 cardbustag_t tag = ca->ca_tag; 161 cardbusreg_t command; 162 bus_space_tag_t bar_tag; 163 bus_space_handle_t bar_memh; 164 bus_size_t bar_size; 165 bus_addr_t bar_addr; 166 cardbusreg_t reg; 167 int found = 0; 168 int cardbus_space = cis_ptr & CARDBUS_CIS_ASIMASK; 169 int i, j; 170 171 memset(tuples, 0, len); 172 173 cis_ptr = cis_ptr & CARDBUS_CIS_ADDRMASK; 174 175 switch (cardbus_space) { 176 case CARDBUS_CIS_ASI_TUPLE: 177 DPRINTF(("%s: reading CIS data from configuration space\n", 178 device_xname(sc->sc_dev))); 179 for (i = cis_ptr, j = 0; i < 0xff; i += 4) { 180 u_int32_t e = (*cf->cardbus_conf_read)(cc, tag, i); 181 tuples[j] = 0xff & e; 182 e >>= 8; 183 tuples[j + 1] = 0xff & e; 184 e >>= 8; 185 tuples[j + 2] = 0xff & e; 186 e >>= 8; 187 tuples[j + 3] = 0xff & e; 188 j += 4; 189 } 190 found++; 191 break; 192 193 case CARDBUS_CIS_ASI_BAR0: 194 case CARDBUS_CIS_ASI_BAR1: 195 case CARDBUS_CIS_ASI_BAR2: 196 case CARDBUS_CIS_ASI_BAR3: 197 case CARDBUS_CIS_ASI_BAR4: 198 case CARDBUS_CIS_ASI_BAR5: 199 case CARDBUS_CIS_ASI_ROM: 200 if (cardbus_space == CARDBUS_CIS_ASI_ROM) { 201 reg = CARDBUS_ROM_REG; 202 DPRINTF(("%s: reading CIS data from ROM\n", 203 device_xname(sc->sc_dev))); 204 } else { 205 reg = CARDBUS_CIS_ASI_BAR(cardbus_space); 206 DPRINTF(("%s: reading CIS data from BAR%d\n", 207 device_xname(sc->sc_dev), cardbus_space - 1)); 208 } 209 210 /* 211 * XXX zero register so mapreg_map doesn't get confused by old 212 * contents. 213 */ 214 cardbus_conf_write(cc, cf, tag, reg, 0); 215 if (Cardbus_mapreg_map(ca->ca_ct, reg, 216 CARDBUS_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 217 0, &bar_tag, &bar_memh, &bar_addr, &bar_size)) { 218 aprint_error_dev(sc->sc_dev, "failed to map memory\n"); 219 return (1); 220 } 221 aprint_debug_dev(sc->sc_dev, "mapped %ju bytes at 0x%jx\n", 222 (uintmax_t)bar_size, (uintmax_t)bar_addr); 223 224 if (cardbus_space == CARDBUS_CIS_ASI_ROM) { 225 cardbusreg_t exrom; 226 int save; 227 struct cardbus_rom_image_head rom_image; 228 struct cardbus_rom_image *p; 229 230 save = splhigh(); 231 /* enable rom address decoder */ 232 exrom = cardbus_conf_read(cc, cf, tag, reg); 233 cardbus_conf_write(cc, cf, tag, reg, exrom | 1); 234 235 command = cardbus_conf_read(cc, cf, tag, 236 CARDBUS_COMMAND_STATUS_REG); 237 cardbus_conf_write(cc, cf, tag, 238 CARDBUS_COMMAND_STATUS_REG, 239 command | CARDBUS_COMMAND_MEM_ENABLE); 240 241 if (cardbus_read_exrom(bar_tag, bar_memh, &rom_image)) 242 goto out; 243 244 SIMPLEQ_FOREACH(p, &rom_image, next) { 245 if (p->rom_image == 246 CARDBUS_CIS_ASI_ROM_IMAGE(cis_ptr)) { 247 bus_space_read_region_1(p->romt, 248 p->romh, CARDBUS_CIS_ADDR(cis_ptr), 249 tuples, MIN(p->image_size, len)); 250 found++; 251 break; 252 } 253 } 254 while ((p = SIMPLEQ_FIRST(&rom_image)) != NULL) { 255 SIMPLEQ_REMOVE_HEAD(&rom_image, next); 256 free(p, M_DEVBUF); 257 } 258 out: 259 exrom = cardbus_conf_read(cc, cf, tag, reg); 260 cardbus_conf_write(cc, cf, tag, reg, exrom & ~1); 261 splx(save); 262 } else { 263 command = cardbus_conf_read(cc, cf, tag, 264 CARDBUS_COMMAND_STATUS_REG); 265 cardbus_conf_write(cc, cf, tag, 266 CARDBUS_COMMAND_STATUS_REG, 267 command | CARDBUS_COMMAND_MEM_ENABLE); 268 /* XXX byte order? */ 269 bus_space_read_region_1(bar_tag, bar_memh, 270 cis_ptr, tuples, 271 MIN(bar_size - MIN(bar_size, cis_ptr), len)); 272 found++; 273 } 274 command = cardbus_conf_read(cc, cf, tag, 275 CARDBUS_COMMAND_STATUS_REG); 276 cardbus_conf_write(cc, cf, tag, CARDBUS_COMMAND_STATUS_REG, 277 command & ~CARDBUS_COMMAND_MEM_ENABLE); 278 cardbus_conf_write(cc, cf, tag, reg, 0); 279 280 Cardbus_mapreg_unmap(ca->ca_ct, reg, bar_tag, bar_memh, 281 bar_size); 282 break; 283 284 #ifdef DIAGNOSTIC 285 default: 286 panic("%s: bad CIS space (%d)", device_xname(sc->sc_dev), 287 cardbus_space); 288 #endif 289 } 290 return (!found); 291 } 292 293 static void 294 parse_tuple(u_int8_t *tuple, int len, void *data) 295 { 296 struct cardbus_cis_info *cis = data; 297 char *p; 298 int i, bar_index; 299 300 switch (tuple[0]) { 301 case PCMCIA_CISTPL_MANFID: 302 if (tuple[1] != 4) { 303 DPRINTF(("%s: wrong length manufacturer id (%d)\n", 304 __func__, tuple[1])); 305 break; 306 } 307 cis->manufacturer = tuple[2] | (tuple[3] << 8); 308 cis->product = tuple[4] | (tuple[5] << 8); 309 break; 310 311 case PCMCIA_CISTPL_VERS_1: 312 memcpy(cis->cis1_info_buf, tuple + 2, tuple[1]); 313 i = 0; 314 p = cis->cis1_info_buf + 2; 315 while (i < 316 sizeof(cis->cis1_info) / sizeof(cis->cis1_info[0])) { 317 if (p >= cis->cis1_info_buf + tuple[1] || *p == '\xff') 318 break; 319 cis->cis1_info[i++] = p; 320 while (*p != '\0' && *p != '\xff') 321 p++; 322 if (*p == '\0') 323 p++; 324 } 325 break; 326 327 case PCMCIA_CISTPL_BAR: 328 if (tuple[1] != 6) { 329 DPRINTF(("%s: BAR with short length (%d)\n", 330 __func__, tuple[1])); 331 break; 332 } 333 bar_index = tuple[2] & 7; 334 if (bar_index == 0) { 335 DPRINTF(("%s: invalid ASI in BAR tuple\n", __func__)); 336 break; 337 } 338 bar_index--; 339 cis->bar[bar_index].flags = tuple[2]; 340 cis->bar[bar_index].size = 341 (tuple[4] << 0) | 342 (tuple[5] << 8) | 343 (tuple[6] << 16) | 344 (tuple[7] << 24); 345 break; 346 347 case PCMCIA_CISTPL_FUNCID: 348 cis->funcid = tuple[2]; 349 break; 350 351 case PCMCIA_CISTPL_FUNCE: 352 switch (cis->funcid) { 353 case PCMCIA_FUNCTION_SERIAL: 354 if (tuple[1] >= 2 && 355 /* XXX PCMCIA_TPLFE_TYPE_SERIAL_??? */ 356 tuple[2] == 0) { 357 cis->funce.serial.uart_type = tuple[3] & 0x1f; 358 cis->funce.serial.uart_present = 1; 359 } 360 break; 361 362 case PCMCIA_FUNCTION_NETWORK: 363 if (tuple[1] >= 8 && 364 tuple[2] == PCMCIA_TPLFE_TYPE_LAN_NID) { 365 if (tuple[3] > 366 sizeof(cis->funce.network.netid)) { 367 DPRINTF(("%s: unknown network id type " 368 "(len = %d)\n", 369 __func__, tuple[3])); 370 } else { 371 cis->funce.network.netid_present = 1; 372 memcpy(cis->funce.network.netid, 373 tuple + 4, tuple[3]); 374 } 375 } 376 break; 377 } 378 break; 379 } 380 } 381 382 /* 383 * int cardbus_attach_card(struct cardbus_softc *sc) 384 * 385 * This function attaches the card on the slot: turns on power, 386 * reads and analyses tuple, sets configuration index. 387 * 388 * This function returns the number of recognised device functions. 389 * If no functions are recognised, return 0. 390 */ 391 int 392 cardbus_attach_card(struct cardbus_softc *sc) 393 { 394 cardbus_chipset_tag_t cc; 395 cardbus_function_tag_t cf; 396 int cdstatus; 397 static int wildcard[CARDBUSCF_NLOCS] = { 398 CARDBUSCF_FUNCTION_DEFAULT 399 }; 400 401 cc = sc->sc_cc; 402 cf = sc->sc_cf; 403 404 DPRINTF(("cardbus_attach_card: cb%d start\n", 405 device_unit(sc->sc_dev))); 406 407 /* inspect initial voltage */ 408 if ((cdstatus = (*cf->cardbus_ctrl)(cc, CARDBUS_CD)) == 0) { 409 DPRINTF(("%s: no CardBus card on cb%d\n", __func__, 410 device_unit(sc->sc_dev))); 411 return (0); 412 } 413 414 device_pmf_driver_set_child_register(sc->sc_dev, cardbus_child_register); 415 cardbus_rescan(sc->sc_dev, "cardbus", wildcard); 416 return (1); /* XXX */ 417 } 418 419 int 420 cardbus_rescan(device_t self, const char *ifattr, 421 const int *locators) 422 { 423 struct cardbus_softc *sc = device_private(self); 424 cardbus_chipset_tag_t cc; 425 cardbus_function_tag_t cf; 426 cardbustag_t tag; 427 cardbusreg_t id, class, cis_ptr; 428 cardbusreg_t bhlc, icr, lattimer; 429 int cdstatus; 430 int function, nfunction; 431 device_t csc; 432 cardbus_devfunc_t ct; 433 434 cc = sc->sc_cc; 435 cf = sc->sc_cf; 436 437 /* inspect initial voltage */ 438 if ((cdstatus = (*cf->cardbus_ctrl)(cc, CARDBUS_CD)) == 0) { 439 DPRINTF(("%s: no CardBus card on cb%d\n", __func__, 440 device_unit(sc->sc_dev))); 441 return (0); 442 } 443 444 /* 445 * XXX use fake function 8 to keep power on during whole 446 * configuration. 447 */ 448 enable_function(sc, cdstatus, 8); 449 function = 0; 450 451 tag = cardbus_make_tag(cc, cf, sc->sc_bus, function); 452 453 /* 454 * Wait until power comes up. Maxmum 500 ms. 455 * 456 * XXX What is this for? The bridge driver ought to have waited 457 * XXX already. 458 */ 459 { 460 int i; 461 462 for (i = 0; i < 5; ++i) { 463 id = cardbus_conf_read(cc, cf, tag, CARDBUS_ID_REG); 464 if (id != 0xffffffff && id != 0) { 465 break; 466 } 467 if (cold) { /* before kernel thread invoked */ 468 delay(100 * 1000); 469 } else { /* thread context */ 470 if (tsleep((void *)sc, PCATCH, "cardbus", 471 hz / 10) != EWOULDBLOCK) { 472 break; 473 } 474 } 475 } 476 aprint_debug_dev(self, "id reg valid in %d iterations\n", i); 477 if (i == 5) { 478 return (EIO); 479 } 480 } 481 482 bhlc = cardbus_conf_read(cc, cf, tag, CARDBUS_BHLC_REG); 483 DPRINTF(("%s bhlc 0x%08x -> ", device_xname(sc->sc_dev), bhlc)); 484 nfunction = CARDBUS_HDRTYPE_MULTIFN(bhlc) ? 8 : 1; 485 486 for (function = 0; function < nfunction; function++) { 487 struct cardbus_attach_args ca; 488 int locs[CARDBUSCF_NLOCS]; 489 490 if (locators[CARDBUSCF_FUNCTION] != 491 CARDBUSCF_FUNCTION_DEFAULT && 492 locators[CARDBUSCF_FUNCTION] != function) 493 continue; 494 495 if (sc->sc_funcs[function]) 496 continue; 497 498 tag = cardbus_make_tag(cc, cf, sc->sc_bus, function); 499 500 id = cardbus_conf_read(cc, cf, tag, CARDBUS_ID_REG); 501 class = cardbus_conf_read(cc, cf, tag, CARDBUS_CLASS_REG); 502 cis_ptr = cardbus_conf_read(cc, cf, tag, CARDBUS_CIS_REG); 503 504 /* Invalid vendor ID value? */ 505 if (CARDBUS_VENDOR(id) == PCI_VENDOR_INVALID) { 506 continue; 507 } 508 509 DPRINTF(("cardbus_attach_card: " 510 "Vendor 0x%x, Product 0x%x, CIS 0x%x\n", 511 CARDBUS_VENDOR(id), CARDBUS_PRODUCT(id), cis_ptr)); 512 513 enable_function(sc, cdstatus, function); 514 515 /* clean up every BAR */ 516 cardbus_conf_write(cc, cf, tag, CARDBUS_BASE0_REG, 0); 517 cardbus_conf_write(cc, cf, tag, CARDBUS_BASE1_REG, 0); 518 cardbus_conf_write(cc, cf, tag, CARDBUS_BASE2_REG, 0); 519 cardbus_conf_write(cc, cf, tag, CARDBUS_BASE3_REG, 0); 520 cardbus_conf_write(cc, cf, tag, CARDBUS_BASE4_REG, 0); 521 cardbus_conf_write(cc, cf, tag, CARDBUS_BASE5_REG, 0); 522 cardbus_conf_write(cc, cf, tag, CARDBUS_ROM_REG, 0); 523 524 /* set initial latency and cacheline size */ 525 bhlc = cardbus_conf_read(cc, cf, tag, CARDBUS_BHLC_REG); 526 icr = cardbus_conf_read(cc, cf, tag, CARDBUS_INTERRUPT_REG); 527 DPRINTF(("%s func%d icr 0x%08x bhlc 0x%08x -> ", 528 device_xname(sc->sc_dev), function, icr, bhlc)); 529 bhlc &= ~(CARDBUS_CACHELINE_MASK << CARDBUS_CACHELINE_SHIFT); 530 bhlc |= (sc->sc_cacheline & CARDBUS_CACHELINE_MASK) << 531 CARDBUS_CACHELINE_SHIFT; 532 /* 533 * Set the initial value of the Latency Timer. 534 * 535 * While a PCI device owns the bus, its Latency 536 * Timer counts down bus cycles from its initial 537 * value to 0. Minimum Grant tells for how long 538 * the device wants to own the bus once it gets 539 * access, in units of 250ns. 540 * 541 * On a 33 MHz bus, there are 8 cycles per 250ns. 542 * So I multiply the Minimum Grant by 8 to find 543 * out the initial value of the Latency Timer. 544 * 545 * Avoid setting a Latency Timer less than 0x10, 546 * since the old code did not do that. 547 */ 548 lattimer = 549 MIN(sc->sc_max_lattimer, MAX(0x10, 8 * PCI_MIN_GNT(icr))); 550 if (PCI_LATTIMER(bhlc) < lattimer) { 551 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 552 bhlc |= (lattimer << PCI_LATTIMER_SHIFT); 553 } 554 555 cardbus_conf_write(cc, cf, tag, CARDBUS_BHLC_REG, bhlc); 556 bhlc = cardbus_conf_read(cc, cf, tag, CARDBUS_BHLC_REG); 557 DPRINTF(("0x%08x\n", bhlc)); 558 559 /* 560 * We need to allocate the ct here, since we might 561 * need it when reading the CIS 562 */ 563 if ((ct = malloc(sizeof(struct cardbus_devfunc), 564 M_DEVBUF, M_NOWAIT)) == NULL) { 565 panic("no room for cardbus_tag"); 566 } 567 568 ct->ct_bhlc = bhlc; 569 ct->ct_cc = sc->sc_cc; 570 ct->ct_cf = sc->sc_cf; 571 ct->ct_bus = sc->sc_bus; 572 ct->ct_func = function; 573 ct->ct_sc = sc; 574 sc->sc_funcs[function] = ct; 575 576 memset(&ca, 0, sizeof(ca)); 577 578 ca.ca_ct = ct; 579 580 ca.ca_iot = sc->sc_iot; 581 ca.ca_memt = sc->sc_memt; 582 ca.ca_dmat = sc->sc_dmat; 583 584 #if rbus 585 ca.ca_rbus_iot = sc->sc_rbus_iot; 586 ca.ca_rbus_memt= sc->sc_rbus_memt; 587 #endif 588 589 ca.ca_tag = tag; 590 ca.ca_bus = sc->sc_bus; 591 ca.ca_function = function; 592 ca.ca_id = id; 593 ca.ca_class = class; 594 595 ca.ca_intrline = sc->sc_intrline; 596 597 if (cis_ptr != 0) { 598 #define TUPLESIZE 2048 599 u_int8_t *tuple = malloc(TUPLESIZE, M_DEVBUF, M_WAITOK); 600 if (cardbus_read_tuples(&ca, cis_ptr, 601 tuple, TUPLESIZE)) { 602 printf("cardbus_attach_card: " 603 "failed to read CIS\n"); 604 } else { 605 #ifdef CARDBUS_DEBUG 606 decode_tuples(tuple, TUPLESIZE, 607 print_tuple, NULL); 608 #endif 609 decode_tuples(tuple, TUPLESIZE, 610 parse_tuple, &ca.ca_cis); 611 } 612 free(tuple, M_DEVBUF); 613 } 614 615 locs[CARDBUSCF_FUNCTION] = function; 616 617 if ((csc = config_found_sm_loc(sc->sc_dev, "cardbus", locs, 618 &ca, cardbusprint, config_stdsubmatch)) == NULL) { 619 /* do not match */ 620 disable_function(sc, function); 621 sc->sc_funcs[function] = NULL; 622 free(ct, M_DEVBUF); 623 } else { 624 /* found */ 625 ct->ct_device = csc; 626 } 627 } 628 /* 629 * XXX power down pseudo function 8 (this will power down the card 630 * if no functions were attached). 631 */ 632 disable_function(sc, 8); 633 634 return (0); 635 } 636 637 static int 638 cardbusprint(void *aux, const char *pnp) 639 { 640 struct cardbus_attach_args *ca = aux; 641 char devinfo[256]; 642 int i; 643 644 if (pnp) { 645 pci_devinfo(ca->ca_id, ca->ca_class, 1, devinfo, 646 sizeof(devinfo)); 647 for (i = 0; i < 4; i++) { 648 if (ca->ca_cis.cis1_info[i] == NULL) 649 break; 650 if (i) 651 aprint_normal(", "); 652 aprint_normal("%s", ca->ca_cis.cis1_info[i]); 653 } 654 aprint_verbose("%s(manufacturer 0x%x, product 0x%x)", 655 i ? " " : "", 656 ca->ca_cis.manufacturer, ca->ca_cis.product); 657 aprint_normal(" %s at %s", devinfo, pnp); 658 } 659 aprint_normal(" function %d", ca->ca_function); 660 661 return (UNCONF); 662 } 663 664 /* 665 * void cardbus_detach_card(struct cardbus_softc *sc) 666 * 667 * This function detaches the card on the slot: detach device data 668 * structure and turns off the power. 669 * 670 * This function must not be called under interrupt context. 671 */ 672 void 673 cardbus_detach_card(struct cardbus_softc *sc) 674 { 675 int f; 676 struct cardbus_devfunc *ct; 677 678 for (f = 0; f < 8; f++) { 679 ct = sc->sc_funcs[f]; 680 if (!ct) 681 continue; 682 683 DPRINTF(("%s: detaching %s\n", device_xname(sc->sc_dev), 684 device_xname(ct->ct_device))); 685 /* call device detach function */ 686 687 if (config_detach(ct->ct_device, 0) != 0) { 688 aprint_error_dev(sc->sc_dev, 689 "cannot detach dev %s, function %d\n", 690 device_xname(ct->ct_device), ct->ct_func); 691 } 692 } 693 694 sc->sc_poweron_func = 0; 695 (*sc->sc_cf->cardbus_power)(sc->sc_cc, 696 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 697 } 698 699 void 700 cardbus_childdetached(device_t self, device_t child) 701 { 702 struct cardbus_softc *sc = device_private(self); 703 struct cardbus_devfunc *ct; 704 705 ct = sc->sc_funcs[device_locator(child, CARDBUSCF_FUNCTION)]; 706 KASSERT(ct->ct_device == child); 707 708 sc->sc_poweron_func &= ~(1 << ct->ct_func); 709 sc->sc_funcs[ct->ct_func] = NULL; 710 free(ct, M_DEVBUF); 711 } 712 713 /* 714 * void *cardbus_intr_establish(cc, cf, irq, level, func, arg) 715 * Interrupt handler of pccard. 716 * args: 717 * cardbus_chipset_tag_t *cc 718 * int irq: 719 */ 720 void * 721 cardbus_intr_establish(cardbus_chipset_tag_t cc, cardbus_function_tag_t cf, 722 cardbus_intr_line_t irq, int level, int (*func)(void *), void *arg) 723 { 724 725 DPRINTF(("- cardbus_intr_establish: irq %d\n", irq)); 726 return ((*cf->cardbus_intr_establish)(cc, irq, level, func, arg)); 727 } 728 729 /* 730 * void cardbus_intr_disestablish(cc, cf, handler) 731 * Interrupt handler of pccard. 732 * args: 733 * cardbus_chipset_tag_t *cc 734 */ 735 void 736 cardbus_intr_disestablish(cardbus_chipset_tag_t cc, cardbus_function_tag_t cf, 737 void *handler) 738 { 739 740 DPRINTF(("- pccard_intr_disestablish\n")); 741 (*cf->cardbus_intr_disestablish)(cc, handler); 742 } 743 744 /* 745 * XXX this should be merged with cardbus_function_{enable,disable}, 746 * but we don't have a ct when these functions are called. 747 */ 748 static void 749 enable_function(struct cardbus_softc *sc, int cdstatus, int function) 750 { 751 752 if (sc->sc_poweron_func == 0) { 753 /* switch to 3V and/or wait for power to stabilize */ 754 if (cdstatus & CARDBUS_3V_CARD) { 755 /* 756 * sc_poweron_func must be substituted before 757 * entering sleep, in order to avoid turn on 758 * power twice. 759 */ 760 sc->sc_poweron_func |= (1 << function); 761 (*sc->sc_cf->cardbus_power)(sc->sc_cc, CARDBUS_VCC_3V); 762 } else { 763 /* No cards other than 3.3V cards. */ 764 return; 765 } 766 (*sc->sc_cf->cardbus_ctrl)(sc->sc_cc, CARDBUS_RESET); 767 } 768 sc->sc_poweron_func |= (1 << function); 769 } 770 771 static void 772 disable_function(struct cardbus_softc *sc, int function) 773 { 774 bool powerdown; 775 cardbus_devfunc_t ct; 776 device_t dv; 777 int i; 778 779 sc->sc_poweron_func &= ~(1 << function); 780 if (sc->sc_poweron_func != 0) 781 return; 782 for (i = 0; i < __arraycount(sc->sc_funcs); i++) { 783 if ((ct = sc->sc_funcs[i]) == NULL) 784 continue; 785 dv = ct->ct_device; 786 if (prop_dictionary_get_bool(device_properties(dv), 787 "pmf-powerdown", &powerdown) && !powerdown) 788 return; 789 } 790 /* power-off because no functions are enabled */ 791 (*sc->sc_cf->cardbus_power)(sc->sc_cc, CARDBUS_VCC_0V); 792 } 793 794 /* 795 * int cardbus_function_enable(struct cardbus_softc *sc, int func) 796 * 797 * This function enables a function on a card. When no power is 798 * applied on the card, power will be applied on it. 799 */ 800 int 801 cardbus_function_enable(struct cardbus_softc *sc, int func) 802 { 803 cardbus_chipset_tag_t cc = sc->sc_cc; 804 cardbus_function_tag_t cf = sc->sc_cf; 805 cardbus_devfunc_t ct; 806 cardbusreg_t command; 807 cardbustag_t tag; 808 809 DPRINTF(("entering cardbus_function_enable... ")); 810 811 /* entering critical area */ 812 813 /* XXX: sc_vold should be used */ 814 enable_function(sc, CARDBUS_3V_CARD, func); 815 816 /* exiting critical area */ 817 818 tag = cardbus_make_tag(cc, cf, sc->sc_bus, func); 819 820 command = cardbus_conf_read(cc, cf, tag, CARDBUS_COMMAND_STATUS_REG); 821 command |= (CARDBUS_COMMAND_MEM_ENABLE | CARDBUS_COMMAND_IO_ENABLE | 822 CARDBUS_COMMAND_MASTER_ENABLE); /* XXX: good guess needed */ 823 824 cardbus_conf_write(cc, cf, tag, CARDBUS_COMMAND_STATUS_REG, command); 825 826 if ((ct = sc->sc_funcs[func]) != NULL) 827 Cardbus_conf_write(ct, tag, CARDBUS_BHLC_REG, ct->ct_bhlc); 828 829 cardbus_free_tag(cc, cf, tag); 830 831 DPRINTF(("%x\n", sc->sc_poweron_func)); 832 833 return (0); 834 } 835 836 /* 837 * int cardbus_function_disable(struct cardbus_softc *, int func) 838 * 839 * This function disable a function on a card. When no functions are 840 * enabled, it turns off the power. 841 */ 842 int 843 cardbus_function_disable(struct cardbus_softc *sc, int func) 844 { 845 846 DPRINTF(("entering cardbus_function_disable... ")); 847 848 disable_function(sc, func); 849 850 return (0); 851 } 852 853 /* 854 * int cardbus_get_capability(cardbus_chipset_tag_t cc, 855 * cardbus_function_tag_t cf, cardbustag_t tag, int capid, int *offset, 856 * cardbusreg_t *value) 857 * 858 * Find the specified PCI capability. 859 */ 860 int 861 cardbus_get_capability(cardbus_chipset_tag_t cc, cardbus_function_tag_t cf, 862 cardbustag_t tag, int capid, int *offset, cardbusreg_t *value) 863 { 864 cardbusreg_t reg; 865 unsigned int ofs; 866 867 reg = cardbus_conf_read(cc, cf, tag, PCI_COMMAND_STATUS_REG); 868 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 869 return (0); 870 871 ofs = PCI_CAPLIST_PTR(cardbus_conf_read(cc, cf, tag, 872 PCI_CAPLISTPTR_REG)); 873 while (ofs != 0) { 874 #ifdef DIAGNOSTIC 875 if ((ofs & 3) || (ofs < 0x40)) 876 panic("cardbus_get_capability"); 877 #endif 878 reg = cardbus_conf_read(cc, cf, tag, ofs); 879 if (PCI_CAPLIST_CAP(reg) == capid) { 880 if (offset) 881 *offset = ofs; 882 if (value) 883 *value = reg; 884 return (1); 885 } 886 ofs = PCI_CAPLIST_NEXT(reg); 887 } 888 889 return (0); 890 } 891 892 /* 893 * below this line, there are some functions for decoding tuples. 894 * They should go out from this file. 895 */ 896 897 static u_int8_t * 898 decode_tuple(u_int8_t *, u_int8_t *, tuple_decode_func, void *); 899 900 static int 901 decode_tuples(u_int8_t *tuple, int buflen, tuple_decode_func func, void *data) 902 { 903 u_int8_t *tp = tuple; 904 905 if (PCMCIA_CISTPL_LINKTARGET != *tuple) { 906 DPRINTF(("WRONG TUPLE: 0x%x\n", *tuple)); 907 return (0); 908 } 909 910 while ((tp = decode_tuple(tp, tuple + buflen, func, data)) != NULL) 911 ; 912 913 return (1); 914 } 915 916 static u_int8_t * 917 decode_tuple(u_int8_t *tuple, u_int8_t *end, 918 tuple_decode_func func, void *data) 919 { 920 u_int8_t type; 921 u_int8_t len; 922 923 type = tuple[0]; 924 switch (type) { 925 case PCMCIA_CISTPL_NULL: 926 case PCMCIA_CISTPL_END: 927 len = 1; 928 break; 929 default: 930 if (tuple + 2 > end) 931 return (NULL); 932 len = tuple[1] + 2; 933 break; 934 } 935 936 if (tuple + len > end) 937 return (NULL); 938 939 (*func)(tuple, len, data); 940 941 if (type == PCMCIA_CISTPL_END || tuple + len == end) 942 return (NULL); 943 944 return (tuple + len); 945 } 946 947 /* 948 * XXX: this is another reason why this code should be shared with PCI. 949 */ 950 static int 951 cardbus_get_powerstate_int(cardbus_devfunc_t ct, cardbustag_t tag, 952 cardbusreg_t *state, int offset) 953 { 954 cardbusreg_t value, now; 955 cardbus_chipset_tag_t cc = ct->ct_cc; 956 cardbus_function_tag_t cf = ct->ct_cf; 957 958 value = cardbus_conf_read(cc, cf, tag, offset + PCI_PMCSR); 959 now = value & PCI_PMCSR_STATE_MASK; 960 switch (now) { 961 case PCI_PMCSR_STATE_D0: 962 case PCI_PMCSR_STATE_D1: 963 case PCI_PMCSR_STATE_D2: 964 case PCI_PMCSR_STATE_D3: 965 *state = now; 966 return 0; 967 default: 968 return EINVAL; 969 } 970 } 971 972 int 973 cardbus_get_powerstate(cardbus_devfunc_t ct, cardbustag_t tag, 974 cardbusreg_t *state) 975 { 976 cardbus_chipset_tag_t cc = ct->ct_cc; 977 cardbus_function_tag_t cf = ct->ct_cf; 978 int offset; 979 cardbusreg_t value; 980 981 if (!cardbus_get_capability(cc, cf, tag, PCI_CAP_PWRMGMT, &offset, &value)) 982 return EOPNOTSUPP; 983 984 return cardbus_get_powerstate_int(ct, tag, state, offset); 985 } 986 987 static int 988 cardbus_set_powerstate_int(cardbus_devfunc_t ct, cardbustag_t tag, 989 cardbusreg_t state, int offset, cardbusreg_t cap_reg) 990 { 991 cardbus_chipset_tag_t cc = ct->ct_cc; 992 cardbus_function_tag_t cf = ct->ct_cf; 993 994 cardbusreg_t value, cap, now; 995 996 KASSERT((offset & 0x3) == 0); 997 998 cap = cap_reg >> PCI_PMCR_SHIFT; 999 value = cardbus_conf_read(cc, cf, tag, offset + PCI_PMCSR); 1000 now = value & PCI_PMCSR_STATE_MASK; 1001 value &= ~PCI_PMCSR_STATE_MASK; 1002 1003 if (now == state) 1004 return 0; 1005 switch (state) { 1006 case PCI_PMCSR_STATE_D0: 1007 break; 1008 case PCI_PMCSR_STATE_D1: 1009 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 1010 printf("invalid transition from %d to D1\n", (int)now); 1011 return EINVAL; 1012 } 1013 if (!(cap & PCI_PMCR_D1SUPP)) { 1014 printf("D1 not supported\n"); 1015 return EOPNOTSUPP; 1016 } 1017 break; 1018 case PCI_PMCSR_STATE_D2: 1019 if (now == PCI_PMCSR_STATE_D3) { 1020 printf("invalid transition from %d to D2\n", (int)now); 1021 return EINVAL; 1022 } 1023 if (!(cap & PCI_PMCR_D2SUPP)) { 1024 printf("D2 not supported\n"); 1025 return EOPNOTSUPP; 1026 } 1027 break; 1028 case PCI_PMCSR_STATE_D3: 1029 break; 1030 default: 1031 return EINVAL; 1032 } 1033 value |= state; 1034 cardbus_conf_write(cc, cf, tag, offset + PCI_PMCSR, value); 1035 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 1036 DELAY(10000); 1037 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 1038 DELAY(200); 1039 1040 return 0; 1041 } 1042 1043 int 1044 cardbus_set_powerstate(cardbus_devfunc_t ct, cardbustag_t tag, cardbusreg_t state) 1045 { 1046 cardbus_chipset_tag_t cc = ct->ct_cc; 1047 cardbus_function_tag_t cf = ct->ct_cf; 1048 int offset; 1049 cardbusreg_t value; 1050 1051 if (!cardbus_get_capability(cc, cf, tag, PCI_CAP_PWRMGMT, &offset, 1052 &value)) 1053 return EOPNOTSUPP; 1054 1055 return cardbus_set_powerstate_int(ct, tag, state, offset, value); 1056 } 1057 1058 #ifdef CARDBUS_DEBUG 1059 static const char *tuple_name(int); 1060 static const char *tuple_names[] = { 1061 "TPL_NULL", "TPL_DEVICE", "Reserved", "Reserved", /* 0-3 */ 1062 "CONFIG_CB", "CFTABLE_ENTRY_CB", "Reserved", "BAR", /* 4-7 */ 1063 "Reserved", "Reserved", "Reserved", "Reserved", /* 8-B */ 1064 "Reserved", "Reserved", "Reserved", "Reserved", /* C-F */ 1065 "CHECKSUM", "LONGLINK_A", "LONGLINK_C", "LINKTARGET", /* 10-13 */ 1066 "NO_LINK", "VERS_1", "ALTSTR", "DEVICE_A", 1067 "JEDEC_C", "JEDEC_A", "CONFIG", "CFTABLE_ENTRY", 1068 "DEVICE_OC", "DEVICE_OA", "DEVICE_GEO", "DEVICE_GEO_A", 1069 "MANFID", "FUNCID", "FUNCE", "SWIL", /* 20-23 */ 1070 "Reserved", "Reserved", "Reserved", "Reserved", /* 24-27 */ 1071 "Reserved", "Reserved", "Reserved", "Reserved", /* 28-2B */ 1072 "Reserved", "Reserved", "Reserved", "Reserved", /* 2C-2F */ 1073 "Reserved", "Reserved", "Reserved", "Reserved", /* 30-33 */ 1074 "Reserved", "Reserved", "Reserved", "Reserved", /* 34-37 */ 1075 "Reserved", "Reserved", "Reserved", "Reserved", /* 38-3B */ 1076 "Reserved", "Reserved", "Reserved", "Reserved", /* 3C-3F */ 1077 "VERS_2", "FORMAT", "GEOMETRY", "BYTEORDER", 1078 "DATE", "BATTERY", "ORG" 1079 }; 1080 #define NAME_LEN(x) (sizeof x / sizeof(x[0])) 1081 1082 static const char * 1083 tuple_name(int type) 1084 { 1085 1086 if (0 <= type && type < NAME_LEN(tuple_names)) { 1087 return (tuple_names[type]); 1088 } else if (type == 0xff) { 1089 return ("END"); 1090 } else { 1091 return ("Reserved"); 1092 } 1093 } 1094 1095 static void 1096 print_tuple(u_int8_t *tuple, int len, void *data) 1097 { 1098 int i; 1099 1100 printf("tuple: %s len %d\n", tuple_name(tuple[0]), len); 1101 1102 for (i = 0; i < len; ++i) { 1103 if (i % 16 == 0) { 1104 printf(" 0x%2x:", i); 1105 } 1106 printf(" %x", tuple[i]); 1107 if (i % 16 == 15) { 1108 printf("\n"); 1109 } 1110 } 1111 if (i % 16 != 0) { 1112 printf("\n"); 1113 } 1114 } 1115 #endif 1116 1117 void 1118 cardbus_conf_capture(cardbus_chipset_tag_t cc, cardbus_function_tag_t cf, 1119 cardbustag_t tag, struct cardbus_conf_state *pcs) 1120 { 1121 int off; 1122 1123 for (off = 0; off < 16; off++) 1124 pcs->reg[off] = cardbus_conf_read(cc, cf, tag, (off * 4)); 1125 } 1126 1127 void 1128 cardbus_conf_restore(cardbus_chipset_tag_t cc, cardbus_function_tag_t cf, 1129 cardbustag_t tag, struct cardbus_conf_state *pcs) 1130 { 1131 int off; 1132 cardbusreg_t val; 1133 1134 for (off = 15; off >= 0; off--) { 1135 val = cardbus_conf_read(cc, cf, tag, (off * 4)); 1136 if (val != pcs->reg[off]) 1137 cardbus_conf_write(cc, cf,tag, (off * 4), pcs->reg[off]); 1138 } 1139 } 1140 1141 struct cardbus_child_power { 1142 struct cardbus_conf_state p_cardbusconf; 1143 cardbus_devfunc_t p_ct; 1144 cardbustag_t p_tag; 1145 cardbus_chipset_tag_t p_cc; 1146 cardbus_function_tag_t p_cf; 1147 cardbusreg_t p_pm_cap; 1148 bool p_has_pm; 1149 int p_pm_offset; 1150 }; 1151 1152 static bool 1153 cardbus_child_suspend(device_t dv, const pmf_qual_t *qual) 1154 { 1155 struct cardbus_child_power *priv = device_pmf_bus_private(dv); 1156 1157 cardbus_conf_capture(priv->p_cc, priv->p_cf, priv->p_tag, 1158 &priv->p_cardbusconf); 1159 1160 if (priv->p_has_pm && 1161 cardbus_set_powerstate_int(priv->p_ct, priv->p_tag, 1162 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 1163 aprint_error_dev(dv, "unsupported state, continuing.\n"); 1164 return false; 1165 } 1166 1167 Cardbus_function_disable(priv->p_ct); 1168 1169 return true; 1170 } 1171 1172 static bool 1173 cardbus_child_resume(device_t dv, const pmf_qual_t *qual) 1174 { 1175 struct cardbus_child_power *priv = device_pmf_bus_private(dv); 1176 1177 Cardbus_function_enable(priv->p_ct); 1178 1179 if (priv->p_has_pm && 1180 cardbus_set_powerstate_int(priv->p_ct, priv->p_tag, 1181 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 1182 aprint_error_dev(dv, "unsupported state, continuing.\n"); 1183 return false; 1184 } 1185 1186 cardbus_conf_restore(priv->p_cc, priv->p_cf, priv->p_tag, 1187 &priv->p_cardbusconf); 1188 1189 return true; 1190 } 1191 1192 static void 1193 cardbus_child_deregister(device_t dv) 1194 { 1195 struct cardbus_child_power *priv = device_pmf_bus_private(dv); 1196 1197 free(priv, M_DEVBUF); 1198 } 1199 1200 static bool 1201 cardbus_child_register(device_t child) 1202 { 1203 device_t self = device_parent(child); 1204 struct cardbus_softc *sc = device_private(self); 1205 struct cardbus_devfunc *ct; 1206 struct cardbus_child_power *priv; 1207 int off; 1208 cardbusreg_t reg; 1209 1210 ct = sc->sc_funcs[device_locator(child, CARDBUSCF_FUNCTION)]; 1211 1212 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 1213 1214 priv->p_ct = ct; 1215 priv->p_cc = ct->ct_cc; 1216 priv->p_cf = ct->ct_cf; 1217 priv->p_tag = cardbus_make_tag(priv->p_cc, priv->p_cf, ct->ct_bus, 1218 ct->ct_func); 1219 1220 if (cardbus_get_capability(priv->p_cc, priv->p_cf, priv->p_tag, 1221 PCI_CAP_PWRMGMT, &off, ®)) { 1222 priv->p_has_pm = true; 1223 priv->p_pm_offset = off; 1224 priv->p_pm_cap = reg; 1225 } else { 1226 priv->p_has_pm = false; 1227 priv->p_pm_offset = -1; 1228 } 1229 1230 device_pmf_bus_register(child, priv, cardbus_child_suspend, 1231 cardbus_child_resume, 0, cardbus_child_deregister); 1232 1233 return true; 1234 } 1235
Indexes created Tue Sep 30 07:10:03 GMT 2025