cardbus.c revision 1.109
1 /* $NetBSD: cardbus.c,v 1.109 2019/11/10 21:16:34 chs Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 and 2000 5 * HAYAKAWA Koichi. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: cardbus.c,v 1.109 2019/11/10 21:16:34 chs Exp $"); 31 32 #include "opt_cardbus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/syslog.h> 40 #include <sys/proc.h> 41 #include <sys/reboot.h> /* for AB_* needed by bootverbose */ 42 43 #include <sys/bus.h> 44 45 #include <dev/cardbus/cardbusvar.h> 46 #include <dev/pci/pcidevs.h> 47 48 #include <dev/cardbus/cardbus_exrom.h> 49 50 #include <dev/pci/pcivar.h> /* XXX */ 51 #include <dev/pci/pcireg.h> /* XXX */ 52 53 #include <dev/pcmcia/pcmciareg.h> 54 55 #include "locators.h" 56 57 #if defined CARDBUS_DEBUG 58 #define STATIC 59 #define DPRINTF(a) printf a 60 #else 61 #define STATIC static 62 #define DPRINTF(a) 63 #endif 64 65 66 STATIC void cardbusattach(device_t, device_t, void *); 67 STATIC int cardbusdetach(device_t, int); 68 STATIC int cardbusmatch(device_t, cfdata_t, void *); 69 int cardbus_rescan(device_t, const char *, const int *); 70 void cardbus_childdetached(device_t, device_t); 71 static int cardbusprint(void *, const char *); 72 73 typedef void (*tuple_decode_func)(u_int8_t*, int, void*); 74 75 static int decode_tuples(u_int8_t *, int, tuple_decode_func, void*); 76 #ifdef CARDBUS_DEBUG 77 static void print_tuple(u_int8_t*, int, void*); 78 #endif 79 80 static int cardbus_read_tuples(struct cardbus_attach_args *, 81 pcireg_t, u_int8_t *, size_t); 82 83 static void enable_function(struct cardbus_softc *, int, int); 84 static void disable_function(struct cardbus_softc *, int); 85 86 static bool cardbus_child_register(device_t); 87 88 CFATTACH_DECL3_NEW(cardbus, sizeof(struct cardbus_softc), 89 cardbusmatch, cardbusattach, cardbusdetach, NULL, 90 cardbus_rescan, cardbus_childdetached, DVF_DETACH_SHUTDOWN); 91 92 #ifndef __NetBSD_Version__ 93 struct cfdriver cardbus_cd = { 94 NULL, "cardbus", DV_DULL 95 }; 96 #endif 97 98 99 STATIC int 100 cardbusmatch(device_t parent, cfdata_t cf, void *aux) 101 { 102 103 return (1); 104 } 105 106 STATIC void 107 cardbusattach(device_t parent, device_t self, void *aux) 108 { 109 struct cardbus_softc *sc = device_private(self); 110 struct cbslot_attach_args *cba = aux; 111 112 sc->sc_dev = self; 113 114 sc->sc_bus = cba->cba_bus; 115 sc->sc_cacheline = cba->cba_cacheline; 116 sc->sc_max_lattimer = MIN(0xf8, cba->cba_max_lattimer); 117 118 aprint_naive("\n"); 119 aprint_normal(": bus %d", sc->sc_bus); 120 if (bootverbose) 121 aprint_normal(" cacheline 0x%x, lattimer 0x%x", 122 sc->sc_cacheline, sc->sc_max_lattimer); 123 aprint_normal("\n"); 124 125 sc->sc_iot = cba->cba_iot; /* CardBus I/O space tag */ 126 sc->sc_memt = cba->cba_memt; /* CardBus MEM space tag */ 127 sc->sc_dmat = cba->cba_dmat; /* DMA tag */ 128 sc->sc_cc = cba->cba_cc; 129 sc->sc_cf = cba->cba_cf; 130 131 sc->sc_rbus_iot = cba->cba_rbus_iot; 132 sc->sc_rbus_memt = cba->cba_rbus_memt; 133 134 if (!pmf_device_register(self, NULL, NULL)) 135 aprint_error_dev(self, "couldn't establish power handler\n"); 136 } 137 138 STATIC int 139 cardbusdetach(device_t self, int flags) 140 { 141 int rc; 142 143 if ((rc = config_detach_children(self, flags)) != 0) 144 return rc; 145 146 pmf_device_deregister(self); 147 return 0; 148 } 149 150 static int 151 cardbus_read_tuples(struct cardbus_attach_args *ca, pcireg_t cis_ptr, 152 u_int8_t *tuples, size_t len) 153 { 154 struct cardbus_softc *sc = ca->ca_ct->ct_sc; 155 cardbus_chipset_tag_t cc = ca->ca_ct->ct_cc; 156 cardbus_function_tag_t cf = ca->ca_ct->ct_cf; 157 pcitag_t tag = ca->ca_tag; 158 pcireg_t command; 159 bus_space_tag_t bar_tag; 160 bus_space_handle_t bar_memh; 161 bus_size_t bar_size; 162 bus_addr_t bar_addr; 163 pcireg_t reg; 164 int found = 0; 165 int cardbus_space = cis_ptr & CARDBUS_CIS_ASIMASK; 166 int i, j; 167 168 memset(tuples, 0, len); 169 170 cis_ptr = cis_ptr & CARDBUS_CIS_ADDRMASK; 171 172 switch (cardbus_space) { 173 case CARDBUS_CIS_ASI_TUPLE: 174 DPRINTF(("%s: reading CIS data from configuration space\n", 175 device_xname(sc->sc_dev))); 176 for (i = cis_ptr, j = 0; i < 0xff; i += 4) { 177 u_int32_t e = (*cf->cardbus_conf_read)(cc, tag, i); 178 tuples[j] = 0xff & e; 179 e >>= 8; 180 tuples[j + 1] = 0xff & e; 181 e >>= 8; 182 tuples[j + 2] = 0xff & e; 183 e >>= 8; 184 tuples[j + 3] = 0xff & e; 185 j += 4; 186 } 187 found++; 188 break; 189 190 case CARDBUS_CIS_ASI_BAR0: 191 case CARDBUS_CIS_ASI_BAR1: 192 case CARDBUS_CIS_ASI_BAR2: 193 case CARDBUS_CIS_ASI_BAR3: 194 case CARDBUS_CIS_ASI_BAR4: 195 case CARDBUS_CIS_ASI_BAR5: 196 case CARDBUS_CIS_ASI_ROM: 197 if (cardbus_space == CARDBUS_CIS_ASI_ROM) { 198 reg = CARDBUS_ROM_REG; 199 DPRINTF(("%s: reading CIS data from ROM\n", 200 device_xname(sc->sc_dev))); 201 } else { 202 reg = CARDBUS_CIS_ASI_BAR(cardbus_space); 203 DPRINTF(("%s: reading CIS data from BAR%d\n", 204 device_xname(sc->sc_dev), cardbus_space - 1)); 205 } 206 207 /* 208 * XXX zero register so mapreg_map doesn't get confused by old 209 * contents. 210 */ 211 cardbus_conf_write(cc, cf, tag, reg, 0); 212 if (Cardbus_mapreg_map(ca->ca_ct, reg, 213 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 214 0, &bar_tag, &bar_memh, &bar_addr, &bar_size)) { 215 aprint_error_dev(sc->sc_dev, "failed to map memory\n"); 216 return (1); 217 } 218 aprint_debug_dev(sc->sc_dev, "mapped %ju bytes at 0x%jx\n", 219 (uintmax_t)bar_size, (uintmax_t)bar_addr); 220 221 if (cardbus_space == CARDBUS_CIS_ASI_ROM) { 222 pcireg_t exrom; 223 int save; 224 struct cardbus_rom_image_head rom_image; 225 struct cardbus_rom_image *p; 226 227 save = splhigh(); 228 /* enable rom address decoder */ 229 exrom = cardbus_conf_read(cc, cf, tag, reg); 230 cardbus_conf_write(cc, cf, tag, reg, exrom | 1); 231 232 command = cardbus_conf_read(cc, cf, tag, 233 PCI_COMMAND_STATUS_REG); 234 cardbus_conf_write(cc, cf, tag, 235 PCI_COMMAND_STATUS_REG, 236 command | PCI_COMMAND_MEM_ENABLE); 237 238 if (cardbus_read_exrom(bar_tag, bar_memh, &rom_image)) 239 goto out; 240 241 SIMPLEQ_FOREACH(p, &rom_image, next) { 242 if (p->rom_image == 243 CARDBUS_CIS_ASI_ROM_IMAGE(cis_ptr)) { 244 bus_space_read_region_1(p->romt, 245 p->romh, CARDBUS_CIS_ADDR(cis_ptr), 246 tuples, MIN(p->image_size, len)); 247 found++; 248 break; 249 } 250 } 251 while ((p = SIMPLEQ_FIRST(&rom_image)) != NULL) { 252 SIMPLEQ_REMOVE_HEAD(&rom_image, next); 253 free(p, M_DEVBUF); 254 } 255 out: 256 exrom = cardbus_conf_read(cc, cf, tag, reg); 257 cardbus_conf_write(cc, cf, tag, reg, exrom & ~1); 258 splx(save); 259 } else { 260 command = cardbus_conf_read(cc, cf, tag, 261 PCI_COMMAND_STATUS_REG); 262 cardbus_conf_write(cc, cf, tag, 263 PCI_COMMAND_STATUS_REG, 264 command | PCI_COMMAND_MEM_ENABLE); 265 /* XXX byte order? */ 266 bus_space_read_region_1(bar_tag, bar_memh, 267 cis_ptr, tuples, 268 MIN(bar_size - MIN(bar_size, cis_ptr), len)); 269 found++; 270 } 271 command = cardbus_conf_read(cc, cf, tag, 272 PCI_COMMAND_STATUS_REG); 273 cardbus_conf_write(cc, cf, tag, PCI_COMMAND_STATUS_REG, 274 command & ~PCI_COMMAND_MEM_ENABLE); 275 cardbus_conf_write(cc, cf, tag, reg, 0); 276 277 Cardbus_mapreg_unmap(ca->ca_ct, reg, bar_tag, bar_memh, 278 bar_size); 279 break; 280 281 #ifdef DIAGNOSTIC 282 default: 283 panic("%s: bad CIS space (%d)", device_xname(sc->sc_dev), 284 cardbus_space); 285 #endif 286 } 287 return (!found); 288 } 289 290 static void 291 parse_tuple(u_int8_t *tuple, int len, void *data) 292 { 293 struct cardbus_cis_info *cis = data; 294 char *p; 295 int i, bar_index; 296 297 switch (tuple[0]) { 298 case PCMCIA_CISTPL_MANFID: 299 if (tuple[1] != 4) { 300 DPRINTF(("%s: wrong length manufacturer id (%d)\n", 301 __func__, tuple[1])); 302 break; 303 } 304 cis->manufacturer = tuple[2] | (tuple[3] << 8); 305 cis->product = tuple[4] | (tuple[5] << 8); 306 break; 307 308 case PCMCIA_CISTPL_VERS_1: 309 memcpy(cis->cis1_info_buf, tuple + 2, tuple[1]); 310 i = 0; 311 p = cis->cis1_info_buf + 2; 312 while (i < 313 sizeof(cis->cis1_info) / sizeof(cis->cis1_info[0])) { 314 if (p >= cis->cis1_info_buf + tuple[1] || *p == '\xff') 315 break; 316 cis->cis1_info[i++] = p; 317 while (*p != '\0' && *p != '\xff') 318 p++; 319 if (*p == '\0') 320 p++; 321 } 322 break; 323 324 case PCMCIA_CISTPL_BAR: 325 if (tuple[1] != 6) { 326 DPRINTF(("%s: BAR with short length (%d)\n", 327 __func__, tuple[1])); 328 break; 329 } 330 bar_index = tuple[2] & 7; 331 if (bar_index == 0) { 332 DPRINTF(("%s: invalid ASI in BAR tuple\n", __func__)); 333 break; 334 } 335 bar_index--; 336 cis->bar[bar_index].flags = tuple[2]; 337 cis->bar[bar_index].size = 338 (tuple[4] << 0) | 339 (tuple[5] << 8) | 340 (tuple[6] << 16) | 341 (tuple[7] << 24); 342 break; 343 344 case PCMCIA_CISTPL_FUNCID: 345 cis->funcid = tuple[2]; 346 break; 347 348 case PCMCIA_CISTPL_FUNCE: 349 switch (cis->funcid) { 350 case PCMCIA_FUNCTION_SERIAL: 351 if (tuple[1] >= 2 && 352 /* XXX PCMCIA_TPLFE_TYPE_SERIAL_??? */ 353 tuple[2] == 0) { 354 cis->funce.serial.uart_type = tuple[3] & 0x1f; 355 cis->funce.serial.uart_present = 1; 356 } 357 break; 358 359 case PCMCIA_FUNCTION_NETWORK: 360 if (tuple[1] >= 8 && 361 tuple[2] == PCMCIA_TPLFE_TYPE_LAN_NID) { 362 if (tuple[3] > 363 sizeof(cis->funce.network.netid)) { 364 DPRINTF(("%s: unknown network id type " 365 "(len = %d)\n", 366 __func__, tuple[3])); 367 } else { 368 cis->funce.network.netid_present = 1; 369 memcpy(cis->funce.network.netid, 370 tuple + 4, tuple[3]); 371 } 372 } 373 break; 374 } 375 break; 376 } 377 } 378 379 /* 380 * int cardbus_attach_card(struct cardbus_softc *sc) 381 * 382 * This function attaches the card on the slot: turns on power, 383 * reads and analyses tuple, sets configuration index. 384 * 385 * This function returns the number of recognised device functions. 386 * If no functions are recognised, return 0. 387 */ 388 int 389 cardbus_attach_card(struct cardbus_softc *sc) 390 { 391 cardbus_chipset_tag_t cc; 392 cardbus_function_tag_t cf; 393 int cdstatus; 394 static int wildcard[CARDBUSCF_NLOCS] = { 395 CARDBUSCF_FUNCTION_DEFAULT 396 }; 397 398 cc = sc->sc_cc; 399 cf = sc->sc_cf; 400 401 DPRINTF(("cardbus_attach_card: cb%d start\n", 402 device_unit(sc->sc_dev))); 403 404 /* inspect initial voltage */ 405 if ((cdstatus = (*cf->cardbus_ctrl)(cc, CARDBUS_CD)) == 0) { 406 DPRINTF(("%s: no CardBus card on cb%d\n", __func__, 407 device_unit(sc->sc_dev))); 408 return (0); 409 } 410 411 device_pmf_driver_set_child_register(sc->sc_dev, cardbus_child_register); 412 cardbus_rescan(sc->sc_dev, "cardbus", wildcard); 413 return (1); /* XXX */ 414 } 415 416 int 417 cardbus_rescan(device_t self, const char *ifattr, 418 const int *locators) 419 { 420 struct cardbus_softc *sc = device_private(self); 421 cardbus_chipset_tag_t cc; 422 cardbus_function_tag_t cf; 423 pcitag_t tag; 424 pcireg_t id, class, cis_ptr; 425 pcireg_t bhlc, icr, lattimer; 426 int cdstatus; 427 int function, nfunction; 428 device_t csc; 429 cardbus_devfunc_t ct; 430 431 cc = sc->sc_cc; 432 cf = sc->sc_cf; 433 434 /* inspect initial voltage */ 435 if ((cdstatus = (*cf->cardbus_ctrl)(cc, CARDBUS_CD)) == 0) { 436 DPRINTF(("%s: no CardBus card on cb%d\n", __func__, 437 device_unit(sc->sc_dev))); 438 return (0); 439 } 440 441 /* 442 * XXX use fake function 8 to keep power on during whole 443 * configuration. 444 */ 445 enable_function(sc, cdstatus, 8); 446 function = 0; 447 448 tag = cardbus_make_tag(cc, cf, sc->sc_bus, function); 449 450 /* 451 * Wait until power comes up. Maxmum 500 ms. 452 * 453 * XXX What is this for? The bridge driver ought to have waited 454 * XXX already. 455 */ 456 { 457 int i; 458 459 for (i = 0; i < 5; ++i) { 460 id = cardbus_conf_read(cc, cf, tag, PCI_ID_REG); 461 if (id != 0xffffffff && id != 0) { 462 break; 463 } 464 if (cold) { /* before kernel thread invoked */ 465 delay(100 * 1000); 466 } else { /* thread context */ 467 if (tsleep((void *)sc, PCATCH, "cardbus", 468 hz / 10) != EWOULDBLOCK) { 469 break; 470 } 471 } 472 } 473 aprint_debug_dev(self, "id reg valid in %d iterations\n", i); 474 if (i == 5) { 475 return (EIO); 476 } 477 } 478 479 bhlc = cardbus_conf_read(cc, cf, tag, PCI_BHLC_REG); 480 DPRINTF(("%s bhlc 0x%08x -> ", device_xname(sc->sc_dev), bhlc)); 481 nfunction = PCI_HDRTYPE_MULTIFN(bhlc) ? 8 : 1; 482 483 for (function = 0; function < nfunction; function++) { 484 struct cardbus_attach_args ca; 485 int locs[CARDBUSCF_NLOCS]; 486 487 if (locators[CARDBUSCF_FUNCTION] != 488 CARDBUSCF_FUNCTION_DEFAULT && 489 locators[CARDBUSCF_FUNCTION] != function) 490 continue; 491 492 if (sc->sc_funcs[function]) 493 continue; 494 495 tag = cardbus_make_tag(cc, cf, sc->sc_bus, function); 496 497 id = cardbus_conf_read(cc, cf, tag, PCI_ID_REG); 498 class = cardbus_conf_read(cc, cf, tag, PCI_CLASS_REG); 499 cis_ptr = cardbus_conf_read(cc, cf, tag, CARDBUS_CIS_REG); 500 501 /* Invalid vendor ID value? */ 502 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) { 503 continue; 504 } 505 506 DPRINTF(("cardbus_attach_card: " 507 "Vendor 0x%x, Product 0x%x, CIS 0x%x\n", 508 PCI_VENDOR(id), PCI_PRODUCT(id), cis_ptr)); 509 510 enable_function(sc, cdstatus, function); 511 512 /* clean up every BAR */ 513 cardbus_conf_write(cc, cf, tag, PCI_BAR0, 0); 514 cardbus_conf_write(cc, cf, tag, PCI_BAR1, 0); 515 cardbus_conf_write(cc, cf, tag, PCI_BAR2, 0); 516 cardbus_conf_write(cc, cf, tag, PCI_BAR3, 0); 517 cardbus_conf_write(cc, cf, tag, PCI_BAR4, 0); 518 cardbus_conf_write(cc, cf, tag, PCI_BAR5, 0); 519 cardbus_conf_write(cc, cf, tag, CARDBUS_ROM_REG, 0); 520 521 /* set initial latency and cacheline size */ 522 bhlc = cardbus_conf_read(cc, cf, tag, PCI_BHLC_REG); 523 icr = cardbus_conf_read(cc, cf, tag, PCI_INTERRUPT_REG); 524 DPRINTF(("%s func%d icr 0x%08x bhlc 0x%08x -> ", 525 device_xname(sc->sc_dev), function, icr, bhlc)); 526 bhlc &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 527 bhlc |= (sc->sc_cacheline & PCI_CACHELINE_MASK) << 528 PCI_CACHELINE_SHIFT; 529 /* 530 * Set the initial value of the Latency Timer. 531 * 532 * While a PCI device owns the bus, its Latency 533 * Timer counts down bus cycles from its initial 534 * value to 0. Minimum Grant tells for how long 535 * the device wants to own the bus once it gets 536 * access, in units of 250ns. 537 * 538 * On a 33 MHz bus, there are 8 cycles per 250ns. 539 * So I multiply the Minimum Grant by 8 to find 540 * out the initial value of the Latency Timer. 541 * 542 * Avoid setting a Latency Timer less than 0x10, 543 * since the old code did not do that. 544 */ 545 lattimer = 546 MIN(sc->sc_max_lattimer, MAX(0x10, 8 * PCI_MIN_GNT(icr))); 547 if (PCI_LATTIMER(bhlc) < lattimer) { 548 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 549 bhlc |= (lattimer << PCI_LATTIMER_SHIFT); 550 } 551 552 cardbus_conf_write(cc, cf, tag, PCI_BHLC_REG, bhlc); 553 bhlc = cardbus_conf_read(cc, cf, tag, PCI_BHLC_REG); 554 DPRINTF(("0x%08x\n", bhlc)); 555 556 /* 557 * We need to allocate the ct here, since we might 558 * need it when reading the CIS 559 */ 560 ct = malloc(sizeof(struct cardbus_devfunc), 561 M_DEVBUF, M_WAITOK); 562 ct->ct_bhlc = bhlc; 563 ct->ct_cc = sc->sc_cc; 564 ct->ct_cf = sc->sc_cf; 565 ct->ct_bus = sc->sc_bus; 566 ct->ct_func = function; 567 ct->ct_sc = sc; 568 sc->sc_funcs[function] = ct; 569 570 memset(&ca, 0, sizeof(ca)); 571 572 ca.ca_ct = ct; 573 574 ca.ca_iot = sc->sc_iot; 575 ca.ca_memt = sc->sc_memt; 576 ca.ca_dmat = sc->sc_dmat; 577 578 ca.ca_rbus_iot = sc->sc_rbus_iot; 579 ca.ca_rbus_memt= sc->sc_rbus_memt; 580 581 ca.ca_tag = tag; 582 ca.ca_bus = sc->sc_bus; 583 ca.ca_function = function; 584 ca.ca_id = id; 585 ca.ca_class = class; 586 587 if (cis_ptr != 0) { 588 #define TUPLESIZE 2048 589 u_int8_t *tuple = malloc(TUPLESIZE, M_DEVBUF, M_WAITOK); 590 if (cardbus_read_tuples(&ca, cis_ptr, 591 tuple, TUPLESIZE)) { 592 printf("cardbus_attach_card: " 593 "failed to read CIS\n"); 594 } else { 595 #ifdef CARDBUS_DEBUG 596 decode_tuples(tuple, TUPLESIZE, 597 print_tuple, NULL); 598 #endif 599 decode_tuples(tuple, TUPLESIZE, 600 parse_tuple, &ca.ca_cis); 601 } 602 free(tuple, M_DEVBUF); 603 } 604 605 locs[CARDBUSCF_FUNCTION] = function; 606 607 if ((csc = config_found_sm_loc(sc->sc_dev, "cardbus", locs, 608 &ca, cardbusprint, config_stdsubmatch)) == NULL) { 609 /* do not match */ 610 disable_function(sc, function); 611 sc->sc_funcs[function] = NULL; 612 free(ct, M_DEVBUF); 613 } else { 614 /* found */ 615 ct->ct_device = csc; 616 } 617 } 618 /* 619 * XXX power down pseudo function 8 (this will power down the card 620 * if no functions were attached). 621 */ 622 disable_function(sc, 8); 623 624 return (0); 625 } 626 627 static int 628 cardbusprint(void *aux, const char *pnp) 629 { 630 struct cardbus_attach_args *ca = aux; 631 char devinfo[256]; 632 int i; 633 634 if (pnp) { 635 pci_devinfo(ca->ca_id, ca->ca_class, 1, devinfo, 636 sizeof(devinfo)); 637 for (i = 0; i < 4; i++) { 638 if (ca->ca_cis.cis1_info[i] == NULL) 639 break; 640 if (i) 641 aprint_normal(", "); 642 aprint_normal("%s", ca->ca_cis.cis1_info[i]); 643 } 644 aprint_verbose("%s(manufacturer 0x%x, product 0x%x)", 645 i ? " " : "", 646 ca->ca_cis.manufacturer, ca->ca_cis.product); 647 aprint_normal(" %s at %s", devinfo, pnp); 648 } 649 aprint_normal(" function %d", ca->ca_function); 650 651 return (UNCONF); 652 } 653 654 /* 655 * void cardbus_detach_card(struct cardbus_softc *sc) 656 * 657 * This function detaches the card on the slot: detach device data 658 * structure and turns off the power. 659 * 660 * This function must not be called under interrupt context. 661 */ 662 void 663 cardbus_detach_card(struct cardbus_softc *sc) 664 { 665 int f; 666 struct cardbus_devfunc *ct; 667 668 for (f = 0; f < 8; f++) { 669 ct = sc->sc_funcs[f]; 670 if (!ct) 671 continue; 672 673 DPRINTF(("%s: detaching %s\n", device_xname(sc->sc_dev), 674 device_xname(ct->ct_device))); 675 /* call device detach function */ 676 677 if (config_detach(ct->ct_device, 0) != 0) { 678 aprint_error_dev(sc->sc_dev, 679 "cannot detach dev %s, function %d\n", 680 device_xname(ct->ct_device), ct->ct_func); 681 } 682 } 683 684 sc->sc_poweron_func = 0; 685 (*sc->sc_cf->cardbus_power)(sc->sc_cc, 686 CARDBUS_VCC_0V | CARDBUS_VPP_0V); 687 } 688 689 void 690 cardbus_childdetached(device_t self, device_t child) 691 { 692 struct cardbus_softc *sc = device_private(self); 693 struct cardbus_devfunc *ct; 694 695 ct = sc->sc_funcs[device_locator(child, CARDBUSCF_FUNCTION)]; 696 KASSERT(ct->ct_device == child); 697 698 sc->sc_poweron_func &= ~(1 << ct->ct_func); 699 sc->sc_funcs[ct->ct_func] = NULL; 700 free(ct, M_DEVBUF); 701 } 702 703 void * 704 Cardbus_intr_establish(cardbus_devfunc_t ct, 705 int level, int (*func)(void *), void *arg) 706 { 707 return cardbus_intr_establish(ct->ct_cc, ct->ct_cf, level, func, 708 arg); 709 } 710 711 /* 712 * void *cardbus_intr_establish(cc, cf, irq, level, func, arg) 713 * Interrupt handler of pccard. 714 * args: 715 * cardbus_chipset_tag_t *cc 716 * int irq: 717 */ 718 void * 719 cardbus_intr_establish(cardbus_chipset_tag_t cc, cardbus_function_tag_t cf, 720 int level, int (*func)(void *), void *arg) 721 { 722 723 DPRINTF(("- cardbus_intr_establish\n")); 724 return ((*cf->cardbus_intr_establish)(cc, level, func, arg)); 725 } 726 727 void 728 Cardbus_intr_disestablish(cardbus_devfunc_t ct, void *handler) 729 { 730 cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, handler); 731 } 732 733 /* 734 * void cardbus_intr_disestablish(cc, cf, handler) 735 * Interrupt handler of pccard. 736 * args: 737 * cardbus_chipset_tag_t *cc 738 */ 739 void 740 cardbus_intr_disestablish(cardbus_chipset_tag_t cc, cardbus_function_tag_t cf, 741 void *handler) 742 { 743 744 DPRINTF(("- pccard_intr_disestablish\n")); 745 (*cf->cardbus_intr_disestablish)(cc, handler); 746 } 747 748 /* 749 * XXX this should be merged with cardbus_function_{enable,disable}, 750 * but we don't have a ct when these functions are called. 751 */ 752 static void 753 enable_function(struct cardbus_softc *sc, int cdstatus, int function) 754 { 755 756 if (sc->sc_poweron_func == 0) { 757 /* switch to 3V and/or wait for power to stabilize */ 758 if (cdstatus & CARDBUS_3V_CARD) { 759 /* 760 * sc_poweron_func must be substituted before 761 * entering sleep, in order to avoid turn on 762 * power twice. 763 */ 764 sc->sc_poweron_func |= (1 << function); 765 (*sc->sc_cf->cardbus_power)(sc->sc_cc, CARDBUS_VCC_3V); 766 } else { 767 /* No cards other than 3.3V cards. */ 768 return; 769 } 770 (*sc->sc_cf->cardbus_ctrl)(sc->sc_cc, CARDBUS_RESET); 771 } 772 sc->sc_poweron_func |= (1 << function); 773 } 774 775 static void 776 disable_function(struct cardbus_softc *sc, int function) 777 { 778 bool powerdown; 779 cardbus_devfunc_t ct; 780 device_t dv; 781 int i; 782 783 sc->sc_poweron_func &= ~(1 << function); 784 if (sc->sc_poweron_func != 0) 785 return; 786 for (i = 0; i < __arraycount(sc->sc_funcs); i++) { 787 if ((ct = sc->sc_funcs[i]) == NULL) 788 continue; 789 dv = ct->ct_device; 790 if (prop_dictionary_get_bool(device_properties(dv), 791 "pmf-powerdown", &powerdown) && !powerdown) 792 return; 793 } 794 /* power-off because no functions are enabled */ 795 (*sc->sc_cf->cardbus_power)(sc->sc_cc, CARDBUS_VCC_0V); 796 } 797 798 /* 799 * int cardbus_function_enable(struct cardbus_softc *sc, int func) 800 * 801 * This function enables a function on a card. When no power is 802 * applied on the card, power will be applied on it. 803 */ 804 int 805 cardbus_function_enable(struct cardbus_softc *sc, int func) 806 { 807 cardbus_chipset_tag_t cc = sc->sc_cc; 808 cardbus_function_tag_t cf = sc->sc_cf; 809 cardbus_devfunc_t ct; 810 pcireg_t command; 811 pcitag_t tag; 812 813 DPRINTF(("entering cardbus_function_enable... ")); 814 815 /* entering critical area */ 816 817 /* XXX: sc_vold should be used */ 818 enable_function(sc, CARDBUS_3V_CARD, func); 819 820 /* exiting critical area */ 821 822 tag = cardbus_make_tag(cc, cf, sc->sc_bus, func); 823 824 command = cardbus_conf_read(cc, cf, tag, PCI_COMMAND_STATUS_REG); 825 command |= (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_IO_ENABLE | 826 PCI_COMMAND_MASTER_ENABLE); /* XXX: good guess needed */ 827 828 cardbus_conf_write(cc, cf, tag, PCI_COMMAND_STATUS_REG, command); 829 830 if ((ct = sc->sc_funcs[func]) != NULL) 831 Cardbus_conf_write(ct, tag, PCI_BHLC_REG, ct->ct_bhlc); 832 833 DPRINTF(("%x\n", sc->sc_poweron_func)); 834 835 return (0); 836 } 837 838 /* 839 * int cardbus_function_disable(struct cardbus_softc *, int func) 840 * 841 * This function disable a function on a card. When no functions are 842 * enabled, it turns off the power. 843 */ 844 int 845 cardbus_function_disable(struct cardbus_softc *sc, int func) 846 { 847 848 DPRINTF(("entering cardbus_function_disable... ")); 849 850 disable_function(sc, func); 851 852 return (0); 853 } 854 855 /* 856 * int cardbus_get_capability(cardbus_chipset_tag_t cc, 857 * cardbus_function_tag_t cf, pcitag_t tag, int capid, int *offset, 858 * pcireg_t *value) 859 * 860 * Find the specified PCI capability. 861 */ 862 int 863 cardbus_get_capability(cardbus_chipset_tag_t cc, cardbus_function_tag_t cf, 864 pcitag_t tag, int capid, int *offset, pcireg_t *value) 865 { 866 pcireg_t reg; 867 unsigned int ofs; 868 869 reg = cardbus_conf_read(cc, cf, tag, PCI_COMMAND_STATUS_REG); 870 if (!(reg & PCI_STATUS_CAPLIST_SUPPORT)) 871 return (0); 872 873 ofs = PCI_CAPLIST_PTR(cardbus_conf_read(cc, cf, tag, 874 PCI_CAPLISTPTR_REG)); 875 while (ofs != 0) { 876 #ifdef DIAGNOSTIC 877 if ((ofs & 3) || (ofs < 0x40)) 878 panic("cardbus_get_capability"); 879 #endif 880 reg = cardbus_conf_read(cc, cf, tag, ofs); 881 if (PCI_CAPLIST_CAP(reg) == capid) { 882 if (offset) 883 *offset = ofs; 884 if (value) 885 *value = reg; 886 return (1); 887 } 888 ofs = PCI_CAPLIST_NEXT(reg); 889 } 890 891 return (0); 892 } 893 894 /* 895 * below this line, there are some functions for decoding tuples. 896 * They should go out from this file. 897 */ 898 899 static u_int8_t * 900 decode_tuple(u_int8_t *, u_int8_t *, tuple_decode_func, void *); 901 902 static int 903 decode_tuples(u_int8_t *tuple, int buflen, tuple_decode_func func, void *data) 904 { 905 u_int8_t *tp = tuple; 906 907 if (PCMCIA_CISTPL_LINKTARGET != *tuple) { 908 DPRINTF(("WRONG TUPLE: 0x%x\n", *tuple)); 909 return (0); 910 } 911 912 while ((tp = decode_tuple(tp, tuple + buflen, func, data)) != NULL) 913 ; 914 915 return (1); 916 } 917 918 static u_int8_t * 919 decode_tuple(u_int8_t *tuple, u_int8_t *end, 920 tuple_decode_func func, void *data) 921 { 922 u_int8_t type; 923 u_int8_t len; 924 925 type = tuple[0]; 926 switch (type) { 927 case PCMCIA_CISTPL_NULL: 928 case PCMCIA_CISTPL_END: 929 len = 1; 930 break; 931 default: 932 if (tuple + 2 > end) 933 return (NULL); 934 len = tuple[1] + 2; 935 break; 936 } 937 938 if (tuple + len > end) 939 return (NULL); 940 941 (*func)(tuple, len, data); 942 943 if (type == PCMCIA_CISTPL_END || tuple + len == end) 944 return (NULL); 945 946 return (tuple + len); 947 } 948 949 /* 950 * XXX: this is another reason why this code should be shared with PCI. 951 */ 952 static int 953 cardbus_get_powerstate_int(cardbus_devfunc_t ct, pcitag_t tag, 954 pcireg_t *state, int offset) 955 { 956 pcireg_t value, now; 957 cardbus_chipset_tag_t cc = ct->ct_cc; 958 cardbus_function_tag_t cf = ct->ct_cf; 959 960 value = cardbus_conf_read(cc, cf, tag, offset + PCI_PMCSR); 961 now = value & PCI_PMCSR_STATE_MASK; 962 switch (now) { 963 case PCI_PMCSR_STATE_D0: 964 case PCI_PMCSR_STATE_D1: 965 case PCI_PMCSR_STATE_D2: 966 case PCI_PMCSR_STATE_D3: 967 *state = now; 968 return 0; 969 default: 970 return EINVAL; 971 } 972 } 973 974 int 975 cardbus_get_powerstate(cardbus_devfunc_t ct, pcitag_t tag, pcireg_t *state) 976 { 977 cardbus_chipset_tag_t cc = ct->ct_cc; 978 cardbus_function_tag_t cf = ct->ct_cf; 979 int offset; 980 pcireg_t value; 981 982 if (!cardbus_get_capability(cc, cf, tag, PCI_CAP_PWRMGMT, &offset, &value)) 983 return EOPNOTSUPP; 984 985 return cardbus_get_powerstate_int(ct, tag, state, offset); 986 } 987 988 static int 989 cardbus_set_powerstate_int(cardbus_devfunc_t ct, pcitag_t tag, 990 pcireg_t state, int offset, pcireg_t cap_reg) 991 { 992 cardbus_chipset_tag_t cc = ct->ct_cc; 993 cardbus_function_tag_t cf = ct->ct_cf; 994 995 pcireg_t value, cap, now; 996 997 KASSERT((offset & 0x3) == 0); 998 999 cap = cap_reg >> PCI_PMCR_SHIFT; 1000 value = cardbus_conf_read(cc, cf, tag, offset + PCI_PMCSR); 1001 now = value & PCI_PMCSR_STATE_MASK; 1002 value &= ~PCI_PMCSR_STATE_MASK; 1003 1004 if (now == state) 1005 return 0; 1006 switch (state) { 1007 case PCI_PMCSR_STATE_D0: 1008 break; 1009 case PCI_PMCSR_STATE_D1: 1010 if (now == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D3) { 1011 printf("invalid transition from %d to D1\n", (int)now); 1012 return EINVAL; 1013 } 1014 if (!(cap & PCI_PMCR_D1SUPP)) { 1015 printf("D1 not supported\n"); 1016 return EOPNOTSUPP; 1017 } 1018 break; 1019 case PCI_PMCSR_STATE_D2: 1020 if (now == PCI_PMCSR_STATE_D3) { 1021 printf("invalid transition from %d to D2\n", (int)now); 1022 return EINVAL; 1023 } 1024 if (!(cap & PCI_PMCR_D2SUPP)) { 1025 printf("D2 not supported\n"); 1026 return EOPNOTSUPP; 1027 } 1028 break; 1029 case PCI_PMCSR_STATE_D3: 1030 break; 1031 default: 1032 return EINVAL; 1033 } 1034 value |= state; 1035 cardbus_conf_write(cc, cf, tag, offset + PCI_PMCSR, value); 1036 if (state == PCI_PMCSR_STATE_D3 || now == PCI_PMCSR_STATE_D3) 1037 DELAY(10000); 1038 else if (state == PCI_PMCSR_STATE_D2 || now == PCI_PMCSR_STATE_D2) 1039 DELAY(200); 1040 1041 return 0; 1042 } 1043 1044 int 1045 cardbus_set_powerstate(cardbus_devfunc_t ct, pcitag_t tag, pcireg_t state) 1046 { 1047 cardbus_chipset_tag_t cc = ct->ct_cc; 1048 cardbus_function_tag_t cf = ct->ct_cf; 1049 int offset; 1050 pcireg_t value; 1051 1052 if (!cardbus_get_capability(cc, cf, tag, PCI_CAP_PWRMGMT, &offset, 1053 &value)) 1054 return EOPNOTSUPP; 1055 1056 return cardbus_set_powerstate_int(ct, tag, state, offset, value); 1057 } 1058 1059 #ifdef CARDBUS_DEBUG 1060 static const char *tuple_name(int); 1061 static const char *tuple_names[] = { 1062 "TPL_NULL", "TPL_DEVICE", "Reserved", "Reserved", /* 0-3 */ 1063 "CONFIG_CB", "CFTABLE_ENTRY_CB", "Reserved", "BAR", /* 4-7 */ 1064 "Reserved", "Reserved", "Reserved", "Reserved", /* 8-B */ 1065 "Reserved", "Reserved", "Reserved", "Reserved", /* C-F */ 1066 "CHECKSUM", "LONGLINK_A", "LONGLINK_C", "LINKTARGET", /* 10-13 */ 1067 "NO_LINK", "VERS_1", "ALTSTR", "DEVICE_A", 1068 "JEDEC_C", "JEDEC_A", "CONFIG", "CFTABLE_ENTRY", 1069 "DEVICE_OC", "DEVICE_OA", "DEVICE_GEO", "DEVICE_GEO_A", 1070 "MANFID", "FUNCID", "FUNCE", "SWIL", /* 20-23 */ 1071 "Reserved", "Reserved", "Reserved", "Reserved", /* 24-27 */ 1072 "Reserved", "Reserved", "Reserved", "Reserved", /* 28-2B */ 1073 "Reserved", "Reserved", "Reserved", "Reserved", /* 2C-2F */ 1074 "Reserved", "Reserved", "Reserved", "Reserved", /* 30-33 */ 1075 "Reserved", "Reserved", "Reserved", "Reserved", /* 34-37 */ 1076 "Reserved", "Reserved", "Reserved", "Reserved", /* 38-3B */ 1077 "Reserved", "Reserved", "Reserved", "Reserved", /* 3C-3F */ 1078 "VERS_2", "FORMAT", "GEOMETRY", "BYTEORDER", 1079 "DATE", "BATTERY", "ORG" 1080 }; 1081 #define NAME_LEN(x) (sizeof x / sizeof(x[0])) 1082 1083 static const char * 1084 tuple_name(int type) 1085 { 1086 1087 if (0 <= type && type < NAME_LEN(tuple_names)) { 1088 return (tuple_names[type]); 1089 } else if (type == 0xff) { 1090 return ("END"); 1091 } else { 1092 return ("Reserved"); 1093 } 1094 } 1095 1096 static void 1097 print_tuple(u_int8_t *tuple, int len, void *data) 1098 { 1099 int i; 1100 1101 printf("tuple: %s len %d\n", tuple_name(tuple[0]), len); 1102 1103 for (i = 0; i < len; ++i) { 1104 if (i % 16 == 0) { 1105 printf(" 0x%2x:", i); 1106 } 1107 printf(" %x", tuple[i]); 1108 if (i % 16 == 15) { 1109 printf("\n"); 1110 } 1111 } 1112 if (i % 16 != 0) { 1113 printf("\n"); 1114 } 1115 } 1116 #endif 1117 1118 void 1119 cardbus_conf_capture(cardbus_chipset_tag_t cc, cardbus_function_tag_t cf, 1120 pcitag_t tag, struct cardbus_conf_state *pcs) 1121 { 1122 int off; 1123 1124 for (off = 0; off < 16; off++) 1125 pcs->reg[off] = cardbus_conf_read(cc, cf, tag, (off * 4)); 1126 } 1127 1128 void 1129 cardbus_conf_restore(cardbus_chipset_tag_t cc, cardbus_function_tag_t cf, 1130 pcitag_t tag, struct cardbus_conf_state *pcs) 1131 { 1132 int off; 1133 pcireg_t val; 1134 1135 for (off = 15; off >= 0; off--) { 1136 val = cardbus_conf_read(cc, cf, tag, (off * 4)); 1137 if (val != pcs->reg[off]) 1138 cardbus_conf_write(cc, cf,tag, (off * 4), pcs->reg[off]); 1139 } 1140 } 1141 1142 struct cardbus_child_power { 1143 struct cardbus_conf_state p_cardbusconf; 1144 cardbus_devfunc_t p_ct; 1145 pcitag_t p_tag; 1146 cardbus_chipset_tag_t p_cc; 1147 cardbus_function_tag_t p_cf; 1148 pcireg_t p_pm_cap; 1149 bool p_has_pm; 1150 int p_pm_offset; 1151 }; 1152 1153 static bool 1154 cardbus_child_suspend(device_t dv, const pmf_qual_t *qual) 1155 { 1156 struct cardbus_child_power *priv = device_pmf_bus_private(dv); 1157 1158 cardbus_conf_capture(priv->p_cc, priv->p_cf, priv->p_tag, 1159 &priv->p_cardbusconf); 1160 1161 if (priv->p_has_pm && 1162 cardbus_set_powerstate_int(priv->p_ct, priv->p_tag, 1163 PCI_PMCSR_STATE_D3, priv->p_pm_offset, priv->p_pm_cap)) { 1164 aprint_error_dev(dv, "unsupported state, continuing.\n"); 1165 return false; 1166 } 1167 1168 Cardbus_function_disable(priv->p_ct); 1169 1170 return true; 1171 } 1172 1173 static bool 1174 cardbus_child_resume(device_t dv, const pmf_qual_t *qual) 1175 { 1176 struct cardbus_child_power *priv = device_pmf_bus_private(dv); 1177 1178 Cardbus_function_enable(priv->p_ct); 1179 1180 if (priv->p_has_pm && 1181 cardbus_set_powerstate_int(priv->p_ct, priv->p_tag, 1182 PCI_PMCSR_STATE_D0, priv->p_pm_offset, priv->p_pm_cap)) { 1183 aprint_error_dev(dv, "unsupported state, continuing.\n"); 1184 return false; 1185 } 1186 1187 cardbus_conf_restore(priv->p_cc, priv->p_cf, priv->p_tag, 1188 &priv->p_cardbusconf); 1189 1190 return true; 1191 } 1192 1193 static void 1194 cardbus_child_deregister(device_t dv) 1195 { 1196 struct cardbus_child_power *priv = device_pmf_bus_private(dv); 1197 1198 free(priv, M_DEVBUF); 1199 } 1200 1201 static bool 1202 cardbus_child_register(device_t child) 1203 { 1204 device_t self = device_parent(child); 1205 struct cardbus_softc *sc = device_private(self); 1206 struct cardbus_devfunc *ct; 1207 struct cardbus_child_power *priv; 1208 int off; 1209 pcireg_t reg; 1210 1211 ct = sc->sc_funcs[device_locator(child, CARDBUSCF_FUNCTION)]; 1212 1213 priv = malloc(sizeof(*priv), M_DEVBUF, M_WAITOK); 1214 1215 priv->p_ct = ct; 1216 priv->p_cc = ct->ct_cc; 1217 priv->p_cf = ct->ct_cf; 1218 priv->p_tag = cardbus_make_tag(priv->p_cc, priv->p_cf, ct->ct_bus, 1219 ct->ct_func); 1220 1221 if (cardbus_get_capability(priv->p_cc, priv->p_cf, priv->p_tag, 1222 PCI_CAP_PWRMGMT, &off, ®)) { 1223 priv->p_has_pm = true; 1224 priv->p_pm_offset = off; 1225 priv->p_pm_cap = reg; 1226 } else { 1227 priv->p_has_pm = false; 1228 priv->p_pm_offset = -1; 1229 } 1230 1231 device_pmf_bus_register(child, priv, cardbus_child_suspend, 1232 cardbus_child_resume, 0, cardbus_child_deregister); 1233 1234 return true; 1235 } 1236
Indexes created Wed Oct 01 07:09:59 GMT 2025