if_ath_cardbus.c revision 1.29 1 1.29 drochner /* $NetBSD: if_ath_cardbus.c,v 1.29 2008/06/24 19:44:52 drochner Exp $ */
2 1.1 ichiro /*
3 1.1 ichiro * Copyright (c) 2003
4 1.1 ichiro * Ichiro FUKUHARA <ichiro (at) ichiro.org>.
5 1.1 ichiro * All rights reserved.
6 1.1 ichiro *
7 1.1 ichiro * Redistribution and use in source and binary forms, with or without
8 1.1 ichiro * modification, are permitted provided that the following conditions
9 1.1 ichiro * are met:
10 1.1 ichiro * 1. Redistributions of source code must retain the above copyright
11 1.1 ichiro * notice, this list of conditions and the following disclaimer.
12 1.1 ichiro * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 ichiro * notice, this list of conditions and the following disclaimer in the
14 1.1 ichiro * documentation and/or other materials provided with the distribution.
15 1.1 ichiro * 3. All advertising materials mentioning features or use of this software
16 1.1 ichiro * must display the following acknowledgement:
17 1.1 ichiro * This product includes software developed by Ichiro FUKUHARA.
18 1.1 ichiro * 4. The name of the company nor the name of the author may be used to
19 1.1 ichiro * endorse or promote products derived from this software without specific
20 1.1 ichiro * prior written permission.
21 1.1 ichiro *
22 1.1 ichiro * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
23 1.1 ichiro * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 1.1 ichiro * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 1.1 ichiro * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
26 1.1 ichiro * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 1.1 ichiro * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 1.1 ichiro * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 1.1 ichiro * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 1.1 ichiro * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 1.1 ichiro * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 1.1 ichiro * SUCH DAMAGE.
33 1.1 ichiro */
34 1.1 ichiro /*
35 1.1 ichiro * CardBus bus front-end for the AR5001 Wireless LAN 802.11a/b/g CardBus.
36 1.1 ichiro */
37 1.1 ichiro
38 1.1 ichiro #include <sys/cdefs.h>
39 1.29 drochner __KERNEL_RCSID(0, "$NetBSD: if_ath_cardbus.c,v 1.29 2008/06/24 19:44:52 drochner Exp $");
40 1.1 ichiro
41 1.1 ichiro #include "opt_inet.h"
42 1.1 ichiro #include "bpfilter.h"
43 1.1 ichiro
44 1.1 ichiro #include <sys/param.h>
45 1.6 perry #include <sys/systm.h>
46 1.6 perry #include <sys/mbuf.h>
47 1.1 ichiro #include <sys/malloc.h>
48 1.1 ichiro #include <sys/kernel.h>
49 1.1 ichiro #include <sys/socket.h>
50 1.1 ichiro #include <sys/ioctl.h>
51 1.1 ichiro #include <sys/errno.h>
52 1.1 ichiro #include <sys/device.h>
53 1.1 ichiro
54 1.1 ichiro #include <machine/endian.h>
55 1.6 perry
56 1.1 ichiro #include <net/if.h>
57 1.1 ichiro #include <net/if_dl.h>
58 1.1 ichiro #include <net/if_media.h>
59 1.1 ichiro #include <net/if_ether.h>
60 1.1 ichiro
61 1.7 dyoung #include <net80211/ieee80211_netbsd.h>
62 1.1 ichiro #include <net80211/ieee80211_var.h>
63 1.1 ichiro
64 1.6 perry #if NBPFILTER > 0
65 1.1 ichiro #include <net/bpf.h>
66 1.6 perry #endif
67 1.1 ichiro
68 1.1 ichiro #ifdef INET
69 1.6 perry #include <netinet/in.h>
70 1.1 ichiro #include <netinet/if_inarp.h>
71 1.1 ichiro #endif
72 1.1 ichiro
73 1.1 ichiro
74 1.19 ad #include <sys/bus.h>
75 1.19 ad #include <sys/intr.h>
76 1.1 ichiro
77 1.1 ichiro #include <dev/mii/miivar.h>
78 1.1 ichiro #include <dev/mii/mii_bitbang.h>
79 1.1 ichiro
80 1.7 dyoung #include <dev/ic/ath_netbsd.h>
81 1.1 ichiro #include <dev/ic/athvar.h>
82 1.11 gdamore #include <contrib/dev/ath/ah.h>
83 1.1 ichiro
84 1.1 ichiro #include <dev/pci/pcivar.h>
85 1.1 ichiro #include <dev/pci/pcireg.h>
86 1.1 ichiro #include <dev/pci/pcidevs.h>
87 1.1 ichiro
88 1.1 ichiro #include <dev/cardbus/cardbusvar.h>
89 1.4 mycroft #include <dev/pci/pcidevs.h>
90 1.1 ichiro
91 1.1 ichiro /*
92 1.1 ichiro * PCI configuration space registers
93 1.1 ichiro */
94 1.1 ichiro #define ATH_PCI_MMBA 0x10 /* memory mapped base */
95 1.1 ichiro
96 1.1 ichiro struct ath_cardbus_softc {
97 1.1 ichiro struct ath_softc sc_ath;
98 1.1 ichiro
99 1.1 ichiro /* CardBus-specific goo. */
100 1.1 ichiro void *sc_ih; /* interrupt handle */
101 1.1 ichiro cardbus_devfunc_t sc_ct; /* our CardBus devfuncs */
102 1.1 ichiro cardbustag_t sc_tag; /* our CardBus tag */
103 1.1 ichiro bus_size_t sc_mapsize; /* the size of mapped bus space region */
104 1.1 ichiro
105 1.1 ichiro pcireg_t sc_bar_val; /* value of the BAR */
106 1.1 ichiro
107 1.29 drochner cardbus_intr_line_t sc_intrline; /* interrupt line */
108 1.13 gdamore bus_space_tag_t sc_iot;
109 1.13 gdamore bus_space_handle_t sc_ioh;
110 1.1 ichiro };
111 1.1 ichiro
112 1.26 dyoung int ath_cardbus_match(device_t, struct cfdata *, void *);
113 1.26 dyoung void ath_cardbus_attach(device_t, device_t, void *);
114 1.26 dyoung int ath_cardbus_detach(device_t, int);
115 1.1 ichiro
116 1.1 ichiro CFATTACH_DECL(ath_cardbus, sizeof(struct ath_cardbus_softc),
117 1.26 dyoung ath_cardbus_match, ath_cardbus_attach, ath_cardbus_detach, NULL);
118 1.1 ichiro
119 1.1 ichiro void ath_cardbus_setup(struct ath_cardbus_softc *);
120 1.1 ichiro
121 1.26 dyoung static bool
122 1.26 dyoung ath_cardbus_suspend(device_t self PMF_FN_ARGS)
123 1.26 dyoung {
124 1.26 dyoung struct ath_cardbus_softc *csc = device_private(self);
125 1.26 dyoung
126 1.26 dyoung ath_suspend(&csc->sc_ath);
127 1.26 dyoung if (csc->sc_ih != NULL) {
128 1.26 dyoung cardbus_intr_disestablish(csc->sc_ct->ct_cc, csc->sc_ct->ct_cf,
129 1.26 dyoung csc->sc_ih);
130 1.26 dyoung csc->sc_ih = NULL;
131 1.26 dyoung }
132 1.26 dyoung return true;
133 1.26 dyoung }
134 1.21 jmcneill
135 1.21 jmcneill static bool
136 1.26 dyoung ath_cardbus_resume(device_t self PMF_FN_ARGS)
137 1.21 jmcneill {
138 1.26 dyoung struct ath_cardbus_softc *csc = device_private(self);
139 1.21 jmcneill
140 1.26 dyoung csc->sc_ih = cardbus_intr_establish(csc->sc_ct->ct_cc,
141 1.26 dyoung csc->sc_ct->ct_cf, csc->sc_intrline, IPL_NET, ath_intr,
142 1.26 dyoung &csc->sc_ath);
143 1.26 dyoung
144 1.26 dyoung if (csc->sc_ih == NULL) {
145 1.26 dyoung aprint_error_dev(self,
146 1.29 drochner "unable to establish interrupt\n");
147 1.26 dyoung return false;
148 1.26 dyoung }
149 1.26 dyoung
150 1.26 dyoung return ath_resume(&csc->sc_ath);
151 1.21 jmcneill }
152 1.1 ichiro
153 1.1 ichiro int
154 1.26 dyoung ath_cardbus_match(device_t parent, struct cfdata *match, void *aux)
155 1.1 ichiro {
156 1.1 ichiro struct cardbus_attach_args *ca = aux;
157 1.26 dyoung const char *devname;
158 1.1 ichiro
159 1.26 dyoung devname = ath_hal_probe(PCI_VENDOR(ca->ca_id), PCI_PRODUCT(ca->ca_id));
160 1.1 ichiro
161 1.1 ichiro if (devname)
162 1.26 dyoung return 1;
163 1.1 ichiro
164 1.26 dyoung return 0;
165 1.1 ichiro }
166 1.1 ichiro
167 1.1 ichiro void
168 1.26 dyoung ath_cardbus_attach(device_t parent, device_t self, void *aux)
169 1.1 ichiro {
170 1.10 thorpej struct ath_cardbus_softc *csc = device_private(self);
171 1.1 ichiro struct ath_softc *sc = &csc->sc_ath;
172 1.1 ichiro struct cardbus_attach_args *ca = aux;
173 1.1 ichiro cardbus_devfunc_t ct = ca->ca_ct;
174 1.1 ichiro bus_addr_t adr;
175 1.1 ichiro
176 1.1 ichiro sc->sc_dmat = ca->ca_dmat;
177 1.1 ichiro csc->sc_ct = ct;
178 1.1 ichiro csc->sc_tag = ca->ca_tag;
179 1.1 ichiro
180 1.26 dyoung aprint_normal("\n");
181 1.15 seanb
182 1.1 ichiro /*
183 1.1 ichiro * Map the device.
184 1.1 ichiro */
185 1.26 dyoung if (Cardbus_mapreg_map(ct, ATH_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0,
186 1.13 gdamore &csc->sc_iot, &csc->sc_ioh, &adr, &csc->sc_mapsize) == 0) {
187 1.1 ichiro #if rbus
188 1.1 ichiro #else
189 1.1 ichiro (*ct->ct_cf->cardbus_mem_open)(cc, 0, adr, adr+csc->sc_mapsize);
190 1.1 ichiro #endif
191 1.26 dyoung csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM;
192 1.26 dyoung } else {
193 1.26 dyoung aprint_error_dev(self, "unable to map device registers\n");
194 1.1 ichiro return;
195 1.1 ichiro }
196 1.1 ichiro
197 1.13 gdamore sc->sc_st = HALTAG(csc->sc_iot);
198 1.13 gdamore sc->sc_sh = HALHANDLE(csc->sc_ioh);
199 1.13 gdamore
200 1.1 ichiro /*
201 1.1 ichiro * Set up the PCI configuration registers.
202 1.1 ichiro */
203 1.1 ichiro ath_cardbus_setup(csc);
204 1.1 ichiro
205 1.1 ichiro /* Remember which interrupt line. */
206 1.1 ichiro csc->sc_intrline = ca->ca_intrline;
207 1.1 ichiro
208 1.24 dyoung ATH_LOCK_INIT(sc);
209 1.24 dyoung
210 1.1 ichiro /*
211 1.1 ichiro * Finish off the attach.
212 1.1 ichiro */
213 1.26 dyoung if (ath_attach(PCI_PRODUCT(ca->ca_id), sc) != 0)
214 1.26 dyoung return;
215 1.26 dyoung
216 1.26 dyoung if (!pmf_device_register(self, ath_cardbus_suspend, ath_cardbus_resume))
217 1.26 dyoung aprint_error_dev(self, "couldn't establish power handler\n");
218 1.26 dyoung else {
219 1.26 dyoung pmf_class_network_register(self, &sc->sc_if);
220 1.26 dyoung pmf_device_suspend_self(self);
221 1.26 dyoung }
222 1.1 ichiro }
223 1.1 ichiro
224 1.1 ichiro int
225 1.26 dyoung ath_cardbus_detach(device_t self, int flags)
226 1.1 ichiro {
227 1.10 thorpej struct ath_cardbus_softc *csc = device_private(self);
228 1.1 ichiro struct ath_softc *sc = &csc->sc_ath;
229 1.1 ichiro struct cardbus_devfunc *ct = csc->sc_ct;
230 1.1 ichiro int rv;
231 1.1 ichiro
232 1.1 ichiro #if defined(DIAGNOSTIC)
233 1.1 ichiro if (ct == NULL)
234 1.27 cegger panic("%s: data structure lacks", device_xname(&sc->sc_dev));
235 1.1 ichiro #endif
236 1.1 ichiro
237 1.1 ichiro rv = ath_detach(sc);
238 1.1 ichiro if (rv)
239 1.1 ichiro return (rv);
240 1.1 ichiro
241 1.21 jmcneill pmf_device_deregister(self);
242 1.21 jmcneill
243 1.1 ichiro /*
244 1.1 ichiro * Unhook the interrupt handler.
245 1.1 ichiro */
246 1.25 dyoung if (csc->sc_ih != NULL) {
247 1.1 ichiro cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih);
248 1.1 ichiro csc->sc_ih = NULL;
249 1.25 dyoung }
250 1.1 ichiro
251 1.1 ichiro /*
252 1.1 ichiro * Release bus space and close window.
253 1.1 ichiro */
254 1.14 nakayama Cardbus_mapreg_unmap(ct, ATH_PCI_MMBA, csc->sc_iot, csc->sc_ioh,
255 1.14 nakayama csc->sc_mapsize);
256 1.1 ichiro
257 1.24 dyoung ATH_LOCK_DESTROY(sc);
258 1.24 dyoung
259 1.1 ichiro return (0);
260 1.1 ichiro }
261 1.1 ichiro
262 1.1 ichiro void
263 1.1 ichiro ath_cardbus_setup(struct ath_cardbus_softc *csc)
264 1.1 ichiro {
265 1.1 ichiro cardbus_devfunc_t ct = csc->sc_ct;
266 1.1 ichiro cardbus_chipset_tag_t cc = ct->ct_cc;
267 1.1 ichiro cardbus_function_tag_t cf = ct->ct_cf;
268 1.26 dyoung int rc;
269 1.1 ichiro pcireg_t reg;
270 1.1 ichiro
271 1.26 dyoung if ((rc = cardbus_set_powerstate(ct, csc->sc_tag, PCI_PWR_D0)) != 0)
272 1.26 dyoung aprint_debug("%s: cardbus_set_powerstate %d\n", __func__, rc);
273 1.1 ichiro
274 1.3 mycroft /* Program the BAR. */
275 1.26 dyoung cardbus_conf_write(cc, cf, csc->sc_tag, ATH_PCI_MMBA, csc->sc_bar_val);
276 1.1 ichiro
277 1.1 ichiro /* Enable the appropriate bits in the PCI CSR. */
278 1.1 ichiro reg = cardbus_conf_read(cc, cf, csc->sc_tag,
279 1.26 dyoung PCI_COMMAND_STATUS_REG);
280 1.26 dyoung reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
281 1.26 dyoung cardbus_conf_write(cc, cf, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);
282 1.1 ichiro }
283