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if_ath_cardbus.c revision 1.18.22.2 
      1 /*	$NetBSD: if_ath_cardbus.c,v 1.18.22.2 2007/08/23 16:19:46 joerg Exp $ */
      2 /*
      3  * Copyright (c) 2003
      4  *	Ichiro FUKUHARA <ichiro (at) ichiro.org>.
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  * 3. All advertising materials mentioning features or use of this software
     16  *    must display the following acknowledgement:
     17  *	This product includes software developed by Ichiro FUKUHARA.
     18  * 4. The name of the company nor the name of the author may be used to
     19  *    endorse or promote products derived from this software without specific
     20  *    prior written permission.
     21  *
     22  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
     23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     25  * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
     26  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     32  * SUCH DAMAGE.
     33  */
     34 /*
     35  * CardBus bus front-end for the AR5001 Wireless LAN 802.11a/b/g CardBus.
     36  */
     37 
     38 #include <sys/cdefs.h>
     39 __KERNEL_RCSID(0, "$NetBSD: if_ath_cardbus.c,v 1.18.22.2 2007/08/23 16:19:46 joerg Exp $");
     40 
     41 #include "opt_inet.h"
     42 #include "bpfilter.h"
     43 
     44 #include <sys/param.h>
     45 #include <sys/systm.h>
     46 #include <sys/mbuf.h>
     47 #include <sys/malloc.h>
     48 #include <sys/kernel.h>
     49 #include <sys/socket.h>
     50 #include <sys/ioctl.h>
     51 #include <sys/errno.h>
     52 #include <sys/device.h>
     53 
     54 #include <machine/endian.h>
     55 
     56 #include <net/if.h>
     57 #include <net/if_dl.h>
     58 #include <net/if_media.h>
     59 #include <net/if_ether.h>
     60 
     61 #include <net80211/ieee80211_netbsd.h>
     62 #include <net80211/ieee80211_var.h>
     63 
     64 #if NBPFILTER > 0
     65 #include <net/bpf.h>
     66 #endif
     67 
     68 #ifdef INET
     69 #include <netinet/in.h>
     70 #include <netinet/if_inarp.h>
     71 #endif
     72 
     73 
     74 #include <machine/bus.h>
     75 #include <machine/intr.h>
     76 
     77 #include <dev/mii/miivar.h>
     78 #include <dev/mii/mii_bitbang.h>
     79 
     80 #include <dev/ic/ath_netbsd.h>
     81 #include <dev/ic/athvar.h>
     82 #include <contrib/dev/ath/ah.h>
     83 
     84 #include <dev/pci/pcivar.h>
     85 #include <dev/pci/pcireg.h>
     86 #include <dev/pci/pcidevs.h>
     87 
     88 #include <dev/cardbus/cardbusvar.h>
     89 #include <dev/pci/pcidevs.h>
     90 
     91 /*
     92  * PCI configuration space registers
     93  */
     94 #define	ATH_PCI_MMBA		0x10	/* memory mapped base */
     95 
     96 struct ath_cardbus_softc {
     97 	struct ath_softc	sc_ath;
     98 
     99 	/* CardBus-specific goo. */
    100 	void	*sc_ih;			/* interrupt handle */
    101 	cardbus_devfunc_t sc_ct;	/* our CardBus devfuncs */
    102 	cardbustag_t sc_tag;		/* our CardBus tag */
    103 	bus_size_t sc_mapsize;		/* the size of mapped bus space region */
    104 	struct cardbus_conf_state	sc_cardbusconf;
    105 
    106 	pcireg_t sc_bar_val;		/* value of the BAR */
    107 
    108 	int	sc_intrline;		/* interrupt line */
    109 	bus_space_tag_t sc_iot;
    110 	bus_space_handle_t sc_ioh;
    111 };
    112 
    113 int	ath_cardbus_match(struct device *, struct cfdata *, void *);
    114 void	ath_cardbus_attach(struct device *, struct device *, void *);
    115 int	ath_cardbus_detach(struct device *, int);
    116 
    117 CFATTACH_DECL(ath_cardbus, sizeof(struct ath_cardbus_softc),
    118     ath_cardbus_match, ath_cardbus_attach, ath_cardbus_detach, ath_activate);
    119 
    120 void	ath_cardbus_setup(struct ath_cardbus_softc *);
    121 
    122 int	ath_cardbus_enable(struct ath_softc *);
    123 void	ath_cardbus_disable(struct ath_softc *);
    124 
    125 static pnp_status_t ath_cardbus_power(device_t, pnp_request_t, void *);
    126 
    127 int
    128 ath_cardbus_match(struct device *parent, struct cfdata *match,
    129     void *aux)
    130 {
    131 	struct cardbus_attach_args *ca = aux;
    132 	const char* devname;
    133 
    134 	devname = ath_hal_probe(PCI_VENDOR(ca->ca_id),
    135 				PCI_PRODUCT(ca->ca_id));
    136 
    137 	if (devname)
    138 		return (1);
    139 
    140 	return (0);
    141 }
    142 
    143 void
    144 ath_cardbus_attach(struct device *parent, struct device *self,
    145     void *aux)
    146 {
    147 	struct ath_cardbus_softc *csc = device_private(self);
    148 	struct ath_softc *sc = &csc->sc_ath;
    149 	struct cardbus_attach_args *ca = aux;
    150 	cardbus_devfunc_t ct = ca->ca_ct;
    151 	bus_addr_t adr;
    152 
    153 	sc->sc_dmat = ca->ca_dmat;
    154 	csc->sc_ct = ct;
    155 	csc->sc_tag = ca->ca_tag;
    156 
    157 	printf("\n");
    158 
    159 	/*
    160 	 * Power management hooks.
    161 	 */
    162 	sc->sc_enable = ath_cardbus_enable;
    163 	sc->sc_disable = ath_cardbus_disable;
    164 
    165 	/*
    166 	 * Map the device.
    167 	 */
    168 	if (Cardbus_mapreg_map(ct, ATH_PCI_MMBA, CARDBUS_MAPREG_TYPE_MEM, 0,
    169 	    &csc->sc_iot, &csc->sc_ioh, &adr, &csc->sc_mapsize) == 0) {
    170 #if rbus
    171 #else
    172 		(*ct->ct_cf->cardbus_mem_open)(cc, 0, adr, adr+csc->sc_mapsize);
    173 #endif
    174 		csc->sc_bar_val = adr | CARDBUS_MAPREG_TYPE_MEM;
    175 	}
    176 
    177 	else {
    178 		printf("%s: unable to map device registers\n",
    179 		    sc->sc_dev.dv_xname);
    180 		return;
    181 	}
    182 
    183 	sc->sc_st = HALTAG(csc->sc_iot);
    184 	sc->sc_sh = HALHANDLE(csc->sc_ioh);
    185 
    186 	/*
    187 	 * Set up the PCI configuration registers.
    188 	 */
    189 	ath_cardbus_setup(csc);
    190 
    191 	/* Remember which interrupt line. */
    192 	csc->sc_intrline = ca->ca_intrline;
    193 
    194 	if (pnp_register(self, ath_cardbus_power) != PNP_STATUS_SUCCESS)
    195 		aprint_error("%s: couldn't establish power handler\n",
    196 		    device_xname(self));
    197 
    198 	/*
    199 	 * Finish off the attach.
    200 	 */
    201 	ath_attach(PCI_PRODUCT(ca->ca_id), sc);
    202 }
    203 
    204 int
    205 ath_cardbus_detach(struct device *self, int flags)
    206 {
    207 	struct ath_cardbus_softc *csc = device_private(self);
    208 	struct ath_softc *sc = &csc->sc_ath;
    209 	struct cardbus_devfunc *ct = csc->sc_ct;
    210 	int rv;
    211 
    212 #if defined(DIAGNOSTIC)
    213 	if (ct == NULL)
    214 		panic("%s: data structure lacks", sc->sc_dev.dv_xname);
    215 #endif
    216 
    217 	rv = ath_detach(sc);
    218 	if (rv)
    219 		return (rv);
    220 
    221 	pnp_deregister(self);
    222 
    223 	/*
    224 	 * Unhook the interrupt handler.
    225 	 */
    226 	if (csc->sc_ih != NULL)
    227 		cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih);
    228 		csc->sc_ih = NULL;
    229 
    230 	/*
    231 	 * Release bus space and close window.
    232 	 */
    233 	Cardbus_mapreg_unmap(ct, ATH_PCI_MMBA, csc->sc_iot, csc->sc_ioh,
    234 	    csc->sc_mapsize);
    235 
    236 	return (0);
    237 }
    238 
    239 int
    240 ath_cardbus_enable(struct ath_softc *sc)
    241 {
    242 	struct ath_cardbus_softc *csc = (void *) sc;
    243 	cardbus_devfunc_t ct = csc->sc_ct;
    244 	cardbus_chipset_tag_t cc = ct->ct_cc;
    245 	cardbus_function_tag_t cf = ct->ct_cf;
    246 
    247 	/*
    248 	 * Power on the socket.
    249 	 */
    250 	Cardbus_function_enable(ct);
    251 
    252 	/*
    253 	 * Set up the PCI configuration registers.
    254 	 */
    255 	ath_cardbus_setup(csc);
    256 
    257 	/*
    258 	 * Map and establish the interrupt.
    259 	 */
    260 	csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET,
    261 	    ath_intr, sc);
    262 	if (csc->sc_ih == NULL) {
    263 		printf("%s: unable to establish interrupt at %d\n",
    264 		    sc->sc_dev.dv_xname, csc->sc_intrline);
    265 		Cardbus_function_disable(csc->sc_ct);
    266 		return (1);
    267 	}
    268 	printf("%s: interrupting at %d\n", sc->sc_dev.dv_xname,
    269 		csc->sc_intrline);
    270 
    271 	return (0);
    272 }
    273 
    274 void
    275 ath_cardbus_disable(struct ath_softc *sc)
    276 {
    277 	struct ath_cardbus_softc *csc = (void *) sc;
    278 	cardbus_devfunc_t ct = csc->sc_ct;
    279 	cardbus_chipset_tag_t cc = ct->ct_cc;
    280 	cardbus_function_tag_t cf = ct->ct_cf;
    281 
    282 	/* Unhook the interrupt handler. */
    283 	cardbus_intr_disestablish(cc, cf, csc->sc_ih);
    284 	csc->sc_ih = NULL;
    285 
    286 }
    287 
    288 void
    289 ath_cardbus_setup(struct ath_cardbus_softc *csc)
    290 {
    291 	cardbus_devfunc_t ct = csc->sc_ct;
    292 	cardbus_chipset_tag_t cc = ct->ct_cc;
    293 	cardbus_function_tag_t cf = ct->ct_cf;
    294 	pcireg_t reg;
    295 
    296 	(void)cardbus_set_powerstate(ct, csc->sc_tag, PCI_PWR_D0);
    297 
    298 	/* Program the BAR. */
    299 	cardbus_conf_write(cc, cf, csc->sc_tag, ATH_PCI_MMBA,
    300 	    csc->sc_bar_val);
    301 
    302 	/* Make sure the right access type is on the CardBus bridge. */
    303 	(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE);
    304 	(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
    305 
    306 	/* Enable the appropriate bits in the PCI CSR. */
    307 	reg = cardbus_conf_read(cc, cf, csc->sc_tag,
    308 	    CARDBUS_COMMAND_STATUS_REG);
    309 	reg |= CARDBUS_COMMAND_MASTER_ENABLE | CARDBUS_COMMAND_MEM_ENABLE;
    310 	cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_COMMAND_STATUS_REG,
    311 	    reg);
    312 
    313 	/*
    314 	 * Make sure the latency timer is set to some reasonable
    315 	 * value.
    316 	 */
    317 	reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG);
    318 	if (CARDBUS_LATTIMER(reg) < 0x20) {
    319 		reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT);
    320 		reg |= (0x20 << CARDBUS_LATTIMER_SHIFT);
    321 		cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG, reg);
    322 	}
    323 }
    324 
    325 static pnp_status_t
    326 ath_cardbus_power(device_t dv, pnp_request_t req, void *opaque)
    327 {
    328 	struct ath_cardbus_softc *csc = (struct ath_cardbus_softc *)dv;
    329 	cardbus_devfunc_t ct = csc->sc_ct;
    330 	cardbus_chipset_tag_t cc = ct->ct_cc;
    331 	cardbus_function_tag_t cf = ct->ct_cf;
    332 
    333 	return cardbus_net_generic_power(dv, req, opaque, cc, cf, csc->sc_tag,
    334 	    &csc->sc_cardbusconf, &csc->sc_ath.sc_if);
    335 }
    336