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if_ath_cardbus.c revision 1.18.22.3 
      1 /*	$NetBSD: if_ath_cardbus.c,v 1.18.22.3 2007/10/04 21:43:30 joerg Exp $ */
      2 /*
      3  * Copyright (c) 2003
      4  *	Ichiro FUKUHARA <ichiro (at) ichiro.org>.
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  * 3. All advertising materials mentioning features or use of this software
     16  *    must display the following acknowledgement:
     17  *	This product includes software developed by Ichiro FUKUHARA.
     18  * 4. The name of the company nor the name of the author may be used to
     19  *    endorse or promote products derived from this software without specific
     20  *    prior written permission.
     21  *
     22  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
     23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     25  * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
     26  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     32  * SUCH DAMAGE.
     33  */
     34 /*
     35  * CardBus bus front-end for the AR5001 Wireless LAN 802.11a/b/g CardBus.
     36  */
     37 
     38 #include <sys/cdefs.h>
     39 __KERNEL_RCSID(0, "$NetBSD: if_ath_cardbus.c,v 1.18.22.3 2007/10/04 21:43:30 joerg Exp $");
     40 
     41 #include "opt_inet.h"
     42 #include "bpfilter.h"
     43 
     44 #include <sys/param.h>
     45 #include <sys/systm.h>
     46 #include <sys/mbuf.h>
     47 #include <sys/malloc.h>
     48 #include <sys/kernel.h>
     49 #include <sys/socket.h>
     50 #include <sys/ioctl.h>
     51 #include <sys/errno.h>
     52 #include <sys/device.h>
     53 
     54 #include <machine/endian.h>
     55 
     56 #include <net/if.h>
     57 #include <net/if_dl.h>
     58 #include <net/if_media.h>
     59 #include <net/if_ether.h>
     60 
     61 #include <net80211/ieee80211_netbsd.h>
     62 #include <net80211/ieee80211_var.h>
     63 
     64 #if NBPFILTER > 0
     65 #include <net/bpf.h>
     66 #endif
     67 
     68 #ifdef INET
     69 #include <netinet/in.h>
     70 #include <netinet/if_inarp.h>
     71 #endif
     72 
     73 
     74 #include <machine/bus.h>
     75 #include <machine/intr.h>
     76 
     77 #include <dev/mii/miivar.h>
     78 #include <dev/mii/mii_bitbang.h>
     79 
     80 #include <dev/ic/ath_netbsd.h>
     81 #include <dev/ic/athvar.h>
     82 #include <contrib/dev/ath/ah.h>
     83 
     84 #include <dev/pci/pcivar.h>
     85 #include <dev/pci/pcireg.h>
     86 #include <dev/pci/pcidevs.h>
     87 
     88 #include <dev/cardbus/cardbusvar.h>
     89 #include <dev/pci/pcidevs.h>
     90 
     91 /*
     92  * PCI configuration space registers
     93  */
     94 #define	ATH_PCI_MMBA		0x10	/* memory mapped base */
     95 
     96 struct ath_cardbus_softc {
     97 	struct ath_softc	sc_ath;
     98 
     99 	/* CardBus-specific goo. */
    100 	void	*sc_ih;			/* interrupt handle */
    101 	cardbus_devfunc_t sc_ct;	/* our CardBus devfuncs */
    102 	cardbustag_t sc_tag;		/* our CardBus tag */
    103 	bus_size_t sc_mapsize;		/* the size of mapped bus space region */
    104 
    105 	pcireg_t sc_bar_val;		/* value of the BAR */
    106 
    107 	int	sc_intrline;		/* interrupt line */
    108 	bus_space_tag_t sc_iot;
    109 	bus_space_handle_t sc_ioh;
    110 };
    111 
    112 int	ath_cardbus_match(struct device *, struct cfdata *, void *);
    113 void	ath_cardbus_attach(struct device *, struct device *, void *);
    114 int	ath_cardbus_detach(struct device *, int);
    115 
    116 CFATTACH_DECL(ath_cardbus, sizeof(struct ath_cardbus_softc),
    117     ath_cardbus_match, ath_cardbus_attach, ath_cardbus_detach, ath_activate);
    118 
    119 void	ath_cardbus_setup(struct ath_cardbus_softc *);
    120 
    121 int	ath_cardbus_enable(struct ath_softc *);
    122 void	ath_cardbus_disable(struct ath_softc *);
    123 
    124 static void
    125 ath_cardbus_resume(device_t dv)
    126 {
    127 	struct ath_cardbus_softc *csc = device_private(dv);
    128 	cardbus_devfunc_t ct = csc->sc_ct;
    129 	cardbus_chipset_tag_t cc = ct->ct_cc;
    130 	cardbus_function_tag_t cf = ct->ct_cf;
    131 
    132 	cardbus_disable_retry(cc, cf, csc->sc_tag);
    133 	ath_resume(&csc->sc_ath);
    134 }
    135 
    136 int
    137 ath_cardbus_match(struct device *parent, struct cfdata *match,
    138     void *aux)
    139 {
    140 	struct cardbus_attach_args *ca = aux;
    141 	const char* devname;
    142 
    143 	devname = ath_hal_probe(PCI_VENDOR(ca->ca_id),
    144 				PCI_PRODUCT(ca->ca_id));
    145 
    146 	if (devname)
    147 		return (1);
    148 
    149 	return (0);
    150 }
    151 
    152 void
    153 ath_cardbus_attach(struct device *parent, struct device *self,
    154     void *aux)
    155 {
    156 	struct ath_cardbus_softc *csc = device_private(self);
    157 	struct ath_softc *sc = &csc->sc_ath;
    158 	struct cardbus_attach_args *ca = aux;
    159 	cardbus_devfunc_t ct = ca->ca_ct;
    160 	bus_addr_t adr;
    161 	pnp_status_t pnp_status;
    162 
    163 	sc->sc_dmat = ca->ca_dmat;
    164 	csc->sc_ct = ct;
    165 	csc->sc_tag = ca->ca_tag;
    166 
    167 	printf("\n");
    168 
    169 	/*
    170 	 * Power management hooks.
    171 	 */
    172 	sc->sc_enable = ath_cardbus_enable;
    173 	sc->sc_disable = ath_cardbus_disable;
    174 
    175 	/*
    176 	 * Map the device.
    177 	 */
    178 	if (Cardbus_mapreg_map(ct, ATH_PCI_MMBA, CARDBUS_MAPREG_TYPE_MEM, 0,
    179 	    &csc->sc_iot, &csc->sc_ioh, &adr, &csc->sc_mapsize) == 0) {
    180 #if rbus
    181 #else
    182 		(*ct->ct_cf->cardbus_mem_open)(cc, 0, adr, adr+csc->sc_mapsize);
    183 #endif
    184 		csc->sc_bar_val = adr | CARDBUS_MAPREG_TYPE_MEM;
    185 	}
    186 
    187 	else {
    188 		printf("%s: unable to map device registers\n",
    189 		    sc->sc_dev.dv_xname);
    190 		return;
    191 	}
    192 
    193 	sc->sc_st = HALTAG(csc->sc_iot);
    194 	sc->sc_sh = HALHANDLE(csc->sc_ioh);
    195 
    196 	/*
    197 	 * Set up the PCI configuration registers.
    198 	 */
    199 	ath_cardbus_setup(csc);
    200 
    201 	/* Remember which interrupt line. */
    202 	csc->sc_intrline = ca->ca_intrline;
    203 
    204 	pnp_status = cardbus_net_generic_power_register(self,
    205     	    ct->ct_cc, ct->ct_cf, ca->ca_tag, &sc->sc_if, NULL,
    206 	    ath_cardbus_resume);
    207 	if (pnp_status != PNP_STATUS_SUCCESS) {
    208 		aprint_error("%s: couldn't establish power handler\n",
    209 		    device_xname(self));
    210 	}
    211 
    212 	/*
    213 	 * Finish off the attach.
    214 	 */
    215 	ath_attach(PCI_PRODUCT(ca->ca_id), sc);
    216 }
    217 
    218 int
    219 ath_cardbus_detach(struct device *self, int flags)
    220 {
    221 	struct ath_cardbus_softc *csc = device_private(self);
    222 	struct ath_softc *sc = &csc->sc_ath;
    223 	struct cardbus_devfunc *ct = csc->sc_ct;
    224 	int rv;
    225 
    226 #if defined(DIAGNOSTIC)
    227 	if (ct == NULL)
    228 		panic("%s: data structure lacks", sc->sc_dev.dv_xname);
    229 #endif
    230 
    231 	rv = ath_detach(sc);
    232 	if (rv)
    233 		return (rv);
    234 
    235 	cardbus_net_generic_power_deregister(self);
    236 
    237 	/*
    238 	 * Unhook the interrupt handler.
    239 	 */
    240 	if (csc->sc_ih != NULL)
    241 		cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih);
    242 		csc->sc_ih = NULL;
    243 
    244 	/*
    245 	 * Release bus space and close window.
    246 	 */
    247 	Cardbus_mapreg_unmap(ct, ATH_PCI_MMBA, csc->sc_iot, csc->sc_ioh,
    248 	    csc->sc_mapsize);
    249 
    250 	return (0);
    251 }
    252 
    253 int
    254 ath_cardbus_enable(struct ath_softc *sc)
    255 {
    256 	struct ath_cardbus_softc *csc = (void *) sc;
    257 	cardbus_devfunc_t ct = csc->sc_ct;
    258 	cardbus_chipset_tag_t cc = ct->ct_cc;
    259 	cardbus_function_tag_t cf = ct->ct_cf;
    260 
    261 	/*
    262 	 * Power on the socket.
    263 	 */
    264 	Cardbus_function_enable(ct);
    265 
    266 	/*
    267 	 * Set up the PCI configuration registers.
    268 	 */
    269 	ath_cardbus_setup(csc);
    270 
    271 	/*
    272 	 * Map and establish the interrupt.
    273 	 */
    274 	csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET,
    275 	    ath_intr, sc);
    276 	if (csc->sc_ih == NULL) {
    277 		printf("%s: unable to establish interrupt at %d\n",
    278 		    sc->sc_dev.dv_xname, csc->sc_intrline);
    279 		Cardbus_function_disable(csc->sc_ct);
    280 		return (1);
    281 	}
    282 	printf("%s: interrupting at %d\n", sc->sc_dev.dv_xname,
    283 		csc->sc_intrline);
    284 
    285 	return (0);
    286 }
    287 
    288 void
    289 ath_cardbus_disable(struct ath_softc *sc)
    290 {
    291 	struct ath_cardbus_softc *csc = (void *) sc;
    292 	cardbus_devfunc_t ct = csc->sc_ct;
    293 	cardbus_chipset_tag_t cc = ct->ct_cc;
    294 	cardbus_function_tag_t cf = ct->ct_cf;
    295 
    296 	/* Unhook the interrupt handler. */
    297 	cardbus_intr_disestablish(cc, cf, csc->sc_ih);
    298 	csc->sc_ih = NULL;
    299 
    300 }
    301 
    302 void
    303 ath_cardbus_setup(struct ath_cardbus_softc *csc)
    304 {
    305 	cardbus_devfunc_t ct = csc->sc_ct;
    306 	cardbus_chipset_tag_t cc = ct->ct_cc;
    307 	cardbus_function_tag_t cf = ct->ct_cf;
    308 	pcireg_t reg;
    309 
    310 	(void)cardbus_set_powerstate(ct, csc->sc_tag, PCI_PWR_D0);
    311 
    312 	/* Program the BAR. */
    313 	cardbus_conf_write(cc, cf, csc->sc_tag, ATH_PCI_MMBA,
    314 	    csc->sc_bar_val);
    315 
    316 	/* Make sure the right access type is on the CardBus bridge. */
    317 	(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE);
    318 	(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
    319 
    320 	/* Enable the appropriate bits in the PCI CSR. */
    321 	reg = cardbus_conf_read(cc, cf, csc->sc_tag,
    322 	    CARDBUS_COMMAND_STATUS_REG);
    323 	reg |= CARDBUS_COMMAND_MASTER_ENABLE | CARDBUS_COMMAND_MEM_ENABLE;
    324 	cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_COMMAND_STATUS_REG,
    325 	    reg);
    326 
    327 	/*
    328 	 * Make sure the latency timer is set to some reasonable
    329 	 * value.
    330 	 */
    331 	reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG);
    332 	if (CARDBUS_LATTIMER(reg) < 0x20) {
    333 		reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT);
    334 		reg |= (0x20 << CARDBUS_LATTIMER_SHIFT);
    335 		cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG, reg);
    336 	}
    337 }
    338