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if_ath_cardbus.c revision 1.18.22.5 
      1 /*	$NetBSD: if_ath_cardbus.c,v 1.18.22.5 2007/11/06 14:27:15 joerg Exp $ */
      2 /*
      3  * Copyright (c) 2003
      4  *	Ichiro FUKUHARA <ichiro (at) ichiro.org>.
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  * 3. All advertising materials mentioning features or use of this software
     16  *    must display the following acknowledgement:
     17  *	This product includes software developed by Ichiro FUKUHARA.
     18  * 4. The name of the company nor the name of the author may be used to
     19  *    endorse or promote products derived from this software without specific
     20  *    prior written permission.
     21  *
     22  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
     23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     25  * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
     26  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     32  * SUCH DAMAGE.
     33  */
     34 /*
     35  * CardBus bus front-end for the AR5001 Wireless LAN 802.11a/b/g CardBus.
     36  */
     37 
     38 #include <sys/cdefs.h>
     39 __KERNEL_RCSID(0, "$NetBSD: if_ath_cardbus.c,v 1.18.22.5 2007/11/06 14:27:15 joerg Exp $");
     40 
     41 #include "opt_inet.h"
     42 #include "bpfilter.h"
     43 
     44 #include <sys/param.h>
     45 #include <sys/systm.h>
     46 #include <sys/mbuf.h>
     47 #include <sys/malloc.h>
     48 #include <sys/kernel.h>
     49 #include <sys/socket.h>
     50 #include <sys/ioctl.h>
     51 #include <sys/errno.h>
     52 #include <sys/device.h>
     53 
     54 #include <machine/endian.h>
     55 
     56 #include <net/if.h>
     57 #include <net/if_dl.h>
     58 #include <net/if_media.h>
     59 #include <net/if_ether.h>
     60 
     61 #include <net80211/ieee80211_netbsd.h>
     62 #include <net80211/ieee80211_var.h>
     63 
     64 #if NBPFILTER > 0
     65 #include <net/bpf.h>
     66 #endif
     67 
     68 #ifdef INET
     69 #include <netinet/in.h>
     70 #include <netinet/if_inarp.h>
     71 #endif
     72 
     73 
     74 #include <sys/bus.h>
     75 #include <sys/intr.h>
     76 
     77 #include <dev/mii/miivar.h>
     78 #include <dev/mii/mii_bitbang.h>
     79 
     80 #include <dev/ic/ath_netbsd.h>
     81 #include <dev/ic/athvar.h>
     82 #include <contrib/dev/ath/ah.h>
     83 
     84 #include <dev/pci/pcivar.h>
     85 #include <dev/pci/pcireg.h>
     86 #include <dev/pci/pcidevs.h>
     87 
     88 #include <dev/cardbus/cardbusvar.h>
     89 #include <dev/pci/pcidevs.h>
     90 
     91 /*
     92  * PCI configuration space registers
     93  */
     94 #define	ATH_PCI_MMBA		0x10	/* memory mapped base */
     95 
     96 struct ath_cardbus_softc {
     97 	struct ath_softc	sc_ath;
     98 
     99 	/* CardBus-specific goo. */
    100 	void	*sc_ih;			/* interrupt handle */
    101 	cardbus_devfunc_t sc_ct;	/* our CardBus devfuncs */
    102 	cardbustag_t sc_tag;		/* our CardBus tag */
    103 	bus_size_t sc_mapsize;		/* the size of mapped bus space region */
    104 
    105 	pcireg_t sc_bar_val;		/* value of the BAR */
    106 
    107 	int	sc_intrline;		/* interrupt line */
    108 	bus_space_tag_t sc_iot;
    109 	bus_space_handle_t sc_ioh;
    110 };
    111 
    112 int	ath_cardbus_match(struct device *, struct cfdata *, void *);
    113 void	ath_cardbus_attach(struct device *, struct device *, void *);
    114 int	ath_cardbus_detach(struct device *, int);
    115 
    116 CFATTACH_DECL(ath_cardbus, sizeof(struct ath_cardbus_softc),
    117     ath_cardbus_match, ath_cardbus_attach, ath_cardbus_detach, ath_activate);
    118 
    119 void	ath_cardbus_setup(struct ath_cardbus_softc *);
    120 
    121 int	ath_cardbus_enable(struct ath_softc *);
    122 void	ath_cardbus_disable(struct ath_softc *);
    123 
    124 static bool
    125 ath_cardbus_resume(device_t dv)
    126 {
    127 	struct ath_cardbus_softc *csc = device_private(dv);
    128 	cardbus_devfunc_t ct = csc->sc_ct;
    129 	cardbus_chipset_tag_t cc = ct->ct_cc;
    130 	cardbus_function_tag_t cf = ct->ct_cf;
    131 
    132 	cardbus_disable_retry(cc, cf, csc->sc_tag);
    133 	ath_resume(&csc->sc_ath);
    134 
    135 	return true;
    136 }
    137 
    138 int
    139 ath_cardbus_match(struct device *parent, struct cfdata *match,
    140     void *aux)
    141 {
    142 	struct cardbus_attach_args *ca = aux;
    143 	const char* devname;
    144 
    145 	devname = ath_hal_probe(PCI_VENDOR(ca->ca_id),
    146 				PCI_PRODUCT(ca->ca_id));
    147 
    148 	if (devname)
    149 		return (1);
    150 
    151 	return (0);
    152 }
    153 
    154 void
    155 ath_cardbus_attach(struct device *parent, struct device *self,
    156     void *aux)
    157 {
    158 	struct ath_cardbus_softc *csc = device_private(self);
    159 	struct ath_softc *sc = &csc->sc_ath;
    160 	struct cardbus_attach_args *ca = aux;
    161 	cardbus_devfunc_t ct = ca->ca_ct;
    162 	bus_addr_t adr;
    163 
    164 	sc->sc_dmat = ca->ca_dmat;
    165 	csc->sc_ct = ct;
    166 	csc->sc_tag = ca->ca_tag;
    167 
    168 	printf("\n");
    169 
    170 	/*
    171 	 * Power management hooks.
    172 	 */
    173 	sc->sc_enable = ath_cardbus_enable;
    174 	sc->sc_disable = ath_cardbus_disable;
    175 
    176 	/*
    177 	 * Map the device.
    178 	 */
    179 	if (Cardbus_mapreg_map(ct, ATH_PCI_MMBA, CARDBUS_MAPREG_TYPE_MEM, 0,
    180 	    &csc->sc_iot, &csc->sc_ioh, &adr, &csc->sc_mapsize) == 0) {
    181 #if rbus
    182 #else
    183 		(*ct->ct_cf->cardbus_mem_open)(cc, 0, adr, adr+csc->sc_mapsize);
    184 #endif
    185 		csc->sc_bar_val = adr | CARDBUS_MAPREG_TYPE_MEM;
    186 	}
    187 
    188 	else {
    189 		printf("%s: unable to map device registers\n",
    190 		    sc->sc_dev.dv_xname);
    191 		return;
    192 	}
    193 
    194 	sc->sc_st = HALTAG(csc->sc_iot);
    195 	sc->sc_sh = HALHANDLE(csc->sc_ioh);
    196 
    197 	/*
    198 	 * Set up the PCI configuration registers.
    199 	 */
    200 	ath_cardbus_setup(csc);
    201 
    202 	/* Remember which interrupt line. */
    203 	csc->sc_intrline = ca->ca_intrline;
    204 
    205 	if (!pnp_device_register(self, NULL, ath_cardbus_resume))
    206 		aprint_error_dev(self, "couldn't establish power handler\n");
    207 	else
    208 		pnp_class_network_register(self, &sc->sc_if);
    209 
    210 	/*
    211 	 * Finish off the attach.
    212 	 */
    213 	ath_attach(PCI_PRODUCT(ca->ca_id), sc);
    214 }
    215 
    216 int
    217 ath_cardbus_detach(struct device *self, int flags)
    218 {
    219 	struct ath_cardbus_softc *csc = device_private(self);
    220 	struct ath_softc *sc = &csc->sc_ath;
    221 	struct cardbus_devfunc *ct = csc->sc_ct;
    222 	int rv;
    223 
    224 #if defined(DIAGNOSTIC)
    225 	if (ct == NULL)
    226 		panic("%s: data structure lacks", sc->sc_dev.dv_xname);
    227 #endif
    228 
    229 	rv = ath_detach(sc);
    230 	if (rv)
    231 		return (rv);
    232 
    233 	pnp_device_deregister(self);
    234 
    235 	/*
    236 	 * Unhook the interrupt handler.
    237 	 */
    238 	if (csc->sc_ih != NULL)
    239 		cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih);
    240 		csc->sc_ih = NULL;
    241 
    242 	/*
    243 	 * Release bus space and close window.
    244 	 */
    245 	Cardbus_mapreg_unmap(ct, ATH_PCI_MMBA, csc->sc_iot, csc->sc_ioh,
    246 	    csc->sc_mapsize);
    247 
    248 	return (0);
    249 }
    250 
    251 int
    252 ath_cardbus_enable(struct ath_softc *sc)
    253 {
    254 	struct ath_cardbus_softc *csc = (void *) sc;
    255 	cardbus_devfunc_t ct = csc->sc_ct;
    256 	cardbus_chipset_tag_t cc = ct->ct_cc;
    257 	cardbus_function_tag_t cf = ct->ct_cf;
    258 
    259 	/*
    260 	 * Power on the socket.
    261 	 */
    262 	Cardbus_function_enable(ct);
    263 
    264 	/*
    265 	 * Set up the PCI configuration registers.
    266 	 */
    267 	ath_cardbus_setup(csc);
    268 
    269 	/*
    270 	 * Map and establish the interrupt.
    271 	 */
    272 	csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET,
    273 	    ath_intr, sc);
    274 	if (csc->sc_ih == NULL) {
    275 		printf("%s: unable to establish interrupt at %d\n",
    276 		    sc->sc_dev.dv_xname, csc->sc_intrline);
    277 		Cardbus_function_disable(csc->sc_ct);
    278 		return (1);
    279 	}
    280 	printf("%s: interrupting at %d\n", sc->sc_dev.dv_xname,
    281 		csc->sc_intrline);
    282 
    283 	return (0);
    284 }
    285 
    286 void
    287 ath_cardbus_disable(struct ath_softc *sc)
    288 {
    289 	struct ath_cardbus_softc *csc = (void *) sc;
    290 	cardbus_devfunc_t ct = csc->sc_ct;
    291 	cardbus_chipset_tag_t cc = ct->ct_cc;
    292 	cardbus_function_tag_t cf = ct->ct_cf;
    293 
    294 	/* Unhook the interrupt handler. */
    295 	cardbus_intr_disestablish(cc, cf, csc->sc_ih);
    296 	csc->sc_ih = NULL;
    297 
    298 }
    299 
    300 void
    301 ath_cardbus_setup(struct ath_cardbus_softc *csc)
    302 {
    303 	cardbus_devfunc_t ct = csc->sc_ct;
    304 	cardbus_chipset_tag_t cc = ct->ct_cc;
    305 	cardbus_function_tag_t cf = ct->ct_cf;
    306 	pcireg_t reg;
    307 
    308 	(void)cardbus_set_powerstate(ct, csc->sc_tag, PCI_PWR_D0);
    309 
    310 	/* Program the BAR. */
    311 	cardbus_conf_write(cc, cf, csc->sc_tag, ATH_PCI_MMBA,
    312 	    csc->sc_bar_val);
    313 
    314 	/* Make sure the right access type is on the CardBus bridge. */
    315 	(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE);
    316 	(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
    317 
    318 	/* Enable the appropriate bits in the PCI CSR. */
    319 	reg = cardbus_conf_read(cc, cf, csc->sc_tag,
    320 	    CARDBUS_COMMAND_STATUS_REG);
    321 	reg |= CARDBUS_COMMAND_MASTER_ENABLE | CARDBUS_COMMAND_MEM_ENABLE;
    322 	cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_COMMAND_STATUS_REG,
    323 	    reg);
    324 
    325 	/*
    326 	 * Make sure the latency timer is set to some reasonable
    327 	 * value.
    328 	 */
    329 	reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG);
    330 	if (CARDBUS_LATTIMER(reg) < 0x20) {
    331 		reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT);
    332 		reg |= (0x20 << CARDBUS_LATTIMER_SHIFT);
    333 		cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG, reg);
    334 	}
    335 }
    336