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if_ath_cardbus.c revision 1.25.6.4 
      1 /*	$NetBSD: if_ath_cardbus.c,v 1.25.6.4 2008/09/28 10:40:20 mjf Exp $ */
      2 /*
      3  * Copyright (c) 2003
      4  *	Ichiro FUKUHARA <ichiro (at) ichiro.org>.
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  * 3. All advertising materials mentioning features or use of this software
     16  *    must display the following acknowledgement:
     17  *	This product includes software developed by Ichiro FUKUHARA.
     18  * 4. The name of the company nor the name of the author may be used to
     19  *    endorse or promote products derived from this software without specific
     20  *    prior written permission.
     21  *
     22  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
     23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     25  * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
     26  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     32  * SUCH DAMAGE.
     33  */
     34 /*
     35  * CardBus bus front-end for the AR5001 Wireless LAN 802.11a/b/g CardBus.
     36  */
     37 
     38 #include <sys/cdefs.h>
     39 __KERNEL_RCSID(0, "$NetBSD: if_ath_cardbus.c,v 1.25.6.4 2008/09/28 10:40:20 mjf Exp $");
     40 
     41 #include "opt_inet.h"
     42 #include "bpfilter.h"
     43 
     44 #include <sys/param.h>
     45 #include <sys/systm.h>
     46 #include <sys/mbuf.h>
     47 #include <sys/malloc.h>
     48 #include <sys/kernel.h>
     49 #include <sys/socket.h>
     50 #include <sys/ioctl.h>
     51 #include <sys/errno.h>
     52 #include <sys/device.h>
     53 
     54 #include <machine/endian.h>
     55 
     56 #include <net/if.h>
     57 #include <net/if_dl.h>
     58 #include <net/if_media.h>
     59 #include <net/if_ether.h>
     60 
     61 #include <net80211/ieee80211_netbsd.h>
     62 #include <net80211/ieee80211_var.h>
     63 
     64 #if NBPFILTER > 0
     65 #include <net/bpf.h>
     66 #endif
     67 
     68 #ifdef INET
     69 #include <netinet/in.h>
     70 #include <netinet/if_inarp.h>
     71 #endif
     72 
     73 
     74 #include <sys/bus.h>
     75 #include <sys/intr.h>
     76 
     77 #include <dev/mii/miivar.h>
     78 #include <dev/mii/mii_bitbang.h>
     79 
     80 #include <dev/ic/ath_netbsd.h>
     81 #include <dev/ic/athvar.h>
     82 #include <contrib/dev/ath/ah.h>
     83 
     84 #include <dev/pci/pcivar.h>
     85 #include <dev/pci/pcireg.h>
     86 #include <dev/pci/pcidevs.h>
     87 
     88 #include <dev/cardbus/cardbusvar.h>
     89 #include <dev/pci/pcidevs.h>
     90 
     91 /*
     92  * PCI configuration space registers
     93  */
     94 #define	ATH_PCI_MMBA		0x10	/* memory mapped base */
     95 
     96 struct ath_cardbus_softc {
     97 	struct ath_softc	sc_ath;
     98 
     99 	/* CardBus-specific goo. */
    100 	void	*sc_ih;			/* interrupt handle */
    101 	cardbus_devfunc_t sc_ct;	/* our CardBus devfuncs */
    102 	cardbustag_t sc_tag;		/* our CardBus tag */
    103 	bus_size_t sc_mapsize;		/* the size of mapped bus space region */
    104 
    105 	pcireg_t sc_bar_val;		/* value of the BAR */
    106 
    107 	cardbus_intr_line_t sc_intrline; /* interrupt line */
    108 	bus_space_tag_t sc_iot;
    109 	bus_space_handle_t sc_ioh;
    110 };
    111 
    112 int	ath_cardbus_match(device_t, cfdata_t, void *);
    113 void	ath_cardbus_attach(device_t, device_t, void *);
    114 int	ath_cardbus_detach(device_t, int);
    115 
    116 CFATTACH_DECL_NEW(ath_cardbus, sizeof(struct ath_cardbus_softc),
    117     ath_cardbus_match, ath_cardbus_attach, ath_cardbus_detach, NULL);
    118 
    119 void	ath_cardbus_setup(struct ath_cardbus_softc *);
    120 
    121 static bool
    122 ath_cardbus_suspend(device_t self PMF_FN_ARGS)
    123 {
    124 	struct ath_cardbus_softc *csc = device_private(self);
    125 
    126 	ath_suspend(&csc->sc_ath);
    127 	if (csc->sc_ih != NULL) {
    128 		cardbus_intr_disestablish(csc->sc_ct->ct_cc, csc->sc_ct->ct_cf,
    129 		    csc->sc_ih);
    130 		csc->sc_ih = NULL;
    131 	}
    132 	return true;
    133 }
    134 
    135 static bool
    136 ath_cardbus_resume(device_t self PMF_FN_ARGS)
    137 {
    138 	struct ath_cardbus_softc *csc = device_private(self);
    139 
    140 	csc->sc_ih = cardbus_intr_establish(csc->sc_ct->ct_cc,
    141 	    csc->sc_ct->ct_cf, csc->sc_intrline, IPL_NET, ath_intr,
    142 	    &csc->sc_ath);
    143 
    144 	if (csc->sc_ih == NULL) {
    145 		aprint_error_dev(self,
    146 		    "unable to establish interrupt\n");
    147 		return false;
    148 	}
    149 
    150 	return ath_resume(&csc->sc_ath);
    151 }
    152 
    153 int
    154 ath_cardbus_match(device_t parent, struct cfdata *match, void *aux)
    155 {
    156 	struct cardbus_attach_args *ca = aux;
    157 	const char *devname;
    158 
    159 	devname = ath_hal_probe(PCI_VENDOR(ca->ca_id), PCI_PRODUCT(ca->ca_id));
    160 
    161 	if (devname)
    162 		return 1;
    163 
    164 	return 0;
    165 }
    166 
    167 void
    168 ath_cardbus_attach(device_t parent, device_t self, void *aux)
    169 {
    170 	struct ath_cardbus_softc *csc = device_private(self);
    171 	struct ath_softc *sc = &csc->sc_ath;
    172 	struct cardbus_attach_args *ca = aux;
    173 	cardbus_devfunc_t ct = ca->ca_ct;
    174 	bus_addr_t adr;
    175 
    176 	sc->sc_dev = self;
    177 	sc->sc_dmat = ca->ca_dmat;
    178 	csc->sc_ct = ct;
    179 	csc->sc_tag = ca->ca_tag;
    180 
    181 	aprint_normal("\n");
    182 
    183 	/*
    184 	 * Map the device.
    185 	 */
    186 	if (Cardbus_mapreg_map(ct, ATH_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0,
    187 	    &csc->sc_iot, &csc->sc_ioh, &adr, &csc->sc_mapsize) == 0) {
    188 #if rbus
    189 #else
    190 		(*ct->ct_cf->cardbus_mem_open)(cc, 0, adr, adr+csc->sc_mapsize);
    191 #endif
    192 		csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM;
    193 	} else {
    194 		aprint_error_dev(self, "unable to map device registers\n");
    195 		return;
    196 	}
    197 
    198 	sc->sc_st = HALTAG(csc->sc_iot);
    199 	sc->sc_sh = HALHANDLE(csc->sc_ioh);
    200 
    201 	/*
    202 	 * Set up the PCI configuration registers.
    203 	 */
    204 	ath_cardbus_setup(csc);
    205 
    206 	/* Remember which interrupt line. */
    207 	csc->sc_intrline = ca->ca_intrline;
    208 
    209 	ATH_LOCK_INIT(sc);
    210 
    211 	/*
    212 	 * Finish off the attach.
    213 	 */
    214 	if (ath_attach(PCI_PRODUCT(ca->ca_id), sc) != 0)
    215 		return;
    216 
    217 	if (!pmf_device_register(self, ath_cardbus_suspend, ath_cardbus_resume))
    218 		aprint_error_dev(self, "couldn't establish power handler\n");
    219 	else {
    220 		pmf_class_network_register(self, &sc->sc_if);
    221 		pmf_device_suspend_self(self);
    222 	}
    223 }
    224 
    225 int
    226 ath_cardbus_detach(device_t self, int flags)
    227 {
    228 	struct ath_cardbus_softc *csc = device_private(self);
    229 	struct ath_softc *sc = &csc->sc_ath;
    230 	struct cardbus_devfunc *ct = csc->sc_ct;
    231 	int rv;
    232 
    233 #if defined(DIAGNOSTIC)
    234 	if (ct == NULL)
    235 		panic("%s: data structure lacks", device_xname(sc->sc_dev));
    236 #endif
    237 
    238 	rv = ath_detach(sc);
    239 	if (rv)
    240 		return (rv);
    241 
    242 	pmf_device_deregister(self);
    243 
    244 	/*
    245 	 * Unhook the interrupt handler.
    246 	 */
    247 	if (csc->sc_ih != NULL) {
    248 		cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih);
    249 		csc->sc_ih = NULL;
    250 	}
    251 
    252 	/*
    253 	 * Release bus space and close window.
    254 	 */
    255 	Cardbus_mapreg_unmap(ct, ATH_PCI_MMBA, csc->sc_iot, csc->sc_ioh,
    256 	    csc->sc_mapsize);
    257 
    258 	ATH_LOCK_DESTROY(sc);
    259 
    260 	return (0);
    261 }
    262 
    263 void
    264 ath_cardbus_setup(struct ath_cardbus_softc *csc)
    265 {
    266 	cardbus_devfunc_t ct = csc->sc_ct;
    267 	cardbus_chipset_tag_t cc = ct->ct_cc;
    268 	cardbus_function_tag_t cf = ct->ct_cf;
    269 	int rc;
    270 	pcireg_t reg;
    271 
    272 	if ((rc = cardbus_set_powerstate(ct, csc->sc_tag, PCI_PWR_D0)) != 0)
    273 		aprint_debug("%s: cardbus_set_powerstate %d\n", __func__, rc);
    274 
    275 	/* Program the BAR. */
    276 	cardbus_conf_write(cc, cf, csc->sc_tag, ATH_PCI_MMBA, csc->sc_bar_val);
    277 
    278 	/* Enable the appropriate bits in the PCI CSR. */
    279 	reg = cardbus_conf_read(cc, cf, csc->sc_tag,
    280 	    PCI_COMMAND_STATUS_REG);
    281 	reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
    282 	cardbus_conf_write(cc, cf, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);
    283 }
    284