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if_ath_cardbus.c revision 1.37 
      1 /*	$NetBSD: if_ath_cardbus.c,v 1.37 2010/01/08 19:47:42 dyoung Exp $ */
      2 /*
      3  * Copyright (c) 2003
      4  *	Ichiro FUKUHARA <ichiro (at) ichiro.org>.
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
     20  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 /*
     29  * CardBus bus front-end for the AR5001 Wireless LAN 802.11a/b/g CardBus.
     30  */
     31 
     32 #include <sys/cdefs.h>
     33 __KERNEL_RCSID(0, "$NetBSD: if_ath_cardbus.c,v 1.37 2010/01/08 19:47:42 dyoung Exp $");
     34 
     35 #include "opt_inet.h"
     36 #include "bpfilter.h"
     37 
     38 #include <sys/param.h>
     39 #include <sys/systm.h>
     40 #include <sys/mbuf.h>
     41 #include <sys/malloc.h>
     42 #include <sys/kernel.h>
     43 #include <sys/socket.h>
     44 #include <sys/ioctl.h>
     45 #include <sys/errno.h>
     46 #include <sys/device.h>
     47 
     48 #include <machine/endian.h>
     49 
     50 #include <net/if.h>
     51 #include <net/if_dl.h>
     52 #include <net/if_media.h>
     53 #include <net/if_ether.h>
     54 
     55 #include <net80211/ieee80211_netbsd.h>
     56 #include <net80211/ieee80211_var.h>
     57 
     58 #if NBPFILTER > 0
     59 #include <net/bpf.h>
     60 #endif
     61 
     62 #ifdef INET
     63 #include <netinet/in.h>
     64 #include <netinet/if_inarp.h>
     65 #endif
     66 
     67 
     68 #include <sys/bus.h>
     69 #include <sys/intr.h>
     70 
     71 #include <dev/mii/miivar.h>
     72 #include <dev/mii/mii_bitbang.h>
     73 
     74 #include <dev/ic/ath_netbsd.h>
     75 #include <dev/ic/athvar.h>
     76 
     77 #include <external/isc/atheros_hal/dist/ah.h>
     78 
     79 #include <dev/pci/pcivar.h>
     80 #include <dev/pci/pcireg.h>
     81 #include <dev/pci/pcidevs.h>
     82 
     83 #include <dev/cardbus/cardbusvar.h>
     84 #include <dev/pci/pcidevs.h>
     85 
     86 /*
     87  * PCI configuration space registers
     88  */
     89 #define	ATH_PCI_MMBA		0x10	/* memory mapped base */
     90 
     91 struct ath_cardbus_softc {
     92 	struct ath_softc	sc_ath;
     93 
     94 	/* CardBus-specific goo. */
     95 	void	*sc_ih;			/* interrupt handle */
     96 	cardbus_devfunc_t sc_ct;	/* our CardBus devfuncs */
     97 	cardbustag_t sc_tag;		/* our CardBus tag */
     98 	bus_size_t sc_mapsize;		/* the size of mapped bus space region */
     99 
    100 	pcireg_t sc_bar_val;		/* value of the BAR */
    101 
    102 	cardbus_intr_line_t sc_intrline; /* interrupt line */
    103 	bus_space_tag_t sc_iot;
    104 	bus_space_handle_t sc_ioh;
    105 };
    106 
    107 int	ath_cardbus_match(device_t, cfdata_t, void *);
    108 void	ath_cardbus_attach(device_t, device_t, void *);
    109 int	ath_cardbus_detach(device_t, int);
    110 
    111 CFATTACH_DECL_NEW(ath_cardbus, sizeof(struct ath_cardbus_softc),
    112     ath_cardbus_match, ath_cardbus_attach, ath_cardbus_detach, NULL);
    113 
    114 void	ath_cardbus_setup(struct ath_cardbus_softc *);
    115 
    116 static bool
    117 ath_cardbus_suspend(device_t self, pmf_qual_t qual)
    118 {
    119 	struct ath_cardbus_softc *csc = device_private(self);
    120 
    121 	ath_suspend(&csc->sc_ath);
    122 	if (csc->sc_ih != NULL) {
    123 		cardbus_intr_disestablish(csc->sc_ct->ct_cc, csc->sc_ct->ct_cf,
    124 		    csc->sc_ih);
    125 		csc->sc_ih = NULL;
    126 	}
    127 	return true;
    128 }
    129 
    130 static bool
    131 ath_cardbus_resume(device_t self, pmf_qual_t qual)
    132 {
    133 	struct ath_cardbus_softc *csc = device_private(self);
    134 
    135 	csc->sc_ih = cardbus_intr_establish(csc->sc_ct->ct_cc,
    136 	    csc->sc_ct->ct_cf, csc->sc_intrline, IPL_NET, ath_intr,
    137 	    &csc->sc_ath);
    138 
    139 	if (csc->sc_ih == NULL) {
    140 		aprint_error_dev(self,
    141 		    "unable to establish interrupt\n");
    142 		return false;
    143 	}
    144 
    145 	return ath_resume(&csc->sc_ath);
    146 }
    147 
    148 int
    149 ath_cardbus_match(device_t parent, cfdata_t match, void *aux)
    150 {
    151 	struct cardbus_attach_args *ca = aux;
    152 	const char *devname;
    153 
    154 	devname = ath_hal_probe(PCI_VENDOR(ca->ca_id), PCI_PRODUCT(ca->ca_id));
    155 
    156 	if (devname)
    157 		return 1;
    158 
    159 	return 0;
    160 }
    161 
    162 void
    163 ath_cardbus_attach(device_t parent, device_t self, void *aux)
    164 {
    165 	struct ath_cardbus_softc *csc = device_private(self);
    166 	struct ath_softc *sc = &csc->sc_ath;
    167 	struct cardbus_attach_args *ca = aux;
    168 	cardbus_devfunc_t ct = ca->ca_ct;
    169 	bus_addr_t adr;
    170 
    171 	sc->sc_dev = self;
    172 	sc->sc_dmat = ca->ca_dmat;
    173 	csc->sc_ct = ct;
    174 	csc->sc_tag = ca->ca_tag;
    175 
    176 	aprint_normal("\n");
    177 
    178 	/*
    179 	 * Map the device.
    180 	 */
    181 	if (Cardbus_mapreg_map(ct, ATH_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0,
    182 	    &csc->sc_iot, &csc->sc_ioh, &adr, &csc->sc_mapsize) == 0) {
    183 #if rbus
    184 #else
    185 		(*ct->ct_cf->cardbus_mem_open)(cc, 0, adr, adr+csc->sc_mapsize);
    186 #endif
    187 		csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM;
    188 	} else {
    189 		aprint_error_dev(self, "unable to map device registers\n");
    190 		return;
    191 	}
    192 
    193 	sc->sc_st = HALTAG(csc->sc_iot);
    194 	sc->sc_sh = HALHANDLE(csc->sc_ioh);
    195 
    196 	/*
    197 	 * Set up the PCI configuration registers.
    198 	 */
    199 	ath_cardbus_setup(csc);
    200 
    201 	/* Remember which interrupt line. */
    202 	csc->sc_intrline = ca->ca_intrline;
    203 
    204 	ATH_LOCK_INIT(sc);
    205 
    206 	/*
    207 	 * Finish off the attach.
    208 	 */
    209 	if (ath_attach(PCI_PRODUCT(ca->ca_id), sc) != 0)
    210 		return;
    211 
    212 	if (pmf_device_register(self,
    213 	    ath_cardbus_suspend, ath_cardbus_resume)) {
    214 		pmf_class_network_register(self, &sc->sc_if);
    215 		pmf_device_suspend(self, &sc->sc_qual);
    216 	} else
    217 		aprint_error_dev(self, "couldn't establish power handler\n");
    218 }
    219 
    220 int
    221 ath_cardbus_detach(device_t self, int flags)
    222 {
    223 	struct ath_cardbus_softc *csc = device_private(self);
    224 	struct ath_softc *sc = &csc->sc_ath;
    225 	struct cardbus_devfunc *ct = csc->sc_ct;
    226 	int rv;
    227 
    228 #if defined(DIAGNOSTIC)
    229 	if (ct == NULL)
    230 		panic("%s: data structure lacks", device_xname(sc->sc_dev));
    231 #endif
    232 
    233 	rv = ath_detach(sc);
    234 	if (rv)
    235 		return (rv);
    236 
    237 	pmf_device_deregister(self);
    238 
    239 	/*
    240 	 * Unhook the interrupt handler.
    241 	 */
    242 	if (csc->sc_ih != NULL) {
    243 		cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih);
    244 		csc->sc_ih = NULL;
    245 	}
    246 
    247 	/*
    248 	 * Release bus space and close window.
    249 	 */
    250 	Cardbus_mapreg_unmap(ct, ATH_PCI_MMBA, csc->sc_iot, csc->sc_ioh,
    251 	    csc->sc_mapsize);
    252 
    253 	ATH_LOCK_DESTROY(sc);
    254 
    255 	return (0);
    256 }
    257 
    258 void
    259 ath_cardbus_setup(struct ath_cardbus_softc *csc)
    260 {
    261 	cardbus_devfunc_t ct = csc->sc_ct;
    262 	cardbus_chipset_tag_t cc = ct->ct_cc;
    263 	cardbus_function_tag_t cf = ct->ct_cf;
    264 	int rc;
    265 	pcireg_t reg;
    266 
    267 	if ((rc = cardbus_set_powerstate(ct, csc->sc_tag, PCI_PWR_D0)) != 0)
    268 		aprint_debug("%s: cardbus_set_powerstate %d\n", __func__, rc);
    269 
    270 	/* Program the BAR. */
    271 	cardbus_conf_write(cc, cf, csc->sc_tag, ATH_PCI_MMBA, csc->sc_bar_val);
    272 
    273 	/* Enable the appropriate bits in the PCI CSR. */
    274 	reg = cardbus_conf_read(cc, cf, csc->sc_tag,
    275 	    PCI_COMMAND_STATUS_REG);
    276 	reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
    277 	cardbus_conf_write(cc, cf, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);
    278 }
    279