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if_ath_cardbus.c revision 1.38 
      1 /*	$NetBSD: if_ath_cardbus.c,v 1.38 2010/01/18 18:52:35 pooka Exp $ */
      2 /*
      3  * Copyright (c) 2003
      4  *	Ichiro FUKUHARA <ichiro (at) ichiro.org>.
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
     20  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 /*
     29  * CardBus bus front-end for the AR5001 Wireless LAN 802.11a/b/g CardBus.
     30  */
     31 
     32 #include <sys/cdefs.h>
     33 __KERNEL_RCSID(0, "$NetBSD: if_ath_cardbus.c,v 1.38 2010/01/18 18:52:35 pooka Exp $");
     34 
     35 #include "opt_inet.h"
     36 
     37 #include <sys/param.h>
     38 #include <sys/systm.h>
     39 #include <sys/mbuf.h>
     40 #include <sys/malloc.h>
     41 #include <sys/kernel.h>
     42 #include <sys/socket.h>
     43 #include <sys/ioctl.h>
     44 #include <sys/errno.h>
     45 #include <sys/device.h>
     46 
     47 #include <machine/endian.h>
     48 
     49 #include <net/if.h>
     50 #include <net/if_dl.h>
     51 #include <net/if_media.h>
     52 #include <net/if_ether.h>
     53 
     54 #include <net80211/ieee80211_netbsd.h>
     55 #include <net80211/ieee80211_var.h>
     56 
     57 #ifdef INET
     58 #include <netinet/in.h>
     59 #include <netinet/if_inarp.h>
     60 #endif
     61 
     62 
     63 #include <sys/bus.h>
     64 #include <sys/intr.h>
     65 
     66 #include <dev/mii/miivar.h>
     67 #include <dev/mii/mii_bitbang.h>
     68 
     69 #include <dev/ic/ath_netbsd.h>
     70 #include <dev/ic/athvar.h>
     71 
     72 #include <external/isc/atheros_hal/dist/ah.h>
     73 
     74 #include <dev/pci/pcivar.h>
     75 #include <dev/pci/pcireg.h>
     76 #include <dev/pci/pcidevs.h>
     77 
     78 #include <dev/cardbus/cardbusvar.h>
     79 #include <dev/pci/pcidevs.h>
     80 
     81 /*
     82  * PCI configuration space registers
     83  */
     84 #define	ATH_PCI_MMBA		0x10	/* memory mapped base */
     85 
     86 struct ath_cardbus_softc {
     87 	struct ath_softc	sc_ath;
     88 
     89 	/* CardBus-specific goo. */
     90 	void	*sc_ih;			/* interrupt handle */
     91 	cardbus_devfunc_t sc_ct;	/* our CardBus devfuncs */
     92 	cardbustag_t sc_tag;		/* our CardBus tag */
     93 	bus_size_t sc_mapsize;		/* the size of mapped bus space region */
     94 
     95 	pcireg_t sc_bar_val;		/* value of the BAR */
     96 
     97 	cardbus_intr_line_t sc_intrline; /* interrupt line */
     98 	bus_space_tag_t sc_iot;
     99 	bus_space_handle_t sc_ioh;
    100 };
    101 
    102 int	ath_cardbus_match(device_t, cfdata_t, void *);
    103 void	ath_cardbus_attach(device_t, device_t, void *);
    104 int	ath_cardbus_detach(device_t, int);
    105 
    106 CFATTACH_DECL_NEW(ath_cardbus, sizeof(struct ath_cardbus_softc),
    107     ath_cardbus_match, ath_cardbus_attach, ath_cardbus_detach, NULL);
    108 
    109 void	ath_cardbus_setup(struct ath_cardbus_softc *);
    110 
    111 static bool
    112 ath_cardbus_suspend(device_t self, pmf_qual_t qual)
    113 {
    114 	struct ath_cardbus_softc *csc = device_private(self);
    115 
    116 	ath_suspend(&csc->sc_ath);
    117 	if (csc->sc_ih != NULL) {
    118 		cardbus_intr_disestablish(csc->sc_ct->ct_cc, csc->sc_ct->ct_cf,
    119 		    csc->sc_ih);
    120 		csc->sc_ih = NULL;
    121 	}
    122 	return true;
    123 }
    124 
    125 static bool
    126 ath_cardbus_resume(device_t self, pmf_qual_t qual)
    127 {
    128 	struct ath_cardbus_softc *csc = device_private(self);
    129 
    130 	csc->sc_ih = cardbus_intr_establish(csc->sc_ct->ct_cc,
    131 	    csc->sc_ct->ct_cf, csc->sc_intrline, IPL_NET, ath_intr,
    132 	    &csc->sc_ath);
    133 
    134 	if (csc->sc_ih == NULL) {
    135 		aprint_error_dev(self,
    136 		    "unable to establish interrupt\n");
    137 		return false;
    138 	}
    139 
    140 	return ath_resume(&csc->sc_ath);
    141 }
    142 
    143 int
    144 ath_cardbus_match(device_t parent, cfdata_t match, void *aux)
    145 {
    146 	struct cardbus_attach_args *ca = aux;
    147 	const char *devname;
    148 
    149 	devname = ath_hal_probe(PCI_VENDOR(ca->ca_id), PCI_PRODUCT(ca->ca_id));
    150 
    151 	if (devname)
    152 		return 1;
    153 
    154 	return 0;
    155 }
    156 
    157 void
    158 ath_cardbus_attach(device_t parent, device_t self, void *aux)
    159 {
    160 	struct ath_cardbus_softc *csc = device_private(self);
    161 	struct ath_softc *sc = &csc->sc_ath;
    162 	struct cardbus_attach_args *ca = aux;
    163 	cardbus_devfunc_t ct = ca->ca_ct;
    164 	bus_addr_t adr;
    165 
    166 	sc->sc_dev = self;
    167 	sc->sc_dmat = ca->ca_dmat;
    168 	csc->sc_ct = ct;
    169 	csc->sc_tag = ca->ca_tag;
    170 
    171 	aprint_normal("\n");
    172 
    173 	/*
    174 	 * Map the device.
    175 	 */
    176 	if (Cardbus_mapreg_map(ct, ATH_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0,
    177 	    &csc->sc_iot, &csc->sc_ioh, &adr, &csc->sc_mapsize) == 0) {
    178 #if rbus
    179 #else
    180 		(*ct->ct_cf->cardbus_mem_open)(cc, 0, adr, adr+csc->sc_mapsize);
    181 #endif
    182 		csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM;
    183 	} else {
    184 		aprint_error_dev(self, "unable to map device registers\n");
    185 		return;
    186 	}
    187 
    188 	sc->sc_st = HALTAG(csc->sc_iot);
    189 	sc->sc_sh = HALHANDLE(csc->sc_ioh);
    190 
    191 	/*
    192 	 * Set up the PCI configuration registers.
    193 	 */
    194 	ath_cardbus_setup(csc);
    195 
    196 	/* Remember which interrupt line. */
    197 	csc->sc_intrline = ca->ca_intrline;
    198 
    199 	ATH_LOCK_INIT(sc);
    200 
    201 	/*
    202 	 * Finish off the attach.
    203 	 */
    204 	if (ath_attach(PCI_PRODUCT(ca->ca_id), sc) != 0)
    205 		return;
    206 
    207 	if (pmf_device_register(self,
    208 	    ath_cardbus_suspend, ath_cardbus_resume)) {
    209 		pmf_class_network_register(self, &sc->sc_if);
    210 		pmf_device_suspend(self, &sc->sc_qual);
    211 	} else
    212 		aprint_error_dev(self, "couldn't establish power handler\n");
    213 }
    214 
    215 int
    216 ath_cardbus_detach(device_t self, int flags)
    217 {
    218 	struct ath_cardbus_softc *csc = device_private(self);
    219 	struct ath_softc *sc = &csc->sc_ath;
    220 	struct cardbus_devfunc *ct = csc->sc_ct;
    221 	int rv;
    222 
    223 #if defined(DIAGNOSTIC)
    224 	if (ct == NULL)
    225 		panic("%s: data structure lacks", device_xname(sc->sc_dev));
    226 #endif
    227 
    228 	rv = ath_detach(sc);
    229 	if (rv)
    230 		return (rv);
    231 
    232 	pmf_device_deregister(self);
    233 
    234 	/*
    235 	 * Unhook the interrupt handler.
    236 	 */
    237 	if (csc->sc_ih != NULL) {
    238 		cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih);
    239 		csc->sc_ih = NULL;
    240 	}
    241 
    242 	/*
    243 	 * Release bus space and close window.
    244 	 */
    245 	Cardbus_mapreg_unmap(ct, ATH_PCI_MMBA, csc->sc_iot, csc->sc_ioh,
    246 	    csc->sc_mapsize);
    247 
    248 	ATH_LOCK_DESTROY(sc);
    249 
    250 	return (0);
    251 }
    252 
    253 void
    254 ath_cardbus_setup(struct ath_cardbus_softc *csc)
    255 {
    256 	cardbus_devfunc_t ct = csc->sc_ct;
    257 	cardbus_chipset_tag_t cc = ct->ct_cc;
    258 	cardbus_function_tag_t cf = ct->ct_cf;
    259 	int rc;
    260 	pcireg_t reg;
    261 
    262 	if ((rc = cardbus_set_powerstate(ct, csc->sc_tag, PCI_PWR_D0)) != 0)
    263 		aprint_debug("%s: cardbus_set_powerstate %d\n", __func__, rc);
    264 
    265 	/* Program the BAR. */
    266 	cardbus_conf_write(cc, cf, csc->sc_tag, ATH_PCI_MMBA, csc->sc_bar_val);
    267 
    268 	/* Enable the appropriate bits in the PCI CSR. */
    269 	reg = cardbus_conf_read(cc, cf, csc->sc_tag,
    270 	    PCI_COMMAND_STATUS_REG);
    271 	reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
    272 	cardbus_conf_write(cc, cf, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);
    273 }
    274