if_athn_cardbus.c revision 1.2.4.2
1 1.2.4.2 tls /* $NetBSD: if_athn_cardbus.c,v 1.2.4.2 2013/06/23 06:20:16 tls Exp $ */ 2 1.2.4.2 tls /* $OpenBSD: if_athn_cardbus.c,v 1.13 2011/01/08 10:02:32 damien Exp $ */ 3 1.2.4.2 tls 4 1.2.4.2 tls /*- 5 1.2.4.2 tls * Copyright (c) 2009 Damien Bergamini <damien.bergamini (at) free.fr> 6 1.2.4.2 tls * 7 1.2.4.2 tls * Permission to use, copy, modify, and distribute this software for any 8 1.2.4.2 tls * purpose with or without fee is hereby granted, provided that the above 9 1.2.4.2 tls * copyright notice and this permission notice appear in all copies. 10 1.2.4.2 tls * 11 1.2.4.2 tls * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 1.2.4.2 tls * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 1.2.4.2 tls * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 1.2.4.2 tls * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 1.2.4.2 tls * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 1.2.4.2 tls * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 1.2.4.2 tls * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 1.2.4.2 tls */ 19 1.2.4.2 tls 20 1.2.4.2 tls /* 21 1.2.4.2 tls * CardBus front-end for Atheros 802.11a/g/n chipsets. 22 1.2.4.2 tls */ 23 1.2.4.2 tls 24 1.2.4.2 tls #include <sys/cdefs.h> 25 1.2.4.2 tls __KERNEL_RCSID(0, "$NetBSD: if_athn_cardbus.c,v 1.2.4.2 2013/06/23 06:20:16 tls Exp $"); 26 1.2.4.2 tls 27 1.2.4.2 tls #include "opt_inet.h" 28 1.2.4.2 tls 29 1.2.4.2 tls #include <sys/param.h> 30 1.2.4.2 tls #include <sys/sockio.h> 31 1.2.4.2 tls #include <sys/mbuf.h> 32 1.2.4.2 tls #include <sys/kernel.h> 33 1.2.4.2 tls #include <sys/socket.h> 34 1.2.4.2 tls #include <sys/systm.h> 35 1.2.4.2 tls #include <sys/malloc.h> 36 1.2.4.2 tls #include <sys/callout.h> 37 1.2.4.2 tls #include <sys/device.h> 38 1.2.4.2 tls 39 1.2.4.2 tls #include <sys/bus.h> 40 1.2.4.2 tls #include <sys/intr.h> 41 1.2.4.2 tls 42 1.2.4.2 tls #include <net/if.h> 43 1.2.4.2 tls #include <net/if_ether.h> 44 1.2.4.2 tls #include <net/if_media.h> 45 1.2.4.2 tls 46 1.2.4.2 tls #include <net80211/ieee80211_var.h> 47 1.2.4.2 tls #include <net80211/ieee80211_amrr.h> 48 1.2.4.2 tls #include <net80211/ieee80211_radiotap.h> 49 1.2.4.2 tls 50 1.2.4.2 tls #include <dev/ic/athnreg.h> 51 1.2.4.2 tls #include <dev/ic/athnvar.h> 52 1.2.4.2 tls 53 1.2.4.2 tls #include <dev/pci/pcireg.h> 54 1.2.4.2 tls #include <dev/pci/pcivar.h> 55 1.2.4.2 tls #include <dev/pci/pcidevs.h> 56 1.2.4.2 tls 57 1.2.4.2 tls #include <dev/cardbus/cardbusvar.h> 58 1.2.4.2 tls 59 1.2.4.2 tls /* 60 1.2.4.2 tls * PCI configuration space registers 61 1.2.4.2 tls */ 62 1.2.4.2 tls #define ATHN_PCI_MMBA PCI_BAR(0) /* memory mapped base */ 63 1.2.4.2 tls 64 1.2.4.2 tls struct athn_cardbus_softc { 65 1.2.4.2 tls struct athn_softc csc_sc; 66 1.2.4.2 tls 67 1.2.4.2 tls /* CardBus specific goo. */ 68 1.2.4.2 tls cardbus_devfunc_t csc_ct; 69 1.2.4.2 tls pcitag_t csc_tag; 70 1.2.4.2 tls void *csc_ih; 71 1.2.4.2 tls bus_space_tag_t csc_iot; 72 1.2.4.2 tls bus_space_handle_t csc_ioh; 73 1.2.4.2 tls bus_size_t csc_mapsz; 74 1.2.4.2 tls pcireg_t csc_bar_val; 75 1.2.4.2 tls }; 76 1.2.4.2 tls 77 1.2.4.2 tls #define Static static 78 1.2.4.2 tls 79 1.2.4.2 tls Static int athn_cardbus_match(device_t, cfdata_t, void *); 80 1.2.4.2 tls Static void athn_cardbus_attach(device_t, device_t, void *); 81 1.2.4.2 tls Static int athn_cardbus_detach(device_t, int); 82 1.2.4.2 tls 83 1.2.4.2 tls CFATTACH_DECL_NEW(athn_cardbus, sizeof(struct athn_cardbus_softc), 84 1.2.4.2 tls athn_cardbus_match, athn_cardbus_attach, athn_cardbus_detach, NULL); 85 1.2.4.2 tls 86 1.2.4.2 tls Static uint32_t athn_cardbus_read(struct athn_softc *, uint32_t); 87 1.2.4.2 tls Static bool athn_cardbus_resume(device_t, const pmf_qual_t *l); 88 1.2.4.2 tls Static void athn_cardbus_setup(struct athn_cardbus_softc *); 89 1.2.4.2 tls Static bool athn_cardbus_suspend(device_t, const pmf_qual_t *); 90 1.2.4.2 tls Static void athn_cardbus_write(struct athn_softc *, uint32_t, uint32_t); 91 1.2.4.2 tls Static void athn_cardbus_write_barrier(struct athn_softc *); 92 1.2.4.2 tls 93 1.2.4.2 tls #ifdef openbsd_power_management 94 1.2.4.2 tls Static int athn_cardbus_enable(struct athn_softc *); 95 1.2.4.2 tls Static void athn_cardbus_disable(struct athn_softc *); 96 1.2.4.2 tls Static void athn_cardbus_power(struct athn_softc *, int); 97 1.2.4.2 tls #endif /* openbsd_power_management */ 98 1.2.4.2 tls 99 1.2.4.2 tls Static int 100 1.2.4.2 tls athn_cardbus_match(device_t parent, cfdata_t match, void *aux) 101 1.2.4.2 tls { 102 1.2.4.2 tls static const struct { 103 1.2.4.2 tls pci_vendor_id_t vendor; 104 1.2.4.2 tls pci_product_id_t product; 105 1.2.4.2 tls } athn_cardbus_devices[] = { 106 1.2.4.2 tls { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5416 }, 107 1.2.4.2 tls { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5418 }, 108 1.2.4.2 tls { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9160 }, 109 1.2.4.2 tls { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9280 }, 110 1.2.4.2 tls { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9281 }, 111 1.2.4.2 tls { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9285 }, 112 1.2.4.2 tls { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR2427 }, 113 1.2.4.2 tls { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9227 }, 114 1.2.4.2 tls { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9287 }, 115 1.2.4.2 tls { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9300 } 116 1.2.4.2 tls }; 117 1.2.4.2 tls struct cardbus_attach_args *ca = aux; 118 1.2.4.2 tls size_t i; 119 1.2.4.2 tls 120 1.2.4.2 tls for (i = 0; i < __arraycount(athn_cardbus_devices); i++) { 121 1.2.4.2 tls if (PCI_VENDOR(ca->ca_id) == athn_cardbus_devices[i].vendor && 122 1.2.4.2 tls PCI_VENDOR(ca->ca_id) == athn_cardbus_devices[i].product) 123 1.2.4.2 tls return 1; 124 1.2.4.2 tls } 125 1.2.4.2 tls return 0; 126 1.2.4.2 tls } 127 1.2.4.2 tls 128 1.2.4.2 tls Static void 129 1.2.4.2 tls athn_cardbus_attach(device_t parent, device_t self, void *aux) 130 1.2.4.2 tls { 131 1.2.4.2 tls struct athn_cardbus_softc *csc = device_private(self); 132 1.2.4.2 tls struct athn_softc *sc = &csc->csc_sc; 133 1.2.4.2 tls struct ieee80211com *ic = &sc->sc_ic; 134 1.2.4.2 tls struct cardbus_attach_args *ca = aux; 135 1.2.4.2 tls cardbus_devfunc_t ct = ca->ca_ct; 136 1.2.4.2 tls bus_addr_t base; 137 1.2.4.2 tls int error; 138 1.2.4.2 tls 139 1.2.4.2 tls sc->sc_dmat = ca->ca_dmat; 140 1.2.4.2 tls csc->csc_ct = ct; 141 1.2.4.2 tls csc->csc_tag = ca->ca_tag; 142 1.2.4.2 tls 143 1.2.4.2 tls aprint_normal("\n"); 144 1.2.4.2 tls aprint_naive("\n"); 145 1.2.4.2 tls 146 1.2.4.2 tls #ifdef openbsd_power_management 147 1.2.4.2 tls /* Power management hooks. */ 148 1.2.4.2 tls sc->sc_enable = athn_cardbus_enable; 149 1.2.4.2 tls sc->sc_disable = athn_cardbus_disable; 150 1.2.4.2 tls sc->sc_power = athn_cardbus_power; 151 1.2.4.2 tls #endif 152 1.2.4.2 tls sc->sc_ops.read = athn_cardbus_read; 153 1.2.4.2 tls sc->sc_ops.write = athn_cardbus_write; 154 1.2.4.2 tls sc->sc_ops.write_barrier = athn_cardbus_write_barrier; 155 1.2.4.2 tls 156 1.2.4.2 tls /* 157 1.2.4.2 tls * Map control/status registers. 158 1.2.4.2 tls */ 159 1.2.4.2 tls error = Cardbus_mapreg_map(ct, ATHN_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0, 160 1.2.4.2 tls &csc->csc_iot, &csc->csc_ioh, &base, &csc->csc_mapsz); 161 1.2.4.2 tls if (error != 0) { 162 1.2.4.2 tls aprint_error_dev(self, "unable to map device (%d)\n", error); 163 1.2.4.2 tls return; 164 1.2.4.2 tls } 165 1.2.4.2 tls csc->csc_bar_val = base | PCI_MAPREG_TYPE_MEM; 166 1.2.4.2 tls 167 1.2.4.2 tls /* 168 1.2.4.2 tls * Set up the PCI configuration registers. 169 1.2.4.2 tls */ 170 1.2.4.2 tls athn_cardbus_setup(csc); 171 1.2.4.2 tls 172 1.2.4.2 tls if (athn_attach(sc) != 0) { 173 1.2.4.2 tls Cardbus_mapreg_unmap(ct, ATHN_PCI_MMBA, csc->csc_iot, 174 1.2.4.2 tls csc->csc_ioh, csc->csc_mapsz); 175 1.2.4.2 tls return; 176 1.2.4.2 tls } 177 1.2.4.2 tls 178 1.2.4.2 tls if (pmf_device_register(self, 179 1.2.4.2 tls athn_cardbus_suspend, athn_cardbus_resume)) { 180 1.2.4.2 tls pmf_class_network_register(self, &sc->sc_if); 181 1.2.4.2 tls pmf_device_suspend(self, &sc->sc_qual); 182 1.2.4.2 tls } else 183 1.2.4.2 tls aprint_error_dev(self, "couldn't establish power handler\n"); 184 1.2.4.2 tls 185 1.2.4.2 tls // Cardbus_function_disable(ct); 186 1.2.4.2 tls 187 1.2.4.2 tls ieee80211_announce(ic); 188 1.2.4.2 tls } 189 1.2.4.2 tls 190 1.2.4.2 tls Static int 191 1.2.4.2 tls athn_cardbus_detach(device_t self, int flags) 192 1.2.4.2 tls { 193 1.2.4.2 tls struct athn_cardbus_softc *csc = device_private(self); 194 1.2.4.2 tls struct athn_softc *sc = &csc->csc_sc; 195 1.2.4.2 tls cardbus_devfunc_t ct = csc->csc_ct; 196 1.2.4.2 tls cardbus_chipset_tag_t cc = ct->ct_cc; 197 1.2.4.2 tls cardbus_function_tag_t cf = ct->ct_cf; 198 1.2.4.2 tls 199 1.2.4.2 tls athn_detach(sc); 200 1.2.4.2 tls 201 1.2.4.2 tls pmf_device_deregister(self); 202 1.2.4.2 tls 203 1.2.4.2 tls /* Unhook the interrupt handler. */ 204 1.2.4.2 tls if (csc->csc_ih != NULL) 205 1.2.4.2 tls cardbus_intr_disestablish(cc, cf, csc->csc_ih); 206 1.2.4.2 tls 207 1.2.4.2 tls /* Release bus space and close window. */ 208 1.2.4.2 tls Cardbus_mapreg_unmap(ct, ATHN_PCI_MMBA, csc->csc_iot, csc->csc_ioh, 209 1.2.4.2 tls csc->csc_mapsz); 210 1.2.4.2 tls 211 1.2.4.2 tls return 0; 212 1.2.4.2 tls } 213 1.2.4.2 tls 214 1.2.4.2 tls Static void 215 1.2.4.2 tls athn_cardbus_setup(struct athn_cardbus_softc *csc) 216 1.2.4.2 tls { 217 1.2.4.2 tls cardbus_devfunc_t ct = csc->csc_ct; 218 1.2.4.2 tls #ifdef unneeded /* XXX */ 219 1.2.4.2 tls pci_chipset_tag_t pc = csc->csc_pc; 220 1.2.4.2 tls cardbus_chipset_tag_t cc = ct->ct_cc; 221 1.2.4.2 tls cardbus_function_tag_t cf = ct->ct_cf; 222 1.2.4.2 tls #endif 223 1.2.4.2 tls pcireg_t reg; 224 1.2.4.2 tls int rc; 225 1.2.4.2 tls 226 1.2.4.2 tls if ((rc = cardbus_set_powerstate(ct, csc->csc_tag, PCI_PWR_D0)) != 0) 227 1.2.4.2 tls aprint_debug("%s: cardbus_set_powerstate %d\n", __func__, rc); 228 1.2.4.2 tls 229 1.2.4.2 tls /* Program the BAR. */ 230 1.2.4.2 tls Cardbus_conf_write(ct, csc->csc_tag, ATHN_PCI_MMBA, csc->csc_bar_val); 231 1.2.4.2 tls 232 1.2.4.2 tls #ifdef unneeded /* XXX */ 233 1.2.4.2 tls /* Make sure the right access type is on the cardbus bridge. */ 234 1.2.4.2 tls (*cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE); 235 1.2.4.2 tls (*cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); 236 1.2.4.2 tls #endif 237 1.2.4.2 tls /* Enable the appropriate bits in the PCI CSR. */ 238 1.2.4.2 tls reg = Cardbus_conf_read(ct, csc->csc_tag, PCI_COMMAND_STATUS_REG); 239 1.2.4.2 tls reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE; 240 1.2.4.2 tls Cardbus_conf_write(ct, csc->csc_tag, PCI_COMMAND_STATUS_REG, reg); 241 1.2.4.2 tls 242 1.2.4.2 tls /* 243 1.2.4.2 tls * Noone knows why this shit is necessary but there are claims that 244 1.2.4.2 tls * not doing this may cause very frequent PCI FATAL interrupts from 245 1.2.4.2 tls * the card: http://bugzilla.kernel.org/show_bug.cgi?id=13483 246 1.2.4.2 tls */ 247 1.2.4.2 tls reg = Cardbus_conf_read(ct, csc->csc_tag, 0x40); 248 1.2.4.2 tls if (reg & 0xff00) 249 1.2.4.2 tls Cardbus_conf_write(ct, csc->csc_tag, 0x40, reg & ~0xff00); 250 1.2.4.2 tls 251 1.2.4.2 tls /* Change latency timer; default value yields poor results. */ 252 1.2.4.2 tls reg = Cardbus_conf_read(ct, csc->csc_tag, PCI_BHLC_REG); 253 1.2.4.2 tls reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 254 1.2.4.2 tls reg |= 168 << PCI_LATTIMER_SHIFT; 255 1.2.4.2 tls Cardbus_conf_write(ct, csc->csc_tag, PCI_BHLC_REG, reg); 256 1.2.4.2 tls } 257 1.2.4.2 tls 258 1.2.4.2 tls Static uint32_t 259 1.2.4.2 tls athn_cardbus_read(struct athn_softc *sc, uint32_t addr) 260 1.2.4.2 tls { 261 1.2.4.2 tls struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc; 262 1.2.4.2 tls 263 1.2.4.2 tls return bus_space_read_4(csc->csc_iot, csc->csc_ioh, addr); 264 1.2.4.2 tls } 265 1.2.4.2 tls 266 1.2.4.2 tls Static void 267 1.2.4.2 tls athn_cardbus_write(struct athn_softc *sc, uint32_t addr, uint32_t val) 268 1.2.4.2 tls { 269 1.2.4.2 tls struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc; 270 1.2.4.2 tls 271 1.2.4.2 tls bus_space_write_4(csc->csc_iot, csc->csc_ioh, addr, val); 272 1.2.4.2 tls } 273 1.2.4.2 tls 274 1.2.4.2 tls Static void 275 1.2.4.2 tls athn_cardbus_write_barrier(struct athn_softc *sc) 276 1.2.4.2 tls { 277 1.2.4.2 tls struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc; 278 1.2.4.2 tls 279 1.2.4.2 tls bus_space_barrier(csc->csc_iot, csc->csc_ioh, 0, csc->csc_mapsz, 280 1.2.4.2 tls BUS_SPACE_BARRIER_WRITE); 281 1.2.4.2 tls } 282 1.2.4.2 tls 283 1.2.4.2 tls Static bool 284 1.2.4.2 tls athn_cardbus_suspend(device_t self, const pmf_qual_t *qual) 285 1.2.4.2 tls { 286 1.2.4.2 tls struct athn_cardbus_softc *csc = device_private(self); 287 1.2.4.2 tls 288 1.2.4.2 tls athn_suspend(&csc->csc_sc); 289 1.2.4.2 tls if (csc->csc_ih != NULL) { 290 1.2.4.2 tls Cardbus_intr_disestablish(csc->csc_ct, csc->csc_ih); 291 1.2.4.2 tls csc->csc_ih = NULL; 292 1.2.4.2 tls } 293 1.2.4.2 tls return true; 294 1.2.4.2 tls } 295 1.2.4.2 tls 296 1.2.4.2 tls Static bool 297 1.2.4.2 tls athn_cardbus_resume(device_t self, const pmf_qual_t *qual) 298 1.2.4.2 tls { 299 1.2.4.2 tls struct athn_cardbus_softc *csc = device_private(self); 300 1.2.4.2 tls 301 1.2.4.2 tls csc->csc_ih = Cardbus_intr_establish(csc->csc_ct, IPL_NET, athn_intr, 302 1.2.4.2 tls &csc->csc_sc); 303 1.2.4.2 tls 304 1.2.4.2 tls if (csc->csc_ih == NULL) { 305 1.2.4.2 tls aprint_error_dev(self, 306 1.2.4.2 tls "unable to establish interrupt\n"); 307 1.2.4.2 tls return false; 308 1.2.4.2 tls } 309 1.2.4.2 tls return athn_resume(&csc->csc_sc); 310 1.2.4.2 tls } 311 1.2.4.2 tls 312 1.2.4.2 tls /************************************************************************ 313 1.2.4.2 tls * XXX: presumably the pmf_* stuff handles this. 314 1.2.4.2 tls */ 315 1.2.4.2 tls #ifdef openbsd_power_management 316 1.2.4.2 tls Static int 317 1.2.4.2 tls athn_cardbus_enable(struct athn_softc *sc) 318 1.2.4.2 tls { 319 1.2.4.2 tls struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc; 320 1.2.4.2 tls cardbus_devfunc_t ct = csc->csc_ct; 321 1.2.4.2 tls cardbus_chipset_tag_t cc = ct->ct_cc; 322 1.2.4.2 tls cardbus_function_tag_t cf = ct->ct_cf; 323 1.2.4.2 tls 324 1.2.4.2 tls /* Power on the socket. */ 325 1.2.4.2 tls Cardbus_function_enable(ct); 326 1.2.4.2 tls 327 1.2.4.2 tls /* Setup the PCI configuration registers. */ 328 1.2.4.2 tls athn_cardbus_setup(csc); 329 1.2.4.2 tls 330 1.2.4.2 tls /* Map and establish the interrupt handler. */ 331 1.2.4.2 tls csc->csc_ih = cardbus_intr_establish(cc, cf, IPL_NET, athn_intr, sc); 332 1.2.4.2 tls if (csc->csc_ih == NULL) { 333 1.2.4.2 tls printf("%s: could not establish interrupt at %d\n", 334 1.2.4.2 tls device_xname(sc->sc_dev), csc->csc_intrline); 335 1.2.4.2 tls Cardbus_function_disable(ct); 336 1.2.4.2 tls return 1; 337 1.2.4.2 tls } 338 1.2.4.2 tls return 0; 339 1.2.4.2 tls } 340 1.2.4.2 tls 341 1.2.4.2 tls Static void 342 1.2.4.2 tls athn_cardbus_disable(struct athn_softc *sc) 343 1.2.4.2 tls { 344 1.2.4.2 tls struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc; 345 1.2.4.2 tls cardbus_devfunc_t ct = csc->csc_ct; 346 1.2.4.2 tls cardbus_chipset_tag_t cc = ct->ct_cc; 347 1.2.4.2 tls cardbus_function_tag_t cf = ct->ct_cf; 348 1.2.4.2 tls 349 1.2.4.2 tls /* Unhook the interrupt handler. */ 350 1.2.4.2 tls cardbus_intr_disestablish(cc, cf, csc->csc_ih); 351 1.2.4.2 tls csc->csc_ih = NULL; 352 1.2.4.2 tls 353 1.2.4.2 tls /* Power down the socket. */ 354 1.2.4.2 tls Cardbus_function_disable(ct); 355 1.2.4.2 tls } 356 1.2.4.2 tls 357 1.2.4.2 tls Static void 358 1.2.4.2 tls athn_cardbus_power(struct athn_softc *sc, int why) 359 1.2.4.2 tls { 360 1.2.4.2 tls struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc; 361 1.2.4.2 tls 362 1.2.4.2 tls if (why == DVACT_RESUME) { 363 1.2.4.2 tls /* Restore the PCI configuration registers. */ 364 1.2.4.2 tls athn_cardbus_setup(csc); 365 1.2.4.2 tls } 366 1.2.4.2 tls } 367 1.2.4.2 tls #endif /* openbsd_power_management */ 368
Indexes created Wed Oct 22 13:09:56 GMT 2025