if_atw_cardbus.c revision 1.2 1 /* $NetBSD: if_atw_cardbus.c,v 1.2 2003/10/13 08:22:19 dyoung Exp $ */
2
3 /*-
4 * Copyright (c) 1999, 2000, 2003 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center. This code was adapted for the ADMtek ADM8211
10 * by David Young.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the NetBSD
23 * Foundation, Inc. and its contributors.
24 * 4. Neither the name of The NetBSD Foundation nor the names of its
25 * contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 */
40
41 /*
42 * CardBus bus front-end for the ADMtek ADM8211 802.11 MAC/BBP driver.
43 */
44
45 #include <sys/cdefs.h>
46 __KERNEL_RCSID(0, "$NetBSD: if_atw_cardbus.c,v 1.2 2003/10/13 08:22:19 dyoung Exp $");
47
48 #include "opt_inet.h"
49 #include "opt_ns.h"
50 #include "bpfilter.h"
51
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/mbuf.h>
55 #include <sys/malloc.h>
56 #include <sys/kernel.h>
57 #include <sys/socket.h>
58 #include <sys/ioctl.h>
59 #include <sys/errno.h>
60 #include <sys/device.h>
61
62 #include <machine/endian.h>
63
64 #include <net/if.h>
65 #include <net/if_dl.h>
66 #include <net/if_media.h>
67 #include <net/if_ether.h>
68
69 #include <net80211/ieee80211_compat.h>
70 #include <net80211/ieee80211_var.h>
71
72 #if NBPFILTER > 0
73 #include <net/bpf.h>
74 #endif
75
76 #ifdef INET
77 #include <netinet/in.h>
78 #include <netinet/if_inarp.h>
79 #endif
80
81 #ifdef NS
82 #include <netns/ns.h>
83 #include <netns/ns_if.h>
84 #endif
85
86 #include <machine/bus.h>
87 #include <machine/intr.h>
88
89 #include <dev/mii/miivar.h>
90 #include <dev/mii/mii_bitbang.h>
91
92 #include <dev/ic/atwreg.h>
93 #include <dev/ic/atwvar.h>
94
95 #include <dev/pci/pcivar.h>
96 #include <dev/pci/pcireg.h>
97 #include <dev/pci/pcidevs.h>
98
99 #include <dev/cardbus/cardbusvar.h>
100 #include <dev/cardbus/cardbusdevs.h>
101
102 /*
103 * PCI configuration space registers used by the ADM8211.
104 */
105 #define ATW_PCI_IOBA 0x10 /* i/o mapped base */
106 #define ATW_PCI_MMBA 0x14 /* memory mapped base */
107
108 struct atw_cardbus_softc {
109 struct atw_softc sc_atw; /* real ADM8211 softc */
110
111 /* CardBus-specific goo. */
112 void *sc_ih; /* interrupt handle */
113 cardbus_devfunc_t sc_ct; /* our CardBus devfuncs */
114 cardbustag_t sc_tag; /* our CardBus tag */
115 int sc_csr; /* CSR bits */
116 bus_size_t sc_mapsize; /* the size of mapped bus space
117 region */
118
119 int sc_cben; /* CardBus enables */
120 int sc_bar_reg; /* which BAR to use */
121 pcireg_t sc_bar_val; /* value of the BAR */
122
123 int sc_intrline; /* interrupt line */
124 };
125
126 int atw_cardbus_match __P((struct device *, struct cfdata *, void *));
127 void atw_cardbus_attach __P((struct device *, struct device *, void *));
128 int atw_cardbus_detach __P((struct device *, int));
129
130 CFATTACH_DECL(atw_cardbus, sizeof(struct atw_cardbus_softc),
131 atw_cardbus_match, atw_cardbus_attach, atw_cardbus_detach, atw_activate);
132
133 void atw_cardbus_setup __P((struct atw_cardbus_softc *));
134
135 int atw_cardbus_enable __P((struct atw_softc *));
136 void atw_cardbus_disable __P((struct atw_softc *));
137 void atw_cardbus_power __P((struct atw_softc *, int));
138
139 static void atw_cardbus_intr_ack(struct atw_softc *);
140
141 const struct atw_cardbus_product *atw_cardbus_lookup
142 __P((const struct cardbus_attach_args *));
143
144 const struct atw_cardbus_product {
145 u_int32_t acp_vendor; /* PCI vendor ID */
146 u_int32_t acp_product; /* PCI product ID */
147 const char *acp_product_name;
148 } atw_cardbus_products[] = {
149 { PCI_VENDOR_ADMTEK, PCI_PRODUCT_ADMTEK_ADM8211,
150 "ADMtek ADM8211 802.11 MAC/BBP" },
151
152 { 0, 0, NULL },
153 };
154
155 const struct atw_cardbus_product *
156 atw_cardbus_lookup(ca)
157 const struct cardbus_attach_args *ca;
158 {
159 const struct atw_cardbus_product *acp;
160
161 for (acp = atw_cardbus_products;
162 acp->acp_product_name != NULL;
163 acp++) {
164 if (PCI_VENDOR(ca->ca_id) == acp->acp_vendor &&
165 PCI_PRODUCT(ca->ca_id) == acp->acp_product)
166 return (acp);
167 }
168 return (NULL);
169 }
170
171 int
172 atw_cardbus_match(parent, match, aux)
173 struct device *parent;
174 struct cfdata *match;
175 void *aux;
176 {
177 struct cardbus_attach_args *ca = aux;
178
179 if (atw_cardbus_lookup(ca) != NULL)
180 return (1);
181
182 return (0);
183 }
184
185 void
186 atw_cardbus_attach(parent, self, aux)
187 struct device *parent, *self;
188 void *aux;
189 {
190 struct atw_cardbus_softc *csc = (void *)self;
191 struct atw_softc *sc = &csc->sc_atw;
192 struct cardbus_attach_args *ca = aux;
193 cardbus_devfunc_t ct = ca->ca_ct;
194 const struct atw_cardbus_product *acp;
195 bus_addr_t adr;
196 int rev;
197
198 sc->sc_dmat = ca->ca_dmat;
199 csc->sc_ct = ct;
200 csc->sc_tag = ca->ca_tag;
201
202 acp = atw_cardbus_lookup(ca);
203 if (acp == NULL) {
204 printf("\n");
205 panic("atw_cardbus_attach: impossible");
206 }
207
208 /*
209 * Power management hooks.
210 */
211 sc->sc_enable = atw_cardbus_enable;
212 sc->sc_disable = atw_cardbus_disable;
213 sc->sc_power = atw_cardbus_power;
214
215 sc->sc_intr_ack = atw_cardbus_intr_ack;
216
217 /* Get revision info. */
218 rev = PCI_REVISION(ca->ca_class);
219
220 printf(": %s\n", acp->acp_product_name);
221
222 #if 0
223 printf("%s: pass %d.%d signature %08x\n", sc->sc_dev.dv_xname,
224 (rev >> 4) & 0xf, rev & 0xf,
225 cardbus_conf_read(ct->ct_cc, ct->ct_cf, csc->sc_tag, 0x80));
226 #endif
227
228 /*
229 * Map the device.
230 */
231 csc->sc_csr = CARDBUS_COMMAND_MASTER_ENABLE;
232 if (Cardbus_mapreg_map(ct, ATW_PCI_MMBA,
233 CARDBUS_MAPREG_TYPE_MEM, 0, &sc->sc_st, &sc->sc_sh, &adr,
234 &csc->sc_mapsize) == 0) {
235 #if 0
236 printf("%s: atw_cardbus_attach mapped %d bytes mem space\n",
237 sc->sc_dev.dv_xname, csc->sc_mapsize);
238 #endif
239 #if rbus
240 #else
241 (*ct->ct_cf->cardbus_mem_open)(cc, 0, adr, adr+csc->sc_mapsize);
242 #endif
243 csc->sc_cben = CARDBUS_MEM_ENABLE;
244 csc->sc_csr |= CARDBUS_COMMAND_MEM_ENABLE;
245 csc->sc_bar_reg = ATW_PCI_MMBA;
246 csc->sc_bar_val = adr | CARDBUS_MAPREG_TYPE_MEM;
247 } else if (Cardbus_mapreg_map(ct, ATW_PCI_IOBA,
248 CARDBUS_MAPREG_TYPE_IO, 0, &sc->sc_st, &sc->sc_sh, &adr,
249 &csc->sc_mapsize) == 0) {
250 #if 0
251 printf("%s: atw_cardbus_attach mapped %d bytes I/O space\n",
252 sc->sc_dev.dv_xname, csc->sc_mapsize);
253 #endif
254 #if rbus
255 #else
256 (*ct->ct_cf->cardbus_io_open)(cc, 0, adr, adr+csc->sc_mapsize);
257 #endif
258 csc->sc_cben = CARDBUS_IO_ENABLE;
259 csc->sc_csr |= CARDBUS_COMMAND_IO_ENABLE;
260 csc->sc_bar_reg = ATW_PCI_IOBA;
261 csc->sc_bar_val = adr | CARDBUS_MAPREG_TYPE_IO;
262 } else {
263 printf("%s: unable to map device registers\n",
264 sc->sc_dev.dv_xname);
265 return;
266 }
267
268 /*
269 * Bring the chip out of powersave mode and initialize the
270 * configuration registers.
271 */
272 atw_cardbus_setup(csc);
273
274 /* Remember which interrupt line. */
275 csc->sc_intrline = ca->ca_intrline;
276
277 printf("%s: interrupting at %d\n", sc->sc_dev.dv_xname,
278 csc->sc_intrline);
279 #if 0
280 /*
281 * The CardBus cards will make it to store-and-forward mode as
282 * soon as you put them under any kind of load, so just start
283 * out there.
284 */
285 sc->sc_txthresh = 3; /* TBD name constant */
286 #endif
287
288 /*
289 * Finish off the attach.
290 */
291 atw_attach(sc);
292
293 ATW_WRITE(sc, ATW_FER, ATW_FER_INTR);
294
295 /*
296 * Power down the socket.
297 */
298 Cardbus_function_disable(csc->sc_ct);
299 }
300
301 static void
302 atw_cardbus_intr_ack(sc)
303 struct atw_softc *sc;
304 {
305 ATW_WRITE(sc, ATW_FER, ATW_FER_INTR);
306 }
307
308 int
309 atw_cardbus_detach(self, flags)
310 struct device *self;
311 int flags;
312 {
313 struct atw_cardbus_softc *csc = (void *)self;
314 struct atw_softc *sc = &csc->sc_atw;
315 struct cardbus_devfunc *ct = csc->sc_ct;
316 int rv;
317
318 #if defined(DIAGNOSTIC)
319 if (ct == NULL)
320 panic("%s: data structure lacks", sc->sc_dev.dv_xname);
321 #endif
322
323 rv = atw_detach(sc);
324 if (rv)
325 return (rv);
326
327 /*
328 * Unhook the interrupt handler.
329 */
330 if (csc->sc_ih != NULL)
331 cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih);
332
333 /*
334 * Release bus space and close window.
335 */
336 if (csc->sc_bar_reg != 0)
337 Cardbus_mapreg_unmap(ct, csc->sc_bar_reg,
338 sc->sc_st, sc->sc_sh, csc->sc_mapsize);
339
340 return (0);
341 }
342
343 int
344 atw_cardbus_enable(sc)
345 struct atw_softc *sc;
346 {
347 struct atw_cardbus_softc *csc = (void *) sc;
348 cardbus_devfunc_t ct = csc->sc_ct;
349 cardbus_chipset_tag_t cc = ct->ct_cc;
350 cardbus_function_tag_t cf = ct->ct_cf;
351
352 /*
353 * Power on the socket.
354 */
355 Cardbus_function_enable(ct);
356
357 /*
358 * Set up the PCI configuration registers.
359 */
360 atw_cardbus_setup(csc);
361
362 /*
363 * Map and establish the interrupt.
364 */
365 csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET,
366 atw_intr, sc);
367 if (csc->sc_ih == NULL) {
368 printf("%s: unable to establish interrupt at %d\n",
369 sc->sc_dev.dv_xname, csc->sc_intrline);
370 Cardbus_function_disable(csc->sc_ct);
371 return (1);
372 }
373
374 return (0);
375 }
376
377 void
378 atw_cardbus_disable(sc)
379 struct atw_softc *sc;
380 {
381 struct atw_cardbus_softc *csc = (void *) sc;
382 cardbus_devfunc_t ct = csc->sc_ct;
383 cardbus_chipset_tag_t cc = ct->ct_cc;
384 cardbus_function_tag_t cf = ct->ct_cf;
385
386 /* Unhook the interrupt handler. */
387 cardbus_intr_disestablish(cc, cf, csc->sc_ih);
388 csc->sc_ih = NULL;
389
390 /* Power down the socket. */
391 Cardbus_function_disable(ct);
392 }
393
394 void
395 atw_cardbus_power(sc, why)
396 struct atw_softc *sc;
397 int why;
398 {
399 struct atw_cardbus_softc *csc = (void *) sc;
400
401 printf("%s: atw_cardbus_power\n", sc->sc_dev.dv_xname);
402
403 if (why == PWR_RESUME) {
404 /*
405 * Give the PCI configuration registers a kick
406 * in the head.
407 */
408 #ifdef DIAGNOSTIC
409 if (ATW_IS_ENABLED(sc) == 0)
410 panic("atw_cardbus_power");
411 #endif
412 atw_cardbus_setup(csc);
413 }
414 }
415
416 void
417 atw_cardbus_setup(csc)
418 struct atw_cardbus_softc *csc;
419 {
420 struct atw_softc *sc = &csc->sc_atw;
421 cardbus_devfunc_t ct = csc->sc_ct;
422 cardbus_chipset_tag_t cc = ct->ct_cc;
423 cardbus_function_tag_t cf = ct->ct_cf;
424 pcireg_t reg;
425 int pmreg;
426
427 if (cardbus_get_capability(cc, cf, csc->sc_tag,
428 PCI_CAP_PWRMGMT, &pmreg, 0)) {
429 reg = cardbus_conf_read(cc, cf, csc->sc_tag, pmreg + 4) & 0x03;
430 #if 1 /* XXX Probably not right for CardBus. */
431 if (reg == 3) {
432 /*
433 * The card has lost all configuration data in
434 * this state, so punt.
435 */
436 printf("%s: unable to wake up from power state D3\n",
437 sc->sc_dev.dv_xname);
438 return;
439 }
440 #endif
441 if (reg != 0) {
442 printf("%s: waking up from power state D%d\n",
443 sc->sc_dev.dv_xname, reg);
444 cardbus_conf_write(cc, cf, csc->sc_tag,
445 pmreg + 4, 0);
446 }
447 }
448
449 /* Make sure the right access type is on the CardBus bridge. */
450 (*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cben);
451 (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
452
453 /* Program the BAR. */
454 cardbus_conf_write(cc, cf, csc->sc_tag, csc->sc_bar_reg,
455 csc->sc_bar_val);
456
457 /* Enable the appropriate bits in the PCI CSR. */
458 reg = cardbus_conf_read(cc, cf, csc->sc_tag,
459 CARDBUS_COMMAND_STATUS_REG);
460 reg &= ~(CARDBUS_COMMAND_IO_ENABLE|CARDBUS_COMMAND_MEM_ENABLE);
461 reg |= csc->sc_csr;
462 cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_COMMAND_STATUS_REG,
463 reg);
464
465 /*
466 * Make sure the latency timer is set to some reasonable
467 * value.
468 */
469 reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG);
470 if (CARDBUS_LATTIMER(reg) < 0x20) {
471 reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT);
472 reg |= (0x20 << CARDBUS_LATTIMER_SHIFT);
473 cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG, reg);
474 }
475 }
476
477