if_re_cardbus.c revision 1.14
1 /* $NetBSD: if_re_cardbus.c,v 1.14 2007/10/19 11:59:39 ad Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Jonathan Stone 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * if_re_cardbus.c: 32 * Cardbus specific routines for Realtek 8169 ethernet adapter. 33 * Tested for : 34 * Netgear GA-511 (8169S) 35 * Buffalo LPC-CB-CLGT 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_re_cardbus.c,v 1.14 2007/10/19 11:59:39 ad Exp $"); 40 41 #include "opt_inet.h" 42 #include "bpfilter.h" 43 #include "rnd.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/callout.h> 48 #include <sys/device.h> 49 #include <sys/sockio.h> 50 #include <sys/mbuf.h> 51 #include <sys/malloc.h> 52 #include <sys/kernel.h> 53 #include <sys/socket.h> 54 55 #include <net/if.h> 56 #include <net/if_arp.h> 57 #include <net/if_ether.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #ifdef INET 61 #include <netinet/in.h> 62 #include <netinet/if_inarp.h> 63 #endif 64 65 #if NBPFILTER > 0 66 #include <net/bpf.h> 67 #endif 68 #if NRND > 0 69 #include <sys/rnd.h> 70 #endif 71 72 #include <sys/bus.h> 73 74 #include <dev/pci/pcireg.h> 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/pcidevs.h> 77 78 #include <dev/cardbus/cardbusvar.h> 79 #include <dev/pci/pcidevs.h> 80 81 #include <dev/mii/mii.h> 82 #include <dev/mii/miivar.h> 83 84 /* 85 * Default to using PIO access for this driver. On SMP systems, 86 * there appear to be problems with memory mapped mode: it looks like 87 * doing too many memory mapped access back to back in rapid succession 88 * can hang the bus. I'm inclined to blame this on crummy design/construction 89 * on the part of Realtek. Memory mapped mode does appear to work on 90 * uniprocessor systems though. 91 */ 92 #define RTK_USEIOSPACE 93 94 #include <dev/ic/rtl81x9reg.h> 95 #include <dev/ic/rtl81x9var.h> 96 97 #include <dev/ic/rtl8169var.h> 98 99 /* 100 * Various supported device vendors/types and their names. 101 */ 102 static const struct rtk_type re_cardbus_devs[] = { 103 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, 104 RTK_8169, "Realtek 10/100/1000baseT" }, 105 { 0, 0, 0, NULL } 106 }; 107 108 static int re_cardbus_match(struct device *, struct cfdata *, void *); 109 static void re_cardbus_attach(struct device *, struct device *, void *); 110 static int re_cardbus_detach(struct device *, int); 111 112 struct re_cardbus_softc { 113 struct rtk_softc sc_rtk; /* real rtk softc */ 114 115 /* CardBus-specific goo. */ 116 void *sc_ih; 117 cardbus_devfunc_t sc_ct; 118 cardbustag_t sc_tag; 119 int sc_csr; 120 int sc_cben; 121 int sc_bar_reg; 122 pcireg_t sc_bar_val; 123 bus_size_t sc_mapsize; 124 int sc_intrline; 125 }; 126 127 CFATTACH_DECL(re_cardbus, sizeof(struct re_cardbus_softc), 128 re_cardbus_match, re_cardbus_attach, re_cardbus_detach, re_activate); 129 130 const struct rtk_type *re_cardbus_lookup(const struct cardbus_attach_args *); 131 132 void re_cardbus_setup(struct re_cardbus_softc *); 133 134 int re_cardbus_enable(struct rtk_softc *); 135 void re_cardbus_disable(struct rtk_softc *); 136 void re_cardbus_power(struct rtk_softc *, int); 137 138 const struct rtk_type * 139 re_cardbus_lookup(const struct cardbus_attach_args *ca) 140 { 141 const struct rtk_type *t; 142 143 for (t = re_cardbus_devs; t->rtk_name != NULL; t++) { 144 if (CARDBUS_VENDOR(ca->ca_id) == t->rtk_vid && 145 CARDBUS_PRODUCT(ca->ca_id) == t->rtk_did) { 146 return t; 147 } 148 } 149 return NULL; 150 } 151 152 int 153 re_cardbus_match(struct device *parent, struct cfdata *match, void *aux) 154 { 155 struct cardbus_attach_args *ca = aux; 156 157 if (re_cardbus_lookup(ca) != NULL) 158 return 1; 159 160 return 0; 161 } 162 163 164 void 165 re_cardbus_attach(struct device *parent, struct device *self, void *aux) 166 { 167 struct re_cardbus_softc *csc = device_private(self); 168 struct rtk_softc *sc = &csc->sc_rtk; 169 struct cardbus_attach_args *ca = aux; 170 cardbus_devfunc_t ct = ca->ca_ct; 171 const struct rtk_type *t; 172 bus_addr_t adr; 173 174 sc->sc_dmat = ca->ca_dmat; 175 csc->sc_ct = ct; 176 csc->sc_tag = ca->ca_tag; 177 csc->sc_intrline = ca->ca_intrline; 178 179 t = re_cardbus_lookup(ca); 180 if (t == NULL) { 181 aprint_error("\n"); 182 panic("re_cardbus_attach: impossible"); 183 } 184 aprint_normal(": %s\n", t->rtk_name); 185 186 /* 187 * Power management hooks. 188 */ 189 sc->sc_enable = re_cardbus_enable; 190 sc->sc_disable = re_cardbus_disable; 191 sc->sc_power = re_cardbus_power; 192 193 /* 194 * Map control/status registers. 195 */ 196 csc->sc_csr = CARDBUS_COMMAND_MASTER_ENABLE; 197 #ifdef RTK_USEIOSPACE 198 if (Cardbus_mapreg_map(ct, RTK_PCI_LOIO, CARDBUS_MAPREG_TYPE_IO, 0, 199 &sc->rtk_btag, &sc->rtk_bhandle, &adr, &csc->sc_mapsize) == 0) { 200 #if rbus 201 #else 202 (*ct->ct_cf->cardbus_io_open)(cc, 0, adr, adr+csc->sc_mapsize); 203 #endif 204 csc->sc_cben = CARDBUS_IO_ENABLE; 205 csc->sc_csr |= CARDBUS_COMMAND_IO_ENABLE; 206 csc->sc_bar_reg = RTK_PCI_LOIO; 207 csc->sc_bar_val = adr | CARDBUS_MAPREG_TYPE_IO; 208 } 209 #else 210 if (Cardbus_mapreg_map(ct, RTK_PCI_LOMEM, CARDBUS_MAPREG_TYPE_MEM, 0, 211 &sc->rtk_btag, &sc->rtk_bhandle, &adr, &csc->sc_mapsize) == 0) { 212 #if rbus 213 #else 214 (*ct->ct_cf->cardbus_mem_open)(cc, 0, adr, adr+csc->sc_mapsize); 215 #endif 216 csc->sc_cben = CARDBUS_MEM_ENABLE; 217 csc->sc_csr |= CARDBUS_COMMAND_MEM_ENABLE; 218 csc->sc_bar_reg = RTK_PCI_LOMEM; 219 csc->sc_bar_val = adr | CARDBUS_MAPREG_TYPE_MEM; 220 } 221 #endif 222 else { 223 aprint_error("%s: unable to map deviceregisters\n", 224 sc->sc_dev.dv_xname); 225 return; 226 } 227 /* 228 * Handle power management nonsense and initialize the 229 * configuration registers. 230 */ 231 re_cardbus_setup(csc); 232 233 sc->sc_dmat = ca->ca_dmat; 234 re_attach(sc); 235 236 /* 237 * Power down the socket. 238 */ 239 Cardbus_function_disable(csc->sc_ct); 240 } 241 242 int 243 re_cardbus_detach(struct device *self, int flags) 244 { 245 struct re_cardbus_softc *csc = device_private(self); 246 struct rtk_softc *sc = &csc->sc_rtk; 247 struct cardbus_devfunc *ct = csc->sc_ct; 248 int rv; 249 250 #ifdef DIAGNOSTIC 251 if (ct == NULL) 252 panic("%s: cardbus softc, cardbus_devfunc NULL", 253 sc->sc_dev.dv_xname); 254 #endif 255 rv = re_detach(sc); 256 if (rv) 257 return rv; 258 /* 259 * Unhook the interrupt handler. 260 */ 261 if (csc->sc_ih != NULL) 262 cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih); 263 264 /* 265 * Release bus space and close window. 266 */ 267 if (csc->sc_bar_reg != 0) 268 Cardbus_mapreg_unmap(ct, csc->sc_bar_reg, 269 sc->rtk_btag, sc->rtk_bhandle, csc->sc_mapsize); 270 271 return 0; 272 } 273 274 void 275 re_cardbus_setup(struct re_cardbus_softc *csc) 276 { 277 struct rtk_softc *sc = &csc->sc_rtk; 278 cardbus_devfunc_t ct = csc->sc_ct; 279 cardbus_chipset_tag_t cc = ct->ct_cc; 280 cardbus_function_tag_t cf = ct->ct_cf; 281 pcireg_t reg,command; 282 int pmreg; 283 284 /* 285 * Handle power management nonsense. 286 */ 287 if (cardbus_get_capability(cc, cf, csc->sc_tag, 288 PCI_CAP_PWRMGMT, &pmreg, 0)) { 289 command = cardbus_conf_read(cc, cf, csc->sc_tag, 290 pmreg + PCI_PMCSR); 291 if (command & PCI_PMCSR_STATE_MASK) { 292 pcireg_t iobase, membase, irq; 293 294 /* Save important PCI config data. */ 295 iobase = cardbus_conf_read(cc, cf, csc->sc_tag, 296 RTK_PCI_LOIO); 297 membase = cardbus_conf_read(cc, cf,csc->sc_tag, 298 RTK_PCI_LOMEM); 299 irq = cardbus_conf_read(cc, cf,csc->sc_tag, 300 CARDBUS_INTERRUPT_REG); 301 302 /* Reset the power state. */ 303 aprint_normal("%s: chip is in D%d power mode " 304 "-- setting to D0\n", sc->sc_dev.dv_xname, 305 command & PCI_PMCSR_STATE_MASK); 306 command &= ~PCI_PMCSR_STATE_MASK; 307 cardbus_conf_write(cc, cf, csc->sc_tag, 308 pmreg + PCI_PMCSR, command); 309 310 /* Restore PCI config data. */ 311 cardbus_conf_write(cc, cf, csc->sc_tag, 312 RTK_PCI_LOIO, iobase); 313 cardbus_conf_write(cc, cf, csc->sc_tag, 314 RTK_PCI_LOMEM, membase); 315 cardbus_conf_write(cc, cf, csc->sc_tag, 316 CARDBUS_INTERRUPT_REG, irq); 317 } 318 } 319 320 /* Program the BAR */ 321 cardbus_conf_write(cc, cf, csc->sc_tag, 322 csc->sc_bar_reg, csc->sc_bar_val); 323 324 /* Make sure the right access type is on the CardBus bridge. */ 325 (*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cben); 326 (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); 327 328 /* Enable the appropriate bits in the CARDBUS CSR. */ 329 reg = cardbus_conf_read(cc, cf, csc->sc_tag, 330 CARDBUS_COMMAND_STATUS_REG); 331 reg &= ~(CARDBUS_COMMAND_IO_ENABLE|CARDBUS_COMMAND_MEM_ENABLE); 332 reg |= csc->sc_csr; 333 cardbus_conf_write(cc, cf, csc->sc_tag, 334 CARDBUS_COMMAND_STATUS_REG, reg); 335 336 /* 337 * Make sure the latency timer is set to some reasonable 338 * value. 339 */ 340 reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG); 341 if (CARDBUS_LATTIMER(reg) < 0x40) { 342 reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT); 343 reg |= (0x40 << CARDBUS_LATTIMER_SHIFT); 344 cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG, reg); 345 } 346 } 347 348 int 349 re_cardbus_enable(struct rtk_softc *sc) 350 { 351 struct re_cardbus_softc *csc = (void *) sc; 352 cardbus_devfunc_t ct = csc->sc_ct; 353 cardbus_chipset_tag_t cc = ct->ct_cc; 354 cardbus_function_tag_t cf = ct->ct_cf; 355 356 /* 357 * Power on the socket. 358 */ 359 Cardbus_function_enable(ct); 360 361 /* 362 * Set up the PCI configuration registers. 363 */ 364 re_cardbus_setup(csc); 365 366 /* 367 * Map and establish the interrupt. 368 */ 369 csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, 370 IPL_NET, re_intr, sc); 371 if (csc->sc_ih == NULL) { 372 aprint_error("%s: unable to establish interrupt at %d\n", 373 sc->sc_dev.dv_xname, csc->sc_intrline); 374 Cardbus_function_disable(csc->sc_ct); 375 return 1; 376 } 377 aprint_normal("%s: interrupting at %d\n", sc->sc_dev.dv_xname, 378 csc->sc_intrline); 379 return 0; 380 } 381 382 void 383 re_cardbus_disable(struct rtk_softc *sc) 384 { 385 struct re_cardbus_softc *csc = (void *) sc; 386 cardbus_devfunc_t ct = csc->sc_ct; 387 cardbus_chipset_tag_t cc = ct->ct_cc; 388 cardbus_function_tag_t cf = ct->ct_cf; 389 390 /* Unhook the interrupt handler. */ 391 cardbus_intr_disestablish(cc, cf, csc->sc_ih); 392 csc->sc_ih = NULL; 393 394 /* Power down the socket. */ 395 Cardbus_function_disable(ct); 396 } 397 398 void 399 re_cardbus_power(struct rtk_softc *sc, int why) 400 { 401 struct re_cardbus_softc *csc = (void *) sc; 402 403 if (why == PWR_RESUME) { 404 /* 405 * Give the PCI configuration registers a kick 406 * in the head. 407 */ 408 #ifdef DIAGNOSTIC 409 if (RTK_IS_ENABLED(sc) == 0) 410 panic("re_cardbus_power"); 411 #endif 412 re_cardbus_setup(csc); 413 } 414 } 415
Indexes created Sun Sep 28 16:09:52 GMT 2025