if_re_cardbus.c revision 1.19
1 /* $NetBSD: if_re_cardbus.c,v 1.19 2009/08/29 14:18:34 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Jonathan Stone 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * if_re_cardbus.c: 32 * Cardbus specific routines for Realtek 8169 ethernet adapter. 33 * Tested for : 34 * Netgear GA-511 (8169S) 35 * Buffalo LPC-CB-CLGT 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_re_cardbus.c,v 1.19 2009/08/29 14:18:34 tsutsui Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 45 #include <net/if.h> 46 #include <net/if_ether.h> 47 #include <net/if_media.h> 48 49 #include <sys/bus.h> 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcidevs.h> 54 55 #include <dev/cardbus/cardbusvar.h> 56 57 #include <dev/mii/mii.h> 58 #include <dev/mii/miivar.h> 59 60 /* 61 * Default to using PIO access for this driver. On SMP systems, 62 * there appear to be problems with memory mapped mode: it looks like 63 * doing too many memory mapped access back to back in rapid succession 64 * can hang the bus. I'm inclined to blame this on crummy design/construction 65 * on the part of Realtek. Memory mapped mode does appear to work on 66 * uniprocessor systems though. 67 */ 68 #define RTK_USEIOSPACE 69 70 #include <dev/ic/rtl81x9reg.h> 71 #include <dev/ic/rtl81x9var.h> 72 73 #include <dev/ic/rtl8169var.h> 74 75 /* 76 * Various supported device vendors/types and their names. 77 */ 78 static const struct rtk_type re_cardbus_devs[] = { 79 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, 80 RTK_8169, "Realtek 10/100/1000baseT" }, 81 { 0, 0, 0, NULL } 82 }; 83 84 static int re_cardbus_match(device_t, cfdata_t, void *); 85 static void re_cardbus_attach(device_t, device_t, void *); 86 static int re_cardbus_detach(device_t, int); 87 88 struct re_cardbus_softc { 89 struct rtk_softc sc_rtk; /* real rtk softc */ 90 91 /* CardBus-specific goo. */ 92 void *sc_ih; 93 cardbus_devfunc_t sc_ct; 94 cardbustag_t sc_tag; 95 int sc_csr; 96 int sc_cben; 97 int sc_bar_reg; 98 pcireg_t sc_bar_val; 99 bus_size_t sc_mapsize; 100 cardbus_intr_line_t sc_intrline; 101 }; 102 103 CFATTACH_DECL_NEW(re_cardbus, sizeof(struct re_cardbus_softc), 104 re_cardbus_match, re_cardbus_attach, re_cardbus_detach, re_activate); 105 106 const struct rtk_type *re_cardbus_lookup(const struct cardbus_attach_args *); 107 108 void re_cardbus_setup(struct re_cardbus_softc *); 109 110 int re_cardbus_enable(struct rtk_softc *); 111 void re_cardbus_disable(struct rtk_softc *); 112 113 const struct rtk_type * 114 re_cardbus_lookup(const struct cardbus_attach_args *ca) 115 { 116 const struct rtk_type *t; 117 118 for (t = re_cardbus_devs; t->rtk_name != NULL; t++) { 119 if (CARDBUS_VENDOR(ca->ca_id) == t->rtk_vid && 120 CARDBUS_PRODUCT(ca->ca_id) == t->rtk_did) { 121 return t; 122 } 123 } 124 return NULL; 125 } 126 127 int 128 re_cardbus_match(device_t parent, cfdata_t cf, void *aux) 129 { 130 struct cardbus_attach_args *ca = aux; 131 132 if (re_cardbus_lookup(ca) != NULL) 133 return 1; 134 135 return 0; 136 } 137 138 139 void 140 re_cardbus_attach(device_t parent, device_t self, void *aux) 141 { 142 struct re_cardbus_softc *csc = device_private(self); 143 struct rtk_softc *sc = &csc->sc_rtk; 144 struct cardbus_attach_args *ca = aux; 145 cardbus_devfunc_t ct = ca->ca_ct; 146 const struct rtk_type *t; 147 bus_addr_t adr; 148 149 sc->sc_dev = self; 150 sc->sc_dmat = ca->ca_dmat; 151 csc->sc_ct = ct; 152 csc->sc_tag = ca->ca_tag; 153 csc->sc_intrline = ca->ca_intrline; 154 155 t = re_cardbus_lookup(ca); 156 if (t == NULL) { 157 aprint_error("\n"); 158 panic("%s: impossible", __func__); 159 } 160 aprint_normal(": %s\n", t->rtk_name); 161 162 /* 163 * Power management hooks. 164 */ 165 sc->sc_enable = re_cardbus_enable; 166 sc->sc_disable = re_cardbus_disable; 167 168 /* 169 * Map control/status registers. 170 */ 171 csc->sc_csr = CARDBUS_COMMAND_MASTER_ENABLE; 172 #ifdef RTK_USEIOSPACE 173 if (Cardbus_mapreg_map(ct, RTK_PCI_LOIO, CARDBUS_MAPREG_TYPE_IO, 0, 174 &sc->rtk_btag, &sc->rtk_bhandle, &adr, &csc->sc_mapsize) == 0) { 175 #if rbus 176 #else 177 (*ct->ct_cf->cardbus_io_open)(cc, 0, adr, adr+csc->sc_mapsize); 178 #endif 179 csc->sc_cben = CARDBUS_IO_ENABLE; 180 csc->sc_csr |= CARDBUS_COMMAND_IO_ENABLE; 181 csc->sc_bar_reg = RTK_PCI_LOIO; 182 csc->sc_bar_val = adr | CARDBUS_MAPREG_TYPE_IO; 183 } 184 #else 185 if (Cardbus_mapreg_map(ct, RTK_PCI_LOMEM, CARDBUS_MAPREG_TYPE_MEM, 0, 186 &sc->rtk_btag, &sc->rtk_bhandle, &adr, &csc->sc_mapsize) == 0) { 187 #if rbus 188 #else 189 (*ct->ct_cf->cardbus_mem_open)(cc, 0, adr, adr+csc->sc_mapsize); 190 #endif 191 csc->sc_cben = CARDBUS_MEM_ENABLE; 192 csc->sc_csr |= CARDBUS_COMMAND_MEM_ENABLE; 193 csc->sc_bar_reg = RTK_PCI_LOMEM; 194 csc->sc_bar_val = adr | CARDBUS_MAPREG_TYPE_MEM; 195 } 196 #endif 197 else { 198 aprint_error_dev(self, "unable to map deviceregisters\n"); 199 return; 200 } 201 /* 202 * Handle power management nonsense and initialize the 203 * configuration registers. 204 */ 205 re_cardbus_setup(csc); 206 207 sc->sc_dmat = ca->ca_dmat; 208 re_attach(sc); 209 210 if (!pmf_device_register(self, NULL, NULL)) 211 aprint_error_dev(self, "couldn't establish power handler\n"); 212 else 213 pmf_class_network_register(self, &sc->ethercom.ec_if); 214 215 /* 216 * Power down the socket. 217 */ 218 Cardbus_function_disable(csc->sc_ct); 219 } 220 221 int 222 re_cardbus_detach(device_t self, int flags) 223 { 224 struct re_cardbus_softc *csc = device_private(self); 225 struct rtk_softc *sc = &csc->sc_rtk; 226 struct cardbus_devfunc *ct = csc->sc_ct; 227 int rv; 228 229 #ifdef DIAGNOSTIC 230 if (ct == NULL) 231 panic("%s: cardbus softc, cardbus_devfunc NULL", 232 device_xname(self)); 233 #endif 234 235 rv = re_detach(sc); 236 if (rv) 237 return rv; 238 239 pmf_device_deregister(self); 240 241 /* 242 * Unhook the interrupt handler. 243 */ 244 if (csc->sc_ih != NULL) 245 cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih); 246 247 /* 248 * Release bus space and close window. 249 */ 250 if (csc->sc_bar_reg != 0) 251 Cardbus_mapreg_unmap(ct, csc->sc_bar_reg, 252 sc->rtk_btag, sc->rtk_bhandle, csc->sc_mapsize); 253 254 return 0; 255 } 256 257 void 258 re_cardbus_setup(struct re_cardbus_softc *csc) 259 { 260 struct rtk_softc *sc = &csc->sc_rtk; 261 cardbus_devfunc_t ct = csc->sc_ct; 262 cardbus_chipset_tag_t cc = ct->ct_cc; 263 cardbus_function_tag_t cf = ct->ct_cf; 264 pcireg_t reg, command; 265 int pmreg; 266 267 /* 268 * Handle power management nonsense. 269 */ 270 if (cardbus_get_capability(cc, cf, csc->sc_tag, 271 PCI_CAP_PWRMGMT, &pmreg, 0)) { 272 command = cardbus_conf_read(cc, cf, csc->sc_tag, 273 pmreg + PCI_PMCSR); 274 if (command & PCI_PMCSR_STATE_MASK) { 275 pcireg_t iobase, membase, irq; 276 277 /* Save important PCI config data. */ 278 iobase = cardbus_conf_read(cc, cf, csc->sc_tag, 279 RTK_PCI_LOIO); 280 membase = cardbus_conf_read(cc, cf,csc->sc_tag, 281 RTK_PCI_LOMEM); 282 irq = cardbus_conf_read(cc, cf,csc->sc_tag, 283 CARDBUS_INTERRUPT_REG); 284 285 /* Reset the power state. */ 286 aprint_normal_dev(sc->sc_dev, 287 "chip is in D%d power mode -- setting to D0\n", 288 command & PCI_PMCSR_STATE_MASK); 289 command &= ~PCI_PMCSR_STATE_MASK; 290 cardbus_conf_write(cc, cf, csc->sc_tag, 291 pmreg + PCI_PMCSR, command); 292 293 /* Restore PCI config data. */ 294 cardbus_conf_write(cc, cf, csc->sc_tag, 295 RTK_PCI_LOIO, iobase); 296 cardbus_conf_write(cc, cf, csc->sc_tag, 297 RTK_PCI_LOMEM, membase); 298 cardbus_conf_write(cc, cf, csc->sc_tag, 299 CARDBUS_INTERRUPT_REG, irq); 300 } 301 } 302 303 /* Program the BAR */ 304 cardbus_conf_write(cc, cf, csc->sc_tag, 305 csc->sc_bar_reg, csc->sc_bar_val); 306 307 /* Make sure the right access type is on the CardBus bridge. */ 308 (*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cben); 309 (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); 310 311 /* Enable the appropriate bits in the CARDBUS CSR. */ 312 reg = cardbus_conf_read(cc, cf, csc->sc_tag, 313 CARDBUS_COMMAND_STATUS_REG); 314 reg &= ~(CARDBUS_COMMAND_IO_ENABLE|CARDBUS_COMMAND_MEM_ENABLE); 315 reg |= csc->sc_csr; 316 cardbus_conf_write(cc, cf, csc->sc_tag, 317 CARDBUS_COMMAND_STATUS_REG, reg); 318 319 /* 320 * Make sure the latency timer is set to some reasonable 321 * value. 322 */ 323 reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG); 324 if (CARDBUS_LATTIMER(reg) < 0x40) { 325 reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT); 326 reg |= (0x40 << CARDBUS_LATTIMER_SHIFT); 327 cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG, reg); 328 } 329 } 330 331 int 332 re_cardbus_enable(struct rtk_softc *sc) 333 { 334 struct re_cardbus_softc *csc = (struct re_cardbus_softc *)sc; 335 cardbus_devfunc_t ct = csc->sc_ct; 336 cardbus_chipset_tag_t cc = ct->ct_cc; 337 cardbus_function_tag_t cf = ct->ct_cf; 338 339 /* 340 * Power on the socket. 341 */ 342 Cardbus_function_enable(ct); 343 344 /* 345 * Set up the PCI configuration registers. 346 */ 347 re_cardbus_setup(csc); 348 349 /* 350 * Map and establish the interrupt. 351 */ 352 csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, 353 IPL_NET, re_intr, sc); 354 if (csc->sc_ih == NULL) { 355 aprint_error_dev(sc->sc_dev, 356 "unable to establish interrupt\n"); 357 Cardbus_function_disable(csc->sc_ct); 358 return 1; 359 } 360 return 0; 361 } 362 363 void 364 re_cardbus_disable(struct rtk_softc *sc) 365 { 366 struct re_cardbus_softc *csc = (struct re_cardbus_softc *)sc; 367 cardbus_devfunc_t ct = csc->sc_ct; 368 cardbus_chipset_tag_t cc = ct->ct_cc; 369 cardbus_function_tag_t cf = ct->ct_cf; 370 371 /* Unhook the interrupt handler. */ 372 cardbus_intr_disestablish(cc, cf, csc->sc_ih); 373 csc->sc_ih = NULL; 374 375 /* Power down the socket. */ 376 Cardbus_function_disable(ct); 377 } 378
Indexes created Wed Oct 22 13:09:56 GMT 2025