if_re_cardbus.c revision 1.26
1 /* $NetBSD: if_re_cardbus.c,v 1.26 2010/07/27 21:02:00 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Jonathan Stone 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * if_re_cardbus.c: 32 * Cardbus specific routines for Realtek 8169 ethernet adapter. 33 * Tested for : 34 * Netgear GA-511 (8169S) 35 * Buffalo LPC-CB-CLGT 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_re_cardbus.c,v 1.26 2010/07/27 21:02:00 jakllsch Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 45 #include <net/if.h> 46 #include <net/if_ether.h> 47 #include <net/if_media.h> 48 49 #include <sys/bus.h> 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcidevs.h> 54 55 #include <dev/cardbus/cardbusvar.h> 56 57 #include <dev/mii/mii.h> 58 #include <dev/mii/miivar.h> 59 60 /* 61 * Default to using PIO access for this driver. On SMP systems, 62 * there appear to be problems with memory mapped mode: it looks like 63 * doing too many memory mapped access back to back in rapid succession 64 * can hang the bus. I'm inclined to blame this on crummy design/construction 65 * on the part of Realtek. Memory mapped mode does appear to work on 66 * uniprocessor systems though. 67 */ 68 #define RTK_USEIOSPACE 69 70 #include <dev/ic/rtl81x9reg.h> 71 #include <dev/ic/rtl81x9var.h> 72 73 #include <dev/ic/rtl8169var.h> 74 75 /* 76 * Various supported device vendors/types and their names. 77 */ 78 static const struct rtk_type re_cardbus_devs[] = { 79 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, 80 RTK_8169, "Realtek 10/100/1000baseT" }, 81 { 0, 0, 0, NULL } 82 }; 83 84 static int re_cardbus_match(device_t, cfdata_t, void *); 85 static void re_cardbus_attach(device_t, device_t, void *); 86 static int re_cardbus_detach(device_t, int); 87 88 struct re_cardbus_softc { 89 struct rtk_softc sc_rtk; /* real rtk softc */ 90 91 /* CardBus-specific goo. */ 92 void *sc_ih; 93 cardbus_devfunc_t sc_ct; 94 pcitag_t sc_tag; 95 pcireg_t sc_csr; 96 int sc_bar_reg; 97 pcireg_t sc_bar_val; 98 cardbus_intr_line_t sc_intrline; 99 }; 100 101 CFATTACH_DECL_NEW(re_cardbus, sizeof(struct re_cardbus_softc), 102 re_cardbus_match, re_cardbus_attach, re_cardbus_detach, re_activate); 103 104 const struct rtk_type *re_cardbus_lookup(const struct cardbus_attach_args *); 105 106 void re_cardbus_setup(struct re_cardbus_softc *); 107 108 int re_cardbus_enable(struct rtk_softc *); 109 void re_cardbus_disable(struct rtk_softc *); 110 111 const struct rtk_type * 112 re_cardbus_lookup(const struct cardbus_attach_args *ca) 113 { 114 const struct rtk_type *t; 115 116 for (t = re_cardbus_devs; t->rtk_name != NULL; t++) { 117 if (PCI_VENDOR(ca->ca_id) == t->rtk_vid && 118 PCI_PRODUCT(ca->ca_id) == t->rtk_did) { 119 return t; 120 } 121 } 122 return NULL; 123 } 124 125 int 126 re_cardbus_match(device_t parent, cfdata_t cf, void *aux) 127 { 128 struct cardbus_attach_args *ca = aux; 129 130 if (re_cardbus_lookup(ca) != NULL) 131 return 1; 132 133 return 0; 134 } 135 136 137 void 138 re_cardbus_attach(device_t parent, device_t self, void *aux) 139 { 140 struct re_cardbus_softc *csc = device_private(self); 141 struct rtk_softc *sc = &csc->sc_rtk; 142 struct cardbus_attach_args *ca = aux; 143 cardbus_devfunc_t ct = ca->ca_ct; 144 const struct rtk_type *t; 145 bus_addr_t adr; 146 147 sc->sc_dev = self; 148 sc->sc_dmat = ca->ca_dmat; 149 csc->sc_ct = ct; 150 csc->sc_tag = ca->ca_tag; 151 csc->sc_intrline = ca->ca_intrline; 152 153 t = re_cardbus_lookup(ca); 154 if (t == NULL) { 155 aprint_error("\n"); 156 panic("%s: impossible", __func__); 157 } 158 aprint_normal(": %s\n", t->rtk_name); 159 160 /* 161 * Power management hooks. 162 */ 163 sc->sc_enable = re_cardbus_enable; 164 sc->sc_disable = re_cardbus_disable; 165 166 /* 167 * Map control/status registers. 168 */ 169 csc->sc_csr = PCI_COMMAND_MASTER_ENABLE; 170 #ifdef RTK_USEIOSPACE 171 if (Cardbus_mapreg_map(ct, RTK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 172 &sc->rtk_btag, &sc->rtk_bhandle, &adr, &sc->rtk_bsize) == 0) { 173 csc->sc_csr |= PCI_COMMAND_IO_ENABLE; 174 csc->sc_bar_reg = RTK_PCI_LOIO; 175 csc->sc_bar_val = adr | PCI_MAPREG_TYPE_IO; 176 } 177 #else 178 if (Cardbus_mapreg_map(ct, RTK_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 179 &sc->rtk_btag, &sc->rtk_bhandle, &adr, &sc->rtk_bsize) == 0) { 180 csc->sc_csr |= PCI_COMMAND_MEM_ENABLE; 181 csc->sc_bar_reg = RTK_PCI_LOMEM; 182 csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM; 183 } 184 #endif 185 else { 186 aprint_error_dev(self, "unable to map deviceregisters\n"); 187 return; 188 } 189 /* 190 * Handle power management nonsense and initialize the 191 * configuration registers. 192 */ 193 re_cardbus_setup(csc); 194 195 sc->sc_dmat = ca->ca_dmat; 196 re_attach(sc); 197 198 /* 199 * Power down the socket. 200 */ 201 Cardbus_function_disable(csc->sc_ct); 202 } 203 204 int 205 re_cardbus_detach(device_t self, int flags) 206 { 207 struct re_cardbus_softc *csc = device_private(self); 208 struct rtk_softc *sc = &csc->sc_rtk; 209 struct cardbus_devfunc *ct = csc->sc_ct; 210 int rv; 211 212 #ifdef DIAGNOSTIC 213 if (ct == NULL) 214 panic("%s: cardbus softc, cardbus_devfunc NULL", 215 device_xname(self)); 216 #endif 217 218 rv = re_detach(sc); 219 if (rv) 220 return rv; 221 222 /* 223 * Unhook the interrupt handler. 224 */ 225 if (csc->sc_ih != NULL) 226 Cardbus_intr_disestablish(ct, csc->sc_ih); 227 228 /* 229 * Release bus space and close window. 230 */ 231 if (csc->sc_bar_reg != 0) 232 Cardbus_mapreg_unmap(ct, csc->sc_bar_reg, 233 sc->rtk_btag, sc->rtk_bhandle, sc->rtk_bsize); 234 235 return 0; 236 } 237 238 void 239 re_cardbus_setup(struct re_cardbus_softc *csc) 240 { 241 struct rtk_softc *sc = &csc->sc_rtk; 242 cardbus_devfunc_t ct = csc->sc_ct; 243 cardbus_chipset_tag_t cc = ct->ct_cc; 244 cardbus_function_tag_t cf = ct->ct_cf; 245 pcireg_t reg, command; 246 int pmreg; 247 248 /* 249 * Handle power management nonsense. 250 */ 251 if (cardbus_get_capability(cc, cf, csc->sc_tag, 252 PCI_CAP_PWRMGMT, &pmreg, 0)) { 253 command = Cardbus_conf_read(ct, csc->sc_tag, 254 pmreg + PCI_PMCSR); 255 if (command & PCI_PMCSR_STATE_MASK) { 256 pcireg_t iobase, membase, irq; 257 258 /* Save important PCI config data. */ 259 iobase = Cardbus_conf_read(ct, csc->sc_tag, 260 RTK_PCI_LOIO); 261 membase = Cardbus_conf_read(ct, csc->sc_tag, 262 RTK_PCI_LOMEM); 263 irq = Cardbus_conf_read(ct, csc->sc_tag, 264 PCI_INTERRUPT_REG); 265 266 /* Reset the power state. */ 267 aprint_normal_dev(sc->sc_dev, 268 "chip is in D%d power mode -- setting to D0\n", 269 command & PCI_PMCSR_STATE_MASK); 270 command &= ~PCI_PMCSR_STATE_MASK; 271 Cardbus_conf_write(ct, csc->sc_tag, 272 pmreg + PCI_PMCSR, command); 273 274 /* Restore PCI config data. */ 275 Cardbus_conf_write(ct, csc->sc_tag, 276 RTK_PCI_LOIO, iobase); 277 Cardbus_conf_write(ct, csc->sc_tag, 278 RTK_PCI_LOMEM, membase); 279 Cardbus_conf_write(ct, csc->sc_tag, 280 PCI_INTERRUPT_REG, irq); 281 } 282 } 283 284 /* Program the BAR */ 285 Cardbus_conf_write(ct, csc->sc_tag, csc->sc_bar_reg, csc->sc_bar_val); 286 287 /* Enable the appropriate bits in the CARDBUS CSR. */ 288 reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG); 289 reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE); 290 reg |= csc->sc_csr; 291 Cardbus_conf_write(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg); 292 293 /* 294 * Make sure the latency timer is set to some reasonable 295 * value. 296 */ 297 reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_BHLC_REG); 298 if (PCI_LATTIMER(reg) < 0x40) { 299 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 300 reg |= (0x40 << PCI_LATTIMER_SHIFT); 301 Cardbus_conf_write(ct, csc->sc_tag, PCI_BHLC_REG, reg); 302 } 303 } 304 305 int 306 re_cardbus_enable(struct rtk_softc *sc) 307 { 308 struct re_cardbus_softc *csc = (struct re_cardbus_softc *)sc; 309 cardbus_devfunc_t ct = csc->sc_ct; 310 311 /* 312 * Power on the socket. 313 */ 314 Cardbus_function_enable(ct); 315 316 /* 317 * Set up the PCI configuration registers. 318 */ 319 re_cardbus_setup(csc); 320 321 /* 322 * Map and establish the interrupt. 323 */ 324 csc->sc_ih = Cardbus_intr_establish(ct, csc->sc_intrline, 325 IPL_NET, re_intr, sc); 326 if (csc->sc_ih == NULL) { 327 aprint_error_dev(sc->sc_dev, 328 "unable to establish interrupt\n"); 329 Cardbus_function_disable(csc->sc_ct); 330 return 1; 331 } 332 return 0; 333 } 334 335 void 336 re_cardbus_disable(struct rtk_softc *sc) 337 { 338 struct re_cardbus_softc *csc = (struct re_cardbus_softc *)sc; 339 cardbus_devfunc_t ct = csc->sc_ct; 340 341 /* Unhook the interrupt handler. */ 342 Cardbus_intr_disestablish(ct, csc->sc_ih); 343 csc->sc_ih = NULL; 344 345 /* Power down the socket. */ 346 Cardbus_function_disable(ct); 347 } 348
Indexes created Mon Sep 29 21:09:56 GMT 2025