if_rtw_cardbus.c revision 1.34.2.1
1 /* $NetBSD: if_rtw_cardbus.c,v 1.34.2.1 2010/04/30 14:43:10 uebayasi Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2005 David Young. All rights reserved. 5 * 6 * Adapted for the RTL8180 by David Young. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 18 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 19 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 20 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 21 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 23 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 28 * OF SUCH DAMAGE. 29 */ 30 /*- 31 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 32 * All rights reserved. 33 * 34 * This code is derived from software contributed to The NetBSD Foundation 35 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 36 * NASA Ames Research Center. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 48 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 49 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 50 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 51 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 52 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 53 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 54 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 55 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 56 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 57 * POSSIBILITY OF SUCH DAMAGE. 58 */ 59 60 /* 61 * Cardbus front-end for the Realtek RTL8180 802.11 MAC/BBP driver. 62 * 63 * TBD factor with atw, tlp Cardbus front-ends? 64 */ 65 66 #include <sys/cdefs.h> 67 __KERNEL_RCSID(0, "$NetBSD: if_rtw_cardbus.c,v 1.34.2.1 2010/04/30 14:43:10 uebayasi Exp $"); 68 69 #include "opt_inet.h" 70 71 #include <sys/param.h> 72 #include <sys/systm.h> 73 #include <sys/mbuf.h> 74 #include <sys/malloc.h> 75 #include <sys/kernel.h> 76 #include <sys/socket.h> 77 #include <sys/ioctl.h> 78 #include <sys/errno.h> 79 #include <sys/device.h> 80 81 #include <machine/endian.h> 82 83 #include <net/if.h> 84 #include <net/if_dl.h> 85 #include <net/if_media.h> 86 #include <net/if_ether.h> 87 88 #include <net80211/ieee80211_netbsd.h> 89 #include <net80211/ieee80211_radiotap.h> 90 #include <net80211/ieee80211_var.h> 91 92 #include <sys/bus.h> 93 #include <sys/intr.h> 94 95 #include <dev/ic/rtwreg.h> 96 #include <dev/ic/rtwvar.h> 97 98 #include <dev/pci/pcivar.h> 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcidevs.h> 101 102 #include <dev/cardbus/cardbusvar.h> 103 #include <dev/pci/pcidevs.h> 104 105 /* 106 * PCI configuration space registers used by the RTL8180. 107 */ 108 #define RTW_PCI_IOBA 0x10 /* i/o mapped base */ 109 #define RTW_PCI_MMBA 0x14 /* memory mapped base */ 110 111 struct rtw_cardbus_softc { 112 struct rtw_softc sc_rtw; /* real RTL8180 softc */ 113 114 /* CardBus-specific goo. */ 115 void *sc_ih; /* interrupt handle */ 116 cardbus_devfunc_t sc_ct; /* our CardBus devfuncs */ 117 pcitag_t sc_tag; /* our CardBus tag */ 118 int sc_csr; /* CSR bits */ 119 bus_size_t sc_mapsize; /* size of the mapped bus space 120 * region 121 */ 122 123 int sc_bar; /* which BAR to use */ 124 125 cardbus_intr_line_t sc_intrline; /* interrupt line */ 126 }; 127 128 int rtw_cardbus_match(device_t, cfdata_t, void *); 129 void rtw_cardbus_attach(device_t, device_t, void *); 130 int rtw_cardbus_detach(device_t, int); 131 132 CFATTACH_DECL3_NEW(rtw_cardbus, sizeof(struct rtw_cardbus_softc), 133 rtw_cardbus_match, rtw_cardbus_attach, rtw_cardbus_detach, NULL, NULL, NULL, 134 DVF_DETACH_SHUTDOWN); 135 136 void rtw_cardbus_setup(struct rtw_cardbus_softc *); 137 138 bool rtw_cardbus_resume(device_t, const pmf_qual_t *); 139 bool rtw_cardbus_suspend(device_t, const pmf_qual_t *); 140 141 const struct rtw_cardbus_product *rtw_cardbus_lookup( 142 const struct cardbus_attach_args *); 143 144 const struct rtw_cardbus_product { 145 u_int32_t rcp_vendor; /* PCI vendor ID */ 146 u_int32_t rcp_product; /* PCI product ID */ 147 const char *rcp_product_name; 148 } rtw_cardbus_products[] = { 149 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8180, 150 "Realtek RTL8180 802.11 MAC/BBP" }, 151 152 { PCI_VENDOR_BELKIN, PCI_PRODUCT_BELKIN_F5D6020V3, 153 "Belkin F5D6020v3 802.11b (RTL8180 MAC/BBP)" }, 154 155 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DWL610, 156 "DWL-610 D-Link Air 802.11b (RTL8180 MAC/BBP)" }, 157 158 { 0, 0, NULL }, 159 }; 160 161 const struct rtw_cardbus_product * 162 rtw_cardbus_lookup(const struct cardbus_attach_args *ca) 163 { 164 const struct rtw_cardbus_product *rcp; 165 166 for (rcp = rtw_cardbus_products; rcp->rcp_product_name != NULL; rcp++) { 167 if (PCI_VENDOR(ca->ca_id) == rcp->rcp_vendor && 168 PCI_PRODUCT(ca->ca_id) == rcp->rcp_product) 169 return rcp; 170 } 171 return NULL; 172 } 173 174 int 175 rtw_cardbus_match(device_t parent, cfdata_t match, void *aux) 176 { 177 struct cardbus_attach_args *ca = aux; 178 179 if (rtw_cardbus_lookup(ca) != NULL) 180 return 1; 181 182 return 0; 183 } 184 185 static void 186 rtw_cardbus_funcregen(struct rtw_regs *regs, int enable) 187 { 188 u_int32_t reg; 189 rtw_config0123_enable(regs, 1); 190 reg = RTW_READ(regs, RTW_CONFIG3); 191 if (enable) 192 RTW_WRITE(regs, RTW_CONFIG3, reg | RTW_CONFIG3_FUNCREGEN); 193 else 194 RTW_WRITE(regs, RTW_CONFIG3, reg & ~RTW_CONFIG3_FUNCREGEN); 195 rtw_config0123_enable(regs, 0); 196 } 197 198 void 199 rtw_cardbus_attach(device_t parent, device_t self, void *aux) 200 { 201 struct rtw_cardbus_softc *csc = device_private(self); 202 struct rtw_softc *sc = &csc->sc_rtw; 203 struct rtw_regs *regs = &sc->sc_regs; 204 struct cardbus_attach_args *ca = aux; 205 cardbus_devfunc_t ct = ca->ca_ct; 206 const struct rtw_cardbus_product *rcp; 207 bus_addr_t adr; 208 int rev; 209 210 sc->sc_dev = self; 211 sc->sc_dmat = ca->ca_dmat; 212 csc->sc_ct = ct; 213 csc->sc_tag = ca->ca_tag; 214 215 rcp = rtw_cardbus_lookup(ca); 216 if (rcp == NULL) { 217 printf("\n"); 218 panic("rtw_cardbus_attach: impossible"); 219 } 220 221 /* Get revision info. */ 222 rev = PCI_REVISION(ca->ca_class); 223 224 printf(": %s\n", rcp->rcp_product_name); 225 226 RTW_DPRINTF(RTW_DEBUG_ATTACH, 227 ("%s: pass %d.%d signature %08x\n", device_xname(self), 228 (rev >> 4) & 0xf, rev & 0xf, 229 Cardbus_conf_read(ct, csc->sc_tag, 0x80))); 230 231 /* 232 * Map the device. 233 */ 234 csc->sc_csr = PCI_COMMAND_MASTER_ENABLE | 235 PCI_COMMAND_PARITY_ENABLE | 236 PCI_COMMAND_SERR_ENABLE; 237 if (Cardbus_mapreg_map(ct, RTW_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0, 238 ®s->r_bt, ®s->r_bh, &adr, ®s->r_sz) == 0) { 239 RTW_DPRINTF(RTW_DEBUG_ATTACH, 240 ("%s: %s mapped %" PRIuMAX " bytes mem space\n", 241 device_xname(self), __func__, (uintmax_t)regs->r_sz)); 242 csc->sc_csr |= PCI_COMMAND_MEM_ENABLE; 243 csc->sc_bar = RTW_PCI_MMBA; 244 } else if (Cardbus_mapreg_map(ct, RTW_PCI_IOBA, PCI_MAPREG_TYPE_IO, 245 0, ®s->r_bt, ®s->r_bh, &adr, ®s->r_sz) == 0) { 246 RTW_DPRINTF(RTW_DEBUG_ATTACH, 247 ("%s: %s mapped %" PRIuMAX " bytes I/O space\n", 248 device_xname(self), __func__, (uintmax_t)regs->r_sz)); 249 csc->sc_csr |= PCI_COMMAND_IO_ENABLE; 250 csc->sc_bar = RTW_PCI_IOBA; 251 } else { 252 aprint_error_dev(self, "unable to map device registers\n"); 253 return; 254 } 255 256 /* 257 * Bring the chip out of powersave mode and initialize the 258 * configuration registers. 259 */ 260 rtw_cardbus_setup(csc); 261 262 /* Remember which interrupt line. */ 263 csc->sc_intrline = ca->ca_intrline; 264 265 /* 266 * Finish off the attach. 267 */ 268 rtw_attach(sc); 269 270 rtw_cardbus_funcregen(regs, 1); 271 272 RTW_WRITE(regs, RTW_FEMR, 0); 273 RTW_WRITE(regs, RTW_FER, RTW_READ(regs, RTW_FER)); 274 275 if (pmf_device_register(self, 276 rtw_cardbus_suspend, rtw_cardbus_resume)) { 277 pmf_class_network_register(self, &sc->sc_if); 278 /* 279 * Power down the socket. 280 */ 281 pmf_device_suspend(self, &sc->sc_qual); 282 } else 283 aprint_error_dev(self, "couldn't establish power handler\n"); 284 } 285 286 int 287 rtw_cardbus_detach(device_t self, int flags) 288 { 289 struct rtw_cardbus_softc *csc = device_private(self); 290 struct rtw_softc *sc = &csc->sc_rtw; 291 struct rtw_regs *regs = &sc->sc_regs; 292 struct cardbus_devfunc *ct = csc->sc_ct; 293 int rc; 294 295 #if defined(DIAGNOSTIC) 296 if (ct == NULL) 297 panic("%s: data structure lacks", device_xname(self)); 298 #endif 299 300 if ((rc = rtw_detach(sc)) != 0) 301 return rc; 302 303 /* 304 * Unhook the interrupt handler. 305 */ 306 if (csc->sc_ih != NULL) 307 Cardbus_intr_disestablish(ct, csc->sc_ih); 308 309 /* 310 * Release bus space and close window. 311 */ 312 if (csc->sc_bar != 0) 313 Cardbus_mapreg_unmap(ct, csc->sc_bar, 314 regs->r_bt, regs->r_bh, regs->r_sz); 315 316 return 0; 317 } 318 319 bool 320 rtw_cardbus_resume(device_t self, const pmf_qual_t *qual) 321 { 322 struct rtw_cardbus_softc *csc = device_private(self); 323 struct rtw_softc *sc = &csc->sc_rtw; 324 cardbus_devfunc_t ct = csc->sc_ct; 325 326 /* 327 * Map and establish the interrupt. 328 */ 329 csc->sc_ih = Cardbus_intr_establish(ct, csc->sc_intrline, IPL_NET, 330 rtw_intr, sc); 331 if (csc->sc_ih == NULL) { 332 aprint_error_dev(sc->sc_dev, 333 "unable to establish interrupt\n"); 334 return false; 335 } 336 337 rtw_cardbus_funcregen(&sc->sc_regs, 1); 338 339 RTW_WRITE(&sc->sc_regs, RTW_FEMR, RTW_FEMR_INTR); 340 RTW_WRITE(&sc->sc_regs, RTW_FER, RTW_FER_INTR); 341 342 return rtw_resume(self, qual); 343 } 344 345 bool 346 rtw_cardbus_suspend(device_t self, const pmf_qual_t *qual) 347 { 348 struct rtw_cardbus_softc *csc = device_private(self); 349 struct rtw_softc *sc = &csc->sc_rtw; 350 cardbus_devfunc_t ct = csc->sc_ct; 351 352 if (!rtw_suspend(self, qual)) 353 return false; 354 355 RTW_WRITE(&sc->sc_regs, RTW_FEMR, 356 RTW_READ(&sc->sc_regs, RTW_FEMR) & ~RTW_FEMR_INTR); 357 358 rtw_cardbus_funcregen(&sc->sc_regs, 0); 359 360 /* Unhook the interrupt handler. */ 361 Cardbus_intr_disestablish(ct, csc->sc_ih); 362 csc->sc_ih = NULL; 363 return true; 364 } 365 366 void 367 rtw_cardbus_setup(struct rtw_cardbus_softc *csc) 368 { 369 pcitag_t tag = csc->sc_tag; 370 cardbus_devfunc_t ct = csc->sc_ct; 371 pcireg_t bhlc, csr, lattimer; 372 373 (void)cardbus_set_powerstate(ct, tag, PCI_PWR_D0); 374 375 /* I believe the datasheet tries to warn us that the RTL8180 376 * wants for 16 (0x10) to divide the latency timer. 377 */ 378 bhlc = Cardbus_conf_read(ct, tag, PCI_BHLC_REG); 379 lattimer = rounddown(PCI_LATTIMER(bhlc), 0x10); 380 if (PCI_LATTIMER(bhlc) != lattimer) { 381 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 382 bhlc |= (lattimer << PCI_LATTIMER_SHIFT); 383 Cardbus_conf_write(ct, tag, PCI_BHLC_REG, bhlc); 384 } 385 386 /* Enable the appropriate bits in the PCI CSR. */ 387 csr = Cardbus_conf_read(ct, tag, PCI_COMMAND_STATUS_REG); 388 csr &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE); 389 csr |= csc->sc_csr; 390 Cardbus_conf_write(ct, tag, PCI_COMMAND_STATUS_REG, csr); 391 } 392
Indexes created Wed Oct 22 13:09:56 GMT 2025