if_rtw_cardbus.c revision 1.39
1 /* $NetBSD: if_rtw_cardbus.c,v 1.39 2010/03/04 22:33:12 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2005 David Young. All rights reserved. 5 * 6 * Adapted for the RTL8180 by David Young. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 18 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 19 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 20 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 21 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 23 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 28 * OF SUCH DAMAGE. 29 */ 30 /*- 31 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 32 * All rights reserved. 33 * 34 * This code is derived from software contributed to The NetBSD Foundation 35 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 36 * NASA Ames Research Center. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 48 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 49 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 50 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 51 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 52 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 53 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 54 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 55 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 56 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 57 * POSSIBILITY OF SUCH DAMAGE. 58 */ 59 60 /* 61 * Cardbus front-end for the Realtek RTL8180 802.11 MAC/BBP driver. 62 * 63 * TBD factor with atw, tlp Cardbus front-ends? 64 */ 65 66 #include <sys/cdefs.h> 67 __KERNEL_RCSID(0, "$NetBSD: if_rtw_cardbus.c,v 1.39 2010/03/04 22:33:12 dyoung Exp $"); 68 69 #include "opt_inet.h" 70 71 #include <sys/param.h> 72 #include <sys/systm.h> 73 #include <sys/mbuf.h> 74 #include <sys/malloc.h> 75 #include <sys/kernel.h> 76 #include <sys/socket.h> 77 #include <sys/ioctl.h> 78 #include <sys/errno.h> 79 #include <sys/device.h> 80 81 #include <machine/endian.h> 82 83 #include <net/if.h> 84 #include <net/if_dl.h> 85 #include <net/if_media.h> 86 #include <net/if_ether.h> 87 88 #include <net80211/ieee80211_netbsd.h> 89 #include <net80211/ieee80211_radiotap.h> 90 #include <net80211/ieee80211_var.h> 91 92 #include <sys/bus.h> 93 #include <sys/intr.h> 94 95 #include <dev/ic/rtwreg.h> 96 #include <dev/ic/rtwvar.h> 97 98 #include <dev/pci/pcivar.h> 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcidevs.h> 101 102 #include <dev/cardbus/cardbusvar.h> 103 #include <dev/pci/pcidevs.h> 104 105 /* 106 * PCI configuration space registers used by the RTL8180. 107 */ 108 #define RTW_PCI_IOBA 0x10 /* i/o mapped base */ 109 #define RTW_PCI_MMBA 0x14 /* memory mapped base */ 110 111 struct rtw_cardbus_softc { 112 struct rtw_softc sc_rtw; /* real RTL8180 softc */ 113 114 /* CardBus-specific goo. */ 115 void *sc_ih; /* interrupt handle */ 116 cardbus_devfunc_t sc_ct; /* our CardBus devfuncs */ 117 pcitag_t sc_tag; /* our CardBus tag */ 118 int sc_csr; /* CSR bits */ 119 bus_size_t sc_mapsize; /* size of the mapped bus space 120 * region 121 */ 122 123 int sc_bar_reg; /* which BAR to use */ 124 pcireg_t sc_bar_val; /* value of the BAR */ 125 126 cardbus_intr_line_t sc_intrline; /* interrupt line */ 127 }; 128 129 int rtw_cardbus_match(device_t, cfdata_t, void *); 130 void rtw_cardbus_attach(device_t, device_t, void *); 131 int rtw_cardbus_detach(device_t, int); 132 133 CFATTACH_DECL3_NEW(rtw_cardbus, sizeof(struct rtw_cardbus_softc), 134 rtw_cardbus_match, rtw_cardbus_attach, rtw_cardbus_detach, NULL, NULL, NULL, 135 DVF_DETACH_SHUTDOWN); 136 137 void rtw_cardbus_setup(struct rtw_cardbus_softc *); 138 139 bool rtw_cardbus_resume(device_t, const pmf_qual_t *); 140 bool rtw_cardbus_suspend(device_t, const pmf_qual_t *); 141 142 const struct rtw_cardbus_product *rtw_cardbus_lookup( 143 const struct cardbus_attach_args *); 144 145 const struct rtw_cardbus_product { 146 u_int32_t rcp_vendor; /* PCI vendor ID */ 147 u_int32_t rcp_product; /* PCI product ID */ 148 const char *rcp_product_name; 149 } rtw_cardbus_products[] = { 150 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8180, 151 "Realtek RTL8180 802.11 MAC/BBP" }, 152 153 { PCI_VENDOR_BELKIN, PCI_PRODUCT_BELKIN_F5D6020V3, 154 "Belkin F5D6020v3 802.11b (RTL8180 MAC/BBP)" }, 155 156 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DWL610, 157 "DWL-610 D-Link Air 802.11b (RTL8180 MAC/BBP)" }, 158 159 { 0, 0, NULL }, 160 }; 161 162 const struct rtw_cardbus_product * 163 rtw_cardbus_lookup(const struct cardbus_attach_args *ca) 164 { 165 const struct rtw_cardbus_product *rcp; 166 167 for (rcp = rtw_cardbus_products; rcp->rcp_product_name != NULL; rcp++) { 168 if (PCI_VENDOR(ca->ca_id) == rcp->rcp_vendor && 169 PCI_PRODUCT(ca->ca_id) == rcp->rcp_product) 170 return rcp; 171 } 172 return NULL; 173 } 174 175 int 176 rtw_cardbus_match(device_t parent, cfdata_t match, void *aux) 177 { 178 struct cardbus_attach_args *ca = aux; 179 180 if (rtw_cardbus_lookup(ca) != NULL) 181 return 1; 182 183 return 0; 184 } 185 186 static void 187 rtw_cardbus_funcregen(struct rtw_regs *regs, int enable) 188 { 189 u_int32_t reg; 190 rtw_config0123_enable(regs, 1); 191 reg = RTW_READ(regs, RTW_CONFIG3); 192 if (enable) 193 RTW_WRITE(regs, RTW_CONFIG3, reg | RTW_CONFIG3_FUNCREGEN); 194 else 195 RTW_WRITE(regs, RTW_CONFIG3, reg & ~RTW_CONFIG3_FUNCREGEN); 196 rtw_config0123_enable(regs, 0); 197 } 198 199 void 200 rtw_cardbus_attach(device_t parent, device_t self, void *aux) 201 { 202 struct rtw_cardbus_softc *csc = device_private(self); 203 struct rtw_softc *sc = &csc->sc_rtw; 204 struct rtw_regs *regs = &sc->sc_regs; 205 struct cardbus_attach_args *ca = aux; 206 cardbus_devfunc_t ct = ca->ca_ct; 207 const struct rtw_cardbus_product *rcp; 208 bus_addr_t adr; 209 int rev; 210 211 sc->sc_dev = self; 212 sc->sc_dmat = ca->ca_dmat; 213 csc->sc_ct = ct; 214 csc->sc_tag = ca->ca_tag; 215 216 rcp = rtw_cardbus_lookup(ca); 217 if (rcp == NULL) { 218 printf("\n"); 219 panic("rtw_cardbus_attach: impossible"); 220 } 221 222 /* Get revision info. */ 223 rev = PCI_REVISION(ca->ca_class); 224 225 printf(": %s\n", rcp->rcp_product_name); 226 227 RTW_DPRINTF(RTW_DEBUG_ATTACH, 228 ("%s: pass %d.%d signature %08x\n", device_xname(self), 229 (rev >> 4) & 0xf, rev & 0xf, 230 Cardbus_conf_read(ct, csc->sc_tag, 0x80))); 231 232 /* 233 * Map the device. 234 */ 235 csc->sc_csr = PCI_COMMAND_MASTER_ENABLE | 236 PCI_COMMAND_PARITY_ENABLE | 237 PCI_COMMAND_SERR_ENABLE; 238 if (Cardbus_mapreg_map(ct, RTW_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0, 239 ®s->r_bt, ®s->r_bh, &adr, ®s->r_sz) == 0) { 240 RTW_DPRINTF(RTW_DEBUG_ATTACH, 241 ("%s: %s mapped %" PRIuMAX " bytes mem space\n", 242 device_xname(self), __func__, (uintmax_t)regs->r_sz)); 243 csc->sc_csr |= PCI_COMMAND_MEM_ENABLE; 244 csc->sc_bar_reg = RTW_PCI_MMBA; 245 csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM; 246 } else if (Cardbus_mapreg_map(ct, RTW_PCI_IOBA, PCI_MAPREG_TYPE_IO, 247 0, ®s->r_bt, ®s->r_bh, &adr, ®s->r_sz) == 0) { 248 RTW_DPRINTF(RTW_DEBUG_ATTACH, 249 ("%s: %s mapped %" PRIuMAX " bytes I/O space\n", 250 device_xname(self), __func__, (uintmax_t)regs->r_sz)); 251 csc->sc_csr |= PCI_COMMAND_IO_ENABLE; 252 csc->sc_bar_reg = RTW_PCI_IOBA; 253 csc->sc_bar_val = adr | PCI_MAPREG_TYPE_IO; 254 } else { 255 aprint_error_dev(self, "unable to map device registers\n"); 256 return; 257 } 258 259 /* 260 * Bring the chip out of powersave mode and initialize the 261 * configuration registers. 262 */ 263 rtw_cardbus_setup(csc); 264 265 /* Remember which interrupt line. */ 266 csc->sc_intrline = ca->ca_intrline; 267 268 /* 269 * Finish off the attach. 270 */ 271 rtw_attach(sc); 272 273 rtw_cardbus_funcregen(regs, 1); 274 275 RTW_WRITE(regs, RTW_FEMR, 0); 276 RTW_WRITE(regs, RTW_FER, RTW_READ(regs, RTW_FER)); 277 278 if (pmf_device_register(self, 279 rtw_cardbus_suspend, rtw_cardbus_resume)) { 280 pmf_class_network_register(self, &sc->sc_if); 281 /* 282 * Power down the socket. 283 */ 284 pmf_device_suspend(self, &sc->sc_qual); 285 } else 286 aprint_error_dev(self, "couldn't establish power handler\n"); 287 } 288 289 int 290 rtw_cardbus_detach(device_t self, int flags) 291 { 292 struct rtw_cardbus_softc *csc = device_private(self); 293 struct rtw_softc *sc = &csc->sc_rtw; 294 struct rtw_regs *regs = &sc->sc_regs; 295 struct cardbus_devfunc *ct = csc->sc_ct; 296 int rc; 297 298 #if defined(DIAGNOSTIC) 299 if (ct == NULL) 300 panic("%s: data structure lacks", device_xname(self)); 301 #endif 302 303 if ((rc = rtw_detach(sc)) != 0) 304 return rc; 305 306 /* 307 * Unhook the interrupt handler. 308 */ 309 if (csc->sc_ih != NULL) 310 Cardbus_intr_disestablish(ct, csc->sc_ih); 311 312 /* 313 * Release bus space and close window. 314 */ 315 if (csc->sc_bar_reg != 0) 316 Cardbus_mapreg_unmap(ct, csc->sc_bar_reg, 317 regs->r_bt, regs->r_bh, regs->r_sz); 318 319 return 0; 320 } 321 322 bool 323 rtw_cardbus_resume(device_t self, const pmf_qual_t *qual) 324 { 325 struct rtw_cardbus_softc *csc = device_private(self); 326 struct rtw_softc *sc = &csc->sc_rtw; 327 cardbus_devfunc_t ct = csc->sc_ct; 328 329 /* 330 * Map and establish the interrupt. 331 */ 332 csc->sc_ih = Cardbus_intr_establish(ct, csc->sc_intrline, IPL_NET, 333 rtw_intr, sc); 334 if (csc->sc_ih == NULL) { 335 aprint_error_dev(sc->sc_dev, 336 "unable to establish interrupt\n"); 337 return false; 338 } 339 340 rtw_cardbus_funcregen(&sc->sc_regs, 1); 341 342 RTW_WRITE(&sc->sc_regs, RTW_FEMR, RTW_FEMR_INTR); 343 RTW_WRITE(&sc->sc_regs, RTW_FER, RTW_FER_INTR); 344 345 return rtw_resume(self, qual); 346 } 347 348 bool 349 rtw_cardbus_suspend(device_t self, const pmf_qual_t *qual) 350 { 351 struct rtw_cardbus_softc *csc = device_private(self); 352 struct rtw_softc *sc = &csc->sc_rtw; 353 cardbus_devfunc_t ct = csc->sc_ct; 354 355 if (!rtw_suspend(self, qual)) 356 return false; 357 358 RTW_WRITE(&sc->sc_regs, RTW_FEMR, 359 RTW_READ(&sc->sc_regs, RTW_FEMR) & ~RTW_FEMR_INTR); 360 361 rtw_cardbus_funcregen(&sc->sc_regs, 0); 362 363 /* Unhook the interrupt handler. */ 364 Cardbus_intr_disestablish(ct, csc->sc_ih); 365 csc->sc_ih = NULL; 366 return true; 367 } 368 369 void 370 rtw_cardbus_setup(struct rtw_cardbus_softc *csc) 371 { 372 pcitag_t tag = csc->sc_tag; 373 cardbus_devfunc_t ct = csc->sc_ct; 374 pcireg_t bhlc, csr, lattimer; 375 376 (void)cardbus_set_powerstate(ct, tag, PCI_PWR_D0); 377 378 /* I believe the datasheet tries to warn us that the RTL8180 379 * wants for 16 (0x10) to divide the latency timer. 380 */ 381 bhlc = Cardbus_conf_read(ct, tag, PCI_BHLC_REG); 382 lattimer = rounddown(PCI_LATTIMER(bhlc), 0x10); 383 if (PCI_LATTIMER(bhlc) != lattimer) { 384 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 385 bhlc |= (lattimer << PCI_LATTIMER_SHIFT); 386 Cardbus_conf_write(ct, tag, PCI_BHLC_REG, bhlc); 387 } 388 389 /* Program the BAR. */ 390 Cardbus_conf_write(ct, tag, csc->sc_bar_reg, csc->sc_bar_val); 391 392 /* Enable the appropriate bits in the PCI CSR. */ 393 csr = Cardbus_conf_read(ct, tag, PCI_COMMAND_STATUS_REG); 394 csr &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE); 395 csr |= csc->sc_csr; 396 Cardbus_conf_write(ct, tag, PCI_COMMAND_STATUS_REG, csr); 397 } 398
Indexes created Wed Oct 22 13:09:56 GMT 2025