njs_cardbus.c revision 1.7.4.4
1 /* $NetBSD: njs_cardbus.c,v 1.7.4.4 2010/03/11 15:03:25 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by ITOH Yasufumi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: njs_cardbus.c,v 1.7.4.4 2010/03/11 15:03:25 yamt Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 40 #include <sys/bus.h> 41 #include <sys/intr.h> 42 43 #include <dev/scsipi/scsi_all.h> 44 #include <dev/scsipi/scsipi_all.h> 45 #include <dev/scsipi/scsiconf.h> 46 47 #include <dev/cardbus/cardbusvar.h> 48 #include <dev/pci/pcidevs.h> 49 50 #include <dev/ic/ninjascsi32reg.h> 51 #include <dev/ic/ninjascsi32var.h> 52 53 #define NJSC32_CARDBUS_BASEADDR_IO PCI_BAR0 54 #define NJSC32_CARDBUS_BASEADDR_MEM PCI_BAR1 55 56 struct njsc32_cardbus_softc { 57 struct njsc32_softc sc_njsc32; 58 59 /* CardBus-specific goo */ 60 cardbus_devfunc_t sc_ct; /* our CardBus devfuncs */ 61 pcitag_t sc_tag; 62 63 bus_space_handle_t sc_regmaph; 64 bus_size_t sc_regmap_size; 65 }; 66 67 static int njs_cardbus_match(device_t, cfdata_t, void *); 68 static void njs_cardbus_attach(device_t, device_t, void *); 69 static int njs_cardbus_detach(device_t, int); 70 71 CFATTACH_DECL_NEW(njs_cardbus, sizeof(struct njsc32_cardbus_softc), 72 njs_cardbus_match, njs_cardbus_attach, njs_cardbus_detach, NULL); 73 74 static const struct njsc32_cardbus_product { 75 pci_vendor_id_t p_vendor; 76 pci_product_id_t p_product; 77 njsc32_model_t p_model; 78 int p_clk; /* one of NJSC32_CLK_* */ 79 } njsc32_cardbus_products[] = { 80 { PCI_VENDOR_IODATA, PCI_PRODUCT_IODATA_CBSCII, 81 NJSC32_MODEL_32BI, NJSC32_CLK_40M }, 82 { PCI_VENDOR_WORKBIT, PCI_PRODUCT_WORKBIT_NJSC32BI, 83 NJSC32_MODEL_32BI, NJSC32_CLK_40M }, 84 { PCI_VENDOR_WORKBIT, PCI_PRODUCT_WORKBIT_NJSC32UDE, 85 NJSC32_MODEL_32UDE | NJSC32_FLAG_DUALEDGE, NJSC32_CLK_40M }, 86 { PCI_VENDOR_WORKBIT, PCI_PRODUCT_WORKBIT_NJSC32BI_KME, 87 NJSC32_MODEL_32BI, NJSC32_CLK_40M }, 88 89 { 0, 0, 90 NJSC32_MODEL_INVALID, 0 }, 91 }; 92 93 static const struct njsc32_cardbus_product * 94 njs_cardbus_lookup(const struct cardbus_attach_args *ca) 95 { 96 const struct njsc32_cardbus_product *p; 97 98 for (p = njsc32_cardbus_products; 99 p->p_model != NJSC32_MODEL_INVALID; p++) { 100 if (PCI_VENDOR(ca->ca_id) == p->p_vendor && 101 PCI_PRODUCT(ca->ca_id) == p->p_product) 102 return p; 103 } 104 105 return NULL; 106 } 107 108 static int 109 njs_cardbus_match(device_t parent, cfdata_t match, void *aux) 110 { 111 struct cardbus_attach_args *ca = aux; 112 113 if (njs_cardbus_lookup(ca)) 114 return 1; 115 116 return 0; 117 } 118 119 static void 120 njs_cardbus_attach(device_t parent, device_t self, void *aux) 121 { 122 struct cardbus_attach_args *ca = aux; 123 struct njsc32_cardbus_softc *csc = device_private(self); 124 struct njsc32_softc *sc = &csc->sc_njsc32; 125 const struct njsc32_cardbus_product *prod; 126 cardbus_devfunc_t ct = ca->ca_ct; 127 cardbus_chipset_tag_t cc = ct->ct_cc; 128 cardbus_function_tag_t cf = ct->ct_cf; 129 pcireg_t reg; 130 int csr; 131 u_int8_t latency = 0x20; 132 133 if ((prod = njs_cardbus_lookup(ca)) == NULL) 134 panic("njs_cardbus_attach"); 135 136 printf(": Workbit NinjaSCSI-32 SCSI adapter\n"); 137 sc->sc_dev = self; 138 sc->sc_model = prod->p_model; 139 sc->sc_clk = prod->p_clk; 140 141 csc->sc_ct = ct; 142 csc->sc_tag = ca->ca_tag; 143 144 /* 145 * Map the device. 146 */ 147 csr = PCI_COMMAND_MASTER_ENABLE; 148 149 /* 150 * Map registers. 151 * Try memory map first, and then try I/O. 152 */ 153 if (Cardbus_mapreg_map(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_MEM, 154 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 155 &sc->sc_regt, &csc->sc_regmaph, NULL, &csc->sc_regmap_size) == 0) { 156 if (bus_space_subregion(sc->sc_regt, csc->sc_regmaph, 157 NJSC32_MEMOFFSET_REG, NJSC32_REGSIZE, &sc->sc_regh) != 0) { 158 /* failed -- undo map and try I/O */ 159 Cardbus_mapreg_unmap(csc->sc_ct, 160 NJSC32_CARDBUS_BASEADDR_MEM, 161 sc->sc_regt, csc->sc_regmaph, csc->sc_regmap_size); 162 goto try_io; 163 } 164 #ifdef NJSC32_DEBUG 165 printf("%s: memory space mapped\n", device_xname(self)); 166 #endif 167 csr |= PCI_COMMAND_MEM_ENABLE; 168 sc->sc_flags = NJSC32_MEM_MAPPED; 169 } else { 170 try_io: 171 if (Cardbus_mapreg_map(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_IO, 172 PCI_MAPREG_TYPE_IO, 0, &sc->sc_regt, &sc->sc_regh, 173 NULL, &csc->sc_regmap_size) == 0) { 174 #ifdef NJSC32_DEBUG 175 printf("%s: io space mapped\n", device_xname(self)); 176 #endif 177 csr |= PCI_COMMAND_IO_ENABLE; 178 sc->sc_flags = NJSC32_IO_MAPPED; 179 } else { 180 aprint_error_dev(self, "unable to map device registers\n"); 181 return; 182 } 183 } 184 185 /* Enable the appropriate bits in the PCI CSR. */ 186 reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG); 187 reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE); 188 reg |= csr; 189 Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg); 190 191 /* 192 * Make sure the latency timer is set to some reasonable 193 * value. 194 */ 195 reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_BHLC_REG); 196 if (PCI_LATTIMER(reg) < latency) { 197 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 198 reg |= (latency << PCI_LATTIMER_SHIFT); 199 Cardbus_conf_write(ct, ca->ca_tag, PCI_BHLC_REG, reg); 200 } 201 202 sc->sc_dmat = ca->ca_dmat; 203 204 /* 205 * Establish the interrupt. 206 */ 207 sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_BIO, 208 njsc32_intr, sc); 209 if (sc->sc_ih == NULL) { 210 aprint_error_dev(self, 211 "unable to establish interrupt\n"); 212 return; 213 } 214 215 /* CardBus device cannot supply termination power. */ 216 sc->sc_flags |= NJSC32_CANNOT_SUPPLY_TERMPWR; 217 218 /* attach */ 219 njsc32_attach(sc); 220 } 221 222 static int 223 njs_cardbus_detach(device_t self, int flags) 224 { 225 struct njsc32_cardbus_softc *csc = device_private(self); 226 struct njsc32_softc *sc = &csc->sc_njsc32; 227 int rv; 228 229 rv = njsc32_detach(sc, flags); 230 if (rv) 231 return rv; 232 233 if (sc->sc_ih) 234 cardbus_intr_disestablish(csc->sc_ct->ct_cc, 235 csc->sc_ct->ct_cf, sc->sc_ih); 236 237 if (sc->sc_flags & NJSC32_IO_MAPPED) 238 Cardbus_mapreg_unmap(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_IO, 239 sc->sc_regt, sc->sc_regh, csc->sc_regmap_size); 240 if (sc->sc_flags & NJSC32_MEM_MAPPED) 241 Cardbus_mapreg_unmap(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_MEM, 242 sc->sc_regt, csc->sc_regmaph, csc->sc_regmap_size); 243 244 return 0; 245 } 246
Indexes created Mon Oct 27 17:09:47 GMT 2025