njs_cardbus.c revision 1.8.4.1
1 /* $NetBSD: njs_cardbus.c,v 1.8.4.1 2008/06/27 15:11:21 simonb Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by ITOH Yasufumi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: njs_cardbus.c,v 1.8.4.1 2008/06/27 15:11:21 simonb Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 40 #include <sys/bus.h> 41 #include <sys/intr.h> 42 43 #include <dev/scsipi/scsi_all.h> 44 #include <dev/scsipi/scsipi_all.h> 45 #include <dev/scsipi/scsiconf.h> 46 47 #include <dev/cardbus/cardbusvar.h> 48 #include <dev/pci/pcidevs.h> 49 50 #include <dev/ic/ninjascsi32reg.h> 51 #include <dev/ic/ninjascsi32var.h> 52 53 #define NJSC32_CARDBUS_BASEADDR_IO CARDBUS_BASE0_REG 54 #define NJSC32_CARDBUS_BASEADDR_MEM CARDBUS_BASE1_REG 55 56 struct njsc32_cardbus_softc { 57 struct njsc32_softc sc_njsc32; 58 59 /* CardBus-specific goo */ 60 cardbus_devfunc_t sc_ct; /* our CardBus devfuncs */ 61 cardbus_intr_line_t sc_intrline; /* our interrupt line */ 62 cardbustag_t sc_tag; 63 64 bus_space_handle_t sc_regmaph; 65 bus_size_t sc_regmap_size; 66 }; 67 68 static int njs_cardbus_match(struct device *, struct cfdata *, void *); 69 static void njs_cardbus_attach(struct device *, struct device *, void *); 70 static int njs_cardbus_detach(struct device *, int); 71 72 CFATTACH_DECL(njs_cardbus, sizeof(struct njsc32_cardbus_softc), 73 njs_cardbus_match, njs_cardbus_attach, njs_cardbus_detach, NULL); 74 75 static const struct njsc32_cardbus_product { 76 cardbus_vendor_id_t p_vendor; 77 cardbus_product_id_t p_product; 78 njsc32_model_t p_model; 79 int p_clk; /* one of NJSC32_CLK_* */ 80 } njsc32_cardbus_products[] = { 81 { PCI_VENDOR_IODATA, PCI_PRODUCT_IODATA_CBSCII, 82 NJSC32_MODEL_32BI, NJSC32_CLK_40M }, 83 { PCI_VENDOR_WORKBIT, PCI_PRODUCT_WORKBIT_NJSC32BI, 84 NJSC32_MODEL_32BI, NJSC32_CLK_40M }, 85 { PCI_VENDOR_WORKBIT, PCI_PRODUCT_WORKBIT_NJSC32UDE, 86 NJSC32_MODEL_32UDE | NJSC32_FLAG_DUALEDGE, NJSC32_CLK_40M }, 87 { PCI_VENDOR_WORKBIT, PCI_PRODUCT_WORKBIT_NJSC32BI_KME, 88 NJSC32_MODEL_32BI, NJSC32_CLK_40M }, 89 90 { 0, 0, 91 NJSC32_MODEL_INVALID, 0 }, 92 }; 93 94 static const struct njsc32_cardbus_product * 95 njs_cardbus_lookup(const struct cardbus_attach_args *ca) 96 { 97 const struct njsc32_cardbus_product *p; 98 99 for (p = njsc32_cardbus_products; 100 p->p_model != NJSC32_MODEL_INVALID; p++) { 101 if (CARDBUS_VENDOR(ca->ca_id) == p->p_vendor && 102 CARDBUS_PRODUCT(ca->ca_id) == p->p_product) 103 return p; 104 } 105 106 return NULL; 107 } 108 109 static int 110 njs_cardbus_match(struct device *parent, struct cfdata *match, 111 void *aux) 112 { 113 struct cardbus_attach_args *ca = aux; 114 115 if (njs_cardbus_lookup(ca)) 116 return 1; 117 118 return 0; 119 } 120 121 static void 122 njs_cardbus_attach(struct device *parent, struct device *self, 123 void *aux) 124 { 125 struct cardbus_attach_args *ca = aux; 126 struct njsc32_cardbus_softc *csc = (void *) self; 127 struct njsc32_softc *sc = &csc->sc_njsc32; 128 const struct njsc32_cardbus_product *prod; 129 cardbus_devfunc_t ct = ca->ca_ct; 130 cardbus_chipset_tag_t cc = ct->ct_cc; 131 cardbus_function_tag_t cf = ct->ct_cf; 132 pcireg_t reg; 133 int csr; 134 u_int8_t latency = 0x20; 135 136 if ((prod = njs_cardbus_lookup(ca)) == NULL) 137 panic("njs_cardbus_attach"); 138 139 printf(": Workbit NinjaSCSI-32 SCSI adapter\n"); 140 sc->sc_model = prod->p_model; 141 sc->sc_clk = prod->p_clk; 142 143 csc->sc_ct = ct; 144 csc->sc_tag = ca->ca_tag; 145 csc->sc_intrline = ca->ca_intrline; 146 147 /* 148 * Map the device. 149 */ 150 csr = PCI_COMMAND_MASTER_ENABLE; 151 152 /* 153 * Map registers. 154 * Try memory map first, and then try I/O. 155 */ 156 if (Cardbus_mapreg_map(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_MEM, 157 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 158 &sc->sc_regt, &csc->sc_regmaph, NULL, &csc->sc_regmap_size) == 0) { 159 if (bus_space_subregion(sc->sc_regt, csc->sc_regmaph, 160 NJSC32_MEMOFFSET_REG, NJSC32_REGSIZE, &sc->sc_regh) != 0) { 161 /* failed -- undo map and try I/O */ 162 Cardbus_mapreg_unmap(csc->sc_ct, 163 NJSC32_CARDBUS_BASEADDR_MEM, 164 sc->sc_regt, csc->sc_regmaph, csc->sc_regmap_size); 165 goto try_io; 166 } 167 #ifdef NJSC32_DEBUG 168 printf("%s: memory space mapped\n", device_xname(&sc->sc_dev)); 169 #endif 170 csr |= PCI_COMMAND_MEM_ENABLE; 171 sc->sc_flags = NJSC32_MEM_MAPPED; 172 (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE); 173 } else { 174 try_io: 175 if (Cardbus_mapreg_map(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_IO, 176 PCI_MAPREG_TYPE_IO, 0, &sc->sc_regt, &sc->sc_regh, 177 NULL, &csc->sc_regmap_size) == 0) { 178 #ifdef NJSC32_DEBUG 179 printf("%s: io space mapped\n", device_xname(&sc->sc_dev)); 180 #endif 181 csr |= PCI_COMMAND_IO_ENABLE; 182 sc->sc_flags = NJSC32_IO_MAPPED; 183 (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_IO_ENABLE); 184 } else { 185 aprint_error_dev(&sc->sc_dev, "unable to map device registers\n"); 186 return; 187 } 188 } 189 190 /* Make sure the right access type is on the CardBus bridge. */ 191 (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); 192 193 /* Enable the appropriate bits in the PCI CSR. */ 194 reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG); 195 reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE); 196 reg |= csr; 197 cardbus_conf_write(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg); 198 199 /* 200 * Make sure the latency timer is set to some reasonable 201 * value. 202 */ 203 reg = cardbus_conf_read(cc, cf, ca->ca_tag, CARDBUS_BHLC_REG); 204 if (CARDBUS_LATTIMER(reg) < latency) { 205 reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT); 206 reg |= (latency << CARDBUS_LATTIMER_SHIFT); 207 cardbus_conf_write(cc, cf, ca->ca_tag, CARDBUS_BHLC_REG, reg); 208 } 209 210 sc->sc_dmat = ca->ca_dmat; 211 212 /* 213 * Establish the interrupt. 214 */ 215 sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_BIO, 216 njsc32_intr, sc); 217 if (sc->sc_ih == NULL) { 218 aprint_error_dev(&sc->sc_dev, 219 "unable to establish interrupt\n"); 220 return; 221 } 222 223 /* CardBus device cannot supply termination power. */ 224 sc->sc_flags |= NJSC32_CANNOT_SUPPLY_TERMPWR; 225 226 /* attach */ 227 njsc32_attach(sc); 228 } 229 230 static int 231 njs_cardbus_detach(struct device *self, int flags) 232 { 233 struct njsc32_cardbus_softc *csc = (void *) self; 234 struct njsc32_softc *sc = &csc->sc_njsc32; 235 int rv; 236 237 rv = njsc32_detach(sc, flags); 238 if (rv) 239 return rv; 240 241 if (sc->sc_ih) 242 cardbus_intr_disestablish(csc->sc_ct->ct_cc, 243 csc->sc_ct->ct_cf, sc->sc_ih); 244 245 if (sc->sc_flags & NJSC32_IO_MAPPED) 246 Cardbus_mapreg_unmap(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_IO, 247 sc->sc_regt, sc->sc_regh, csc->sc_regmap_size); 248 if (sc->sc_flags & NJSC32_MEM_MAPPED) 249 Cardbus_mapreg_unmap(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_MEM, 250 sc->sc_regt, csc->sc_regmaph, csc->sc_regmap_size); 251 252 return 0; 253 } 254
Indexes created Sat Oct 25 16:10:12 GMT 2025