rbus_ppb.c revision 1.1.4.5 1 1.1.4.5 nathanw /* $NetBSD: rbus_ppb.c,v 1.1.4.5 2002/10/18 02:41:34 nathanw Exp $ */
2 1.1.4.2 nathanw
3 1.1.4.2 nathanw /*
4 1.1.4.2 nathanw * Copyright (c) 1999 The NetBSD Foundation, Inc.
5 1.1.4.2 nathanw * All rights reserved.
6 1.1.4.2 nathanw *
7 1.1.4.2 nathanw * This code is derived from software contributed to The NetBSD Foundation
8 1.1.4.2 nathanw * by Michael Richardson <mcr (at) sandelman.ottawa.on.ca>
9 1.1.4.2 nathanw *
10 1.1.4.2 nathanw * Redistribution and use in source and binary forms, with or without
11 1.1.4.2 nathanw * modification, are permitted provided that the following conditions
12 1.1.4.2 nathanw * are met:
13 1.1.4.2 nathanw * 1. Redistributions of source code must retain the above copyright
14 1.1.4.2 nathanw * notice, this list of conditions and the following disclaimer.
15 1.1.4.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright
16 1.1.4.2 nathanw * notice, this list of conditions and the following disclaimer in the
17 1.1.4.2 nathanw * documentation and/or other materials provided with the distribution.
18 1.1.4.2 nathanw * 3. All advertising materials mentioning features or use of this software
19 1.1.4.2 nathanw * must display the following acknowledgement:
20 1.1.4.2 nathanw * This product includes software developed by the NetBSD
21 1.1.4.2 nathanw * Foundation, Inc. and its contributors.
22 1.1.4.2 nathanw * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.1.4.2 nathanw * contributors may be used to endorse or promote products derived
24 1.1.4.2 nathanw * from this software without specific prior written permission.
25 1.1.4.2 nathanw *
26 1.1.4.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.1.4.2 nathanw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.1.4.2 nathanw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1.4.2 nathanw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.1.4.2 nathanw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.1.4.2 nathanw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.1.4.2 nathanw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.1.4.2 nathanw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.1.4.2 nathanw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.1.4.2 nathanw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.1.4.2 nathanw * POSSIBILITY OF SUCH DAMAGE.
37 1.1.4.2 nathanw */
38 1.1.4.2 nathanw
39 1.1.4.2 nathanw /*
40 1.1.4.2 nathanw * CardBus front-end for the Intel/Digital DECchip 21152 PCI-PCI bridge
41 1.1.4.2 nathanw */
42 1.1.4.2 nathanw
43 1.1.4.3 nathanw #include <sys/cdefs.h>
44 1.1.4.5 nathanw __KERNEL_RCSID(0, "$NetBSD: rbus_ppb.c,v 1.1.4.5 2002/10/18 02:41:34 nathanw Exp $");
45 1.1.4.3 nathanw
46 1.1.4.2 nathanw #include <sys/param.h>
47 1.1.4.2 nathanw #include <sys/systm.h>
48 1.1.4.2 nathanw #include <sys/mbuf.h>
49 1.1.4.2 nathanw #include <sys/malloc.h>
50 1.1.4.2 nathanw #include <sys/kernel.h>
51 1.1.4.2 nathanw #include <sys/socket.h>
52 1.1.4.2 nathanw #include <sys/ioctl.h>
53 1.1.4.2 nathanw #include <sys/errno.h>
54 1.1.4.2 nathanw #include <sys/device.h>
55 1.1.4.2 nathanw
56 1.1.4.2 nathanw #if NRND > 0
57 1.1.4.2 nathanw #include <sys/rnd.h>
58 1.1.4.2 nathanw #endif
59 1.1.4.2 nathanw
60 1.1.4.2 nathanw #include <machine/endian.h>
61 1.1.4.2 nathanw
62 1.1.4.2 nathanw #include <machine/bus.h>
63 1.1.4.2 nathanw #include <machine/intr.h>
64 1.1.4.2 nathanw
65 1.1.4.2 nathanw #include <dev/pci/pcivar.h>
66 1.1.4.2 nathanw #include <dev/pci/pcireg.h>
67 1.1.4.2 nathanw #include <dev/pci/pcidevs.h>
68 1.1.4.2 nathanw #include <dev/pci/ppbreg.h>
69 1.1.4.2 nathanw
70 1.1.4.2 nathanw #include <dev/ic/i82365reg.h>
71 1.1.4.2 nathanw #include <dev/ic/i82365var.h>
72 1.1.4.2 nathanw
73 1.1.4.2 nathanw #include <dev/pci/pccbbreg.h>
74 1.1.4.2 nathanw #include <dev/pci/pccbbvar.h>
75 1.1.4.2 nathanw
76 1.1.4.2 nathanw #include <dev/cardbus/cardbusvar.h>
77 1.1.4.2 nathanw #include <dev/cardbus/cardbusdevs.h>
78 1.1.4.2 nathanw
79 1.1.4.2 nathanw #include <i386/pci/pci_addr_fixup.h>
80 1.1.4.2 nathanw #include <i386/pci/pci_bus_fixup.h>
81 1.1.4.2 nathanw #include <i386/pci/pci_intr_fixup.h>
82 1.1.4.2 nathanw #include <i386/pci/pcibios.h>
83 1.1.4.2 nathanw
84 1.1.4.2 nathanw struct ppb_softc;
85 1.1.4.2 nathanw
86 1.1.4.2 nathanw static int ppb_cardbus_match __P((struct device *, struct cfdata *, void *));
87 1.1.4.2 nathanw static void ppb_cardbus_attach __P((struct device *, struct device *, void *));
88 1.1.4.2 nathanw static int ppb_cardbus_detach __P((struct device * self, int flags));
89 1.1.4.2 nathanw /*static*/ void ppb_cardbus_setup __P((struct ppb_softc * sc));
90 1.1.4.2 nathanw /*static*/ int ppb_cardbus_enable __P((struct ppb_softc * sc));
91 1.1.4.2 nathanw /*static*/ void ppb_cardbus_disable __P((struct ppb_softc * sc));
92 1.1.4.2 nathanw static int ppb_activate __P((struct device *self, enum devact act));
93 1.1.4.2 nathanw int rppbprint __P((void *aux, const char *pnp));
94 1.1.4.2 nathanw int rbus_intr_fixup __P((pci_chipset_tag_t pc, int minbus,
95 1.1.4.2 nathanw int maxbus, int line));
96 1.1.4.2 nathanw void rbus_do_header_fixup __P((pci_chipset_tag_t pc, pcitag_t tag,
97 1.1.4.2 nathanw void *context));
98 1.1.4.2 nathanw
99 1.1.4.2 nathanw static void rbus_pci_phys_allocate __P((pci_chipset_tag_t pc,
100 1.1.4.2 nathanw pcitag_t tag,
101 1.1.4.2 nathanw void *context));
102 1.1.4.2 nathanw
103 1.1.4.2 nathanw static int rbus_do_phys_allocate __P((pci_chipset_tag_t pc,
104 1.1.4.2 nathanw pcitag_t tag,
105 1.1.4.2 nathanw int mapreg,
106 1.1.4.2 nathanw void *ctx,
107 1.1.4.2 nathanw int type,
108 1.1.4.2 nathanw bus_addr_t *addr,
109 1.1.4.2 nathanw bus_size_t size));
110 1.1.4.2 nathanw
111 1.1.4.2 nathanw static void rbus_pci_phys_countspace __P((pci_chipset_tag_t pc,
112 1.1.4.2 nathanw pcitag_t tag,
113 1.1.4.2 nathanw void *context));
114 1.1.4.2 nathanw
115 1.1.4.2 nathanw static int rbus_do_phys_countspace __P((pci_chipset_tag_t pc,
116 1.1.4.2 nathanw pcitag_t tag,
117 1.1.4.2 nathanw int mapreg,
118 1.1.4.2 nathanw void *ctx,
119 1.1.4.2 nathanw int type,
120 1.1.4.2 nathanw bus_addr_t *addr,
121 1.1.4.2 nathanw bus_size_t size));
122 1.1.4.2 nathanw
123 1.1.4.2 nathanw unsigned int rbus_round_up __P((unsigned int size, unsigned int min));
124 1.1.4.2 nathanw
125 1.1.4.2 nathanw
126 1.1.4.2 nathanw struct ppb_cardbus_softc {
127 1.1.4.2 nathanw struct device sc_dev;
128 1.1.4.4 nathanw pcitag_t sc_tag;
129 1.1.4.2 nathanw int foo;
130 1.1.4.2 nathanw };
131 1.1.4.2 nathanw
132 1.1.4.5 nathanw CFATTACH_DECL(rbus_ppb, sizeof(struct ppb_cardbus_softc),
133 1.1.4.5 nathanw ppb_cardbus_match, ppb_cardbus_attach, ppb_cardbus_detach, ppb_activate);
134 1.1.4.2 nathanw
135 1.1.4.2 nathanw #ifdef CBB_DEBUG
136 1.1.4.2 nathanw int rbus_ppb_debug = 0; /* hack with kdb */
137 1.1.4.2 nathanw #define DPRINTF(X) if(rbus_ppb_debug) printf X
138 1.1.4.2 nathanw #else
139 1.1.4.2 nathanw #define DPRINTF(X)
140 1.1.4.2 nathanw #endif
141 1.1.4.2 nathanw
142 1.1.4.2 nathanw static int
143 1.1.4.2 nathanw ppb_cardbus_match(parent, match, aux)
144 1.1.4.2 nathanw struct device *parent;
145 1.1.4.2 nathanw struct cfdata *match;
146 1.1.4.2 nathanw void *aux;
147 1.1.4.2 nathanw {
148 1.1.4.2 nathanw struct cardbus_attach_args *ca = aux;
149 1.1.4.2 nathanw
150 1.1.4.2 nathanw if (CARDBUS_VENDOR(ca->ca_id) == PCI_VENDOR_DEC &&
151 1.1.4.2 nathanw CARDBUS_PRODUCT(ca->ca_id) == PCI_PRODUCT_DEC_21152)
152 1.1.4.2 nathanw return (1);
153 1.1.4.2 nathanw
154 1.1.4.2 nathanw if(PCI_CLASS(ca->ca_class) == PCI_CLASS_BRIDGE &&
155 1.1.4.2 nathanw PCI_SUBCLASS(ca->ca_class) == PCI_SUBCLASS_BRIDGE_PCI) {
156 1.1.4.2 nathanw /* XXX */
157 1.1.4.2 nathanw printf("recognizing generic bridge chip\n");
158 1.1.4.2 nathanw }
159 1.1.4.2 nathanw
160 1.1.4.2 nathanw return (0);
161 1.1.4.2 nathanw }
162 1.1.4.2 nathanw
163 1.1.4.2 nathanw
164 1.1.4.2 nathanw int
165 1.1.4.2 nathanw rppbprint(aux, pnp)
166 1.1.4.2 nathanw void *aux;
167 1.1.4.2 nathanw const char *pnp;
168 1.1.4.2 nathanw {
169 1.1.4.2 nathanw struct pcibus_attach_args *pba = aux;
170 1.1.4.2 nathanw
171 1.1.4.2 nathanw /* only PCIs can attach to PPBs; easy. */
172 1.1.4.2 nathanw if (pnp)
173 1.1.4.2 nathanw printf("pci at %s", pnp);
174 1.1.4.2 nathanw printf(" bus %d (rbus)", pba->pba_bus);
175 1.1.4.2 nathanw return (UNCONF);
176 1.1.4.2 nathanw }
177 1.1.4.2 nathanw
178 1.1.4.2 nathanw int
179 1.1.4.2 nathanw rbus_intr_fixup(pci_chipset_tag_t pc,
180 1.1.4.2 nathanw int minbus,
181 1.1.4.2 nathanw int maxbus,
182 1.1.4.2 nathanw int line)
183 1.1.4.2 nathanw {
184 1.1.4.2 nathanw pci_device_foreach_min(pc, minbus,
185 1.1.4.2 nathanw maxbus, rbus_do_header_fixup, (void *)&line);
186 1.1.4.2 nathanw return 0;
187 1.1.4.2 nathanw }
188 1.1.4.2 nathanw
189 1.1.4.2 nathanw void
190 1.1.4.2 nathanw rbus_do_header_fixup(pc, tag, context)
191 1.1.4.2 nathanw pci_chipset_tag_t pc;
192 1.1.4.2 nathanw pcitag_t tag;
193 1.1.4.2 nathanw void *context;
194 1.1.4.2 nathanw {
195 1.1.4.2 nathanw int pin, irq;
196 1.1.4.2 nathanw int bus, device, function;
197 1.1.4.2 nathanw pcireg_t intr, id;
198 1.1.4.2 nathanw int *pline = (int *)context;
199 1.1.4.2 nathanw int line = *pline;
200 1.1.4.2 nathanw
201 1.1.4.2 nathanw pci_decompose_tag(pc, tag, &bus, &device, &function);
202 1.1.4.2 nathanw id = pci_conf_read(pc, tag, PCI_ID_REG);
203 1.1.4.2 nathanw
204 1.1.4.2 nathanw intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
205 1.1.4.2 nathanw pin = PCI_INTERRUPT_PIN(intr);
206 1.1.4.2 nathanw irq = PCI_INTERRUPT_LINE(intr);
207 1.1.4.2 nathanw
208 1.1.4.2 nathanw #if 0
209 1.1.4.2 nathanw printf("do_header %02x:%02x:%02x pin=%d => line %d\n",
210 1.1.4.2 nathanw bus, device, function, pin, line);
211 1.1.4.2 nathanw #endif
212 1.1.4.2 nathanw
213 1.1.4.2 nathanw intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);
214 1.1.4.2 nathanw intr |= (line << PCI_INTERRUPT_LINE_SHIFT);
215 1.1.4.2 nathanw pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr);
216 1.1.4.2 nathanw
217 1.1.4.2 nathanw }
218 1.1.4.2 nathanw
219 1.1.4.2 nathanw /*
220 1.1.4.2 nathanw * This function takes a range of PCI bus numbers and
221 1.1.4.2 nathanw * allocates space for all devices found in this space (the BARs) from
222 1.1.4.2 nathanw * the rbus space maps (I/O and memory).
223 1.1.4.2 nathanw *
224 1.1.4.2 nathanw * It assumes that "rbus" is defined. The whole concept does.
225 1.1.4.2 nathanw *
226 1.1.4.2 nathanw * It uses pci_device_foreach_min() to call rbus_pci_phys_allocate.
227 1.1.4.2 nathanw * This function is mostly stolen from
228 1.1.4.2 nathanw * pci_addr_fixup.c:pciaddr_resource_reserve.
229 1.1.4.2 nathanw *
230 1.1.4.2 nathanw */
231 1.1.4.2 nathanw struct rbus_pci_addr_fixup_context {
232 1.1.4.2 nathanw struct ppb_cardbus_softc *csc;
233 1.1.4.2 nathanw cardbus_chipset_tag_t ct;
234 1.1.4.2 nathanw struct cardbus_softc *sc;
235 1.1.4.2 nathanw struct cardbus_attach_args *caa;
236 1.1.4.2 nathanw int minbus;
237 1.1.4.2 nathanw int maxbus;
238 1.1.4.2 nathanw bus_size_t *bussize_ioreqs;
239 1.1.4.2 nathanw bus_size_t *bussize_memreqs;
240 1.1.4.2 nathanw rbus_tag_t *iobustags;
241 1.1.4.2 nathanw rbus_tag_t *membustags;
242 1.1.4.2 nathanw };
243 1.1.4.2 nathanw
244 1.1.4.2 nathanw unsigned int
245 1.1.4.2 nathanw rbus_round_up(unsigned int size, unsigned int min)
246 1.1.4.2 nathanw {
247 1.1.4.2 nathanw unsigned int power2;
248 1.1.4.2 nathanw
249 1.1.4.2 nathanw if(size == 0) {
250 1.1.4.2 nathanw return 0;
251 1.1.4.2 nathanw }
252 1.1.4.2 nathanw
253 1.1.4.2 nathanw power2=min;
254 1.1.4.2 nathanw
255 1.1.4.2 nathanw while(power2 < (1 << 31) &&
256 1.1.4.2 nathanw power2 < size) {
257 1.1.4.2 nathanw power2 = power2 << 1;
258 1.1.4.2 nathanw }
259 1.1.4.2 nathanw
260 1.1.4.2 nathanw return power2;
261 1.1.4.2 nathanw }
262 1.1.4.2 nathanw
263 1.1.4.2 nathanw static void
264 1.1.4.2 nathanw rbus_pci_addr_fixup(struct ppb_cardbus_softc *csc,
265 1.1.4.2 nathanw cardbus_chipset_tag_t ct,
266 1.1.4.2 nathanw struct cardbus_softc *sc,
267 1.1.4.2 nathanw pci_chipset_tag_t pc,
268 1.1.4.2 nathanw struct cardbus_attach_args *caa,
269 1.1.4.2 nathanw int minbus, int maxbus)
270 1.1.4.2 nathanw {
271 1.1.4.2 nathanw struct rbus_pci_addr_fixup_context rct;
272 1.1.4.2 nathanw int size, busnum;
273 1.1.4.2 nathanw bus_addr_t start;
274 1.1.4.2 nathanw bus_space_handle_t handle;
275 1.1.4.2 nathanw u_int32_t reg;
276 1.1.4.2 nathanw
277 1.1.4.2 nathanw rct.csc=csc;
278 1.1.4.2 nathanw rct.ct=ct;
279 1.1.4.2 nathanw rct.sc=sc;
280 1.1.4.2 nathanw rct.caa=caa;
281 1.1.4.2 nathanw rct.minbus = minbus;
282 1.1.4.2 nathanw rct.maxbus = maxbus;
283 1.1.4.2 nathanw size = sizeof(bus_size_t)*(maxbus+1);
284 1.1.4.2 nathanw rct.bussize_ioreqs = alloca(size);
285 1.1.4.2 nathanw rct.bussize_memreqs = alloca(size);
286 1.1.4.2 nathanw rct.iobustags = alloca(maxbus * sizeof(rbus_tag_t));
287 1.1.4.2 nathanw rct.membustags = alloca(maxbus * sizeof(rbus_tag_t));
288 1.1.4.2 nathanw
289 1.1.4.2 nathanw bzero(rct.bussize_ioreqs, size);
290 1.1.4.2 nathanw bzero(rct.bussize_memreqs, size);
291 1.1.4.2 nathanw
292 1.1.4.2 nathanw printf("%s: sizing buses %d-%d\n",
293 1.1.4.2 nathanw rct.csc->sc_dev.dv_xname,
294 1.1.4.2 nathanw minbus, maxbus);
295 1.1.4.2 nathanw
296 1.1.4.2 nathanw pci_device_foreach_min(pc, minbus, maxbus,
297 1.1.4.2 nathanw rbus_pci_phys_countspace, &rct);
298 1.1.4.2 nathanw
299 1.1.4.2 nathanw /*
300 1.1.4.2 nathanw * we need to determine amount of address space for each
301 1.1.4.2 nathanw * bus. To do this, we have to roll up amounts and then
302 1.1.4.2 nathanw * we need to divide up the cardbus's extent to allocate
303 1.1.4.2 nathanw * some space to each bus.
304 1.1.4.2 nathanw */
305 1.1.4.2 nathanw
306 1.1.4.2 nathanw for(busnum=maxbus; busnum > minbus; busnum--) {
307 1.1.4.2 nathanw if(pci_bus_parent[busnum] != 0) {
308 1.1.4.2 nathanw if(pci_bus_parent[busnum] < minbus ||
309 1.1.4.2 nathanw pci_bus_parent[busnum] >= maxbus) {
310 1.1.4.2 nathanw printf("%s: bus %d has illegal parent %d\n",
311 1.1.4.2 nathanw rct.csc->sc_dev.dv_xname,
312 1.1.4.2 nathanw busnum, pci_bus_parent[busnum]);
313 1.1.4.2 nathanw continue;
314 1.1.4.2 nathanw }
315 1.1.4.2 nathanw
316 1.1.4.2 nathanw /* first round amount of space up */
317 1.1.4.2 nathanw rct.bussize_ioreqs[busnum] =
318 1.1.4.2 nathanw rbus_round_up(rct.bussize_ioreqs[busnum], PPB_IO_MIN);
319 1.1.4.2 nathanw rct.bussize_ioreqs[pci_bus_parent[busnum]] +=
320 1.1.4.2 nathanw rct.bussize_ioreqs[busnum];
321 1.1.4.2 nathanw
322 1.1.4.2 nathanw rct.bussize_memreqs[busnum] =
323 1.1.4.2 nathanw rbus_round_up(rct.bussize_memreqs[busnum], PPB_MEM_MIN);
324 1.1.4.2 nathanw rct.bussize_memreqs[pci_bus_parent[busnum]] +=
325 1.1.4.2 nathanw rct.bussize_memreqs[busnum];
326 1.1.4.2 nathanw
327 1.1.4.2 nathanw }
328 1.1.4.2 nathanw }
329 1.1.4.2 nathanw
330 1.1.4.2 nathanw rct.bussize_ioreqs[minbus] =
331 1.1.4.2 nathanw rbus_round_up(rct.bussize_ioreqs[minbus], 4096);
332 1.1.4.2 nathanw rct.bussize_memreqs[minbus] =
333 1.1.4.2 nathanw rbus_round_up(rct.bussize_memreqs[minbus], 8);
334 1.1.4.2 nathanw
335 1.1.4.2 nathanw printf("%s: total needs IO %08lx and MEM %08lx\n",
336 1.1.4.2 nathanw rct.csc->sc_dev.dv_xname,
337 1.1.4.2 nathanw rct.bussize_ioreqs[minbus], rct.bussize_memreqs[minbus]);
338 1.1.4.2 nathanw
339 1.1.4.2 nathanw if(!caa->ca_rbus_iot) {
340 1.1.4.2 nathanw panic("no iot bus");
341 1.1.4.2 nathanw }
342 1.1.4.2 nathanw
343 1.1.4.2 nathanw if(rct.bussize_ioreqs[minbus]) {
344 1.1.4.2 nathanw if(rbus_space_alloc(caa->ca_rbus_iot, 0,
345 1.1.4.2 nathanw rct.bussize_ioreqs[minbus],
346 1.1.4.2 nathanw rct.bussize_ioreqs[minbus]-1 /* mask */,
347 1.1.4.2 nathanw rct.bussize_ioreqs[minbus] /* align */,
348 1.1.4.2 nathanw /* flags */ 0,
349 1.1.4.2 nathanw &start,
350 1.1.4.2 nathanw &handle) != 0) {
351 1.1.4.5 nathanw panic("rbus_ppb: can not allocate %ld bytes in IO bus %d",
352 1.1.4.2 nathanw rct.bussize_ioreqs[minbus], minbus);
353 1.1.4.2 nathanw }
354 1.1.4.2 nathanw rct.iobustags[minbus]=rbus_new(caa->ca_rbus_iot,
355 1.1.4.2 nathanw start,
356 1.1.4.2 nathanw rct.bussize_ioreqs[minbus],
357 1.1.4.2 nathanw 0 /* offset to add to physical address
358 1.1.4.2 nathanw to make processor address */,
359 1.1.4.2 nathanw RBUS_SPACE_DEDICATE);
360 1.1.4.2 nathanw }
361 1.1.4.2 nathanw
362 1.1.4.2 nathanw if(rct.bussize_memreqs[minbus]) {
363 1.1.4.2 nathanw if(rbus_space_alloc(caa->ca_rbus_memt, 0,
364 1.1.4.2 nathanw rct.bussize_memreqs[minbus],
365 1.1.4.2 nathanw rct.bussize_memreqs[minbus]-1 /* mask */,
366 1.1.4.2 nathanw rct.bussize_memreqs[minbus] /* align */,
367 1.1.4.2 nathanw /* flags */ 0,
368 1.1.4.2 nathanw &start,
369 1.1.4.2 nathanw &handle) != 0) {
370 1.1.4.5 nathanw panic("%s: can not allocate %ld bytes in MEM bus %d",
371 1.1.4.2 nathanw rct.csc->sc_dev.dv_xname,
372 1.1.4.2 nathanw rct.bussize_memreqs[minbus], minbus);
373 1.1.4.2 nathanw }
374 1.1.4.2 nathanw rct.membustags[minbus]=rbus_new(caa->ca_rbus_memt,
375 1.1.4.2 nathanw start,
376 1.1.4.2 nathanw rct.bussize_memreqs[minbus],
377 1.1.4.2 nathanw 0 /* offset to add to physical
378 1.1.4.2 nathanw address to make processor
379 1.1.4.2 nathanw address */,
380 1.1.4.2 nathanw RBUS_SPACE_DEDICATE);
381 1.1.4.2 nathanw }
382 1.1.4.2 nathanw
383 1.1.4.2 nathanw for(busnum=minbus+1; busnum <= maxbus; busnum++) {
384 1.1.4.2 nathanw int busparent;
385 1.1.4.2 nathanw
386 1.1.4.2 nathanw busparent = pci_bus_parent[busnum];
387 1.1.4.2 nathanw
388 1.1.4.2 nathanw printf("%s: bus %d (parent=%d) needs IO %08lx and MEM %08lx\n",
389 1.1.4.2 nathanw rct.csc->sc_dev.dv_xname,
390 1.1.4.2 nathanw busnum,
391 1.1.4.2 nathanw busparent,
392 1.1.4.2 nathanw rct.bussize_ioreqs[busnum],
393 1.1.4.2 nathanw rct.bussize_memreqs[busnum]);
394 1.1.4.2 nathanw
395 1.1.4.2 nathanw if(busparent > maxbus) {
396 1.1.4.2 nathanw panic("rbus_ppb: illegal parent");
397 1.1.4.2 nathanw }
398 1.1.4.2 nathanw
399 1.1.4.2 nathanw if(rct.bussize_ioreqs[busnum]) {
400 1.1.4.2 nathanw if(rbus_space_alloc(rct.iobustags[busparent],
401 1.1.4.2 nathanw 0,
402 1.1.4.2 nathanw rct.bussize_ioreqs[busnum],
403 1.1.4.2 nathanw rct.bussize_ioreqs[busnum]-1 /*mask */,
404 1.1.4.2 nathanw rct.bussize_ioreqs[busnum] /* align */,
405 1.1.4.2 nathanw /* flags */ 0,
406 1.1.4.2 nathanw &start,
407 1.1.4.2 nathanw &handle) != 0) {
408 1.1.4.5 nathanw panic("rbus_ppb: can not allocate %ld bytes in IO bus %d",
409 1.1.4.2 nathanw rct.bussize_ioreqs[busnum], busnum);
410 1.1.4.2 nathanw }
411 1.1.4.2 nathanw rct.iobustags[busnum]=rbus_new(rct.iobustags[busparent],
412 1.1.4.2 nathanw start,
413 1.1.4.2 nathanw rct.bussize_ioreqs[busnum],
414 1.1.4.2 nathanw 0 /* offset to add to physical
415 1.1.4.2 nathanw address
416 1.1.4.2 nathanw to make processor address */,
417 1.1.4.2 nathanw RBUS_SPACE_DEDICATE);
418 1.1.4.2 nathanw
419 1.1.4.2 nathanw /* program the bridge */
420 1.1.4.2 nathanw
421 1.1.4.2 nathanw /* enable I/O space */
422 1.1.4.2 nathanw reg = pci_conf_read(pc, pci_bus_tag[busnum],
423 1.1.4.2 nathanw PCI_COMMAND_STATUS_REG);
424 1.1.4.2 nathanw reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE;
425 1.1.4.2 nathanw pci_conf_write(pc, pci_bus_tag[busnum],
426 1.1.4.2 nathanw PCI_COMMAND_STATUS_REG, reg);
427 1.1.4.2 nathanw
428 1.1.4.2 nathanw /* now init the limit register for I/O */
429 1.1.4.2 nathanw pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_IOSTATUS,
430 1.1.4.2 nathanw (((start & 0xf000) >> 8) << PPB_IOBASE_SHIFT) |
431 1.1.4.2 nathanw ((((start +
432 1.1.4.2 nathanw rct.bussize_ioreqs[busnum] +
433 1.1.4.2 nathanw 4095) & 0xf000) >> 8) << PPB_IOLIMIT_SHIFT));
434 1.1.4.2 nathanw }
435 1.1.4.2 nathanw
436 1.1.4.2 nathanw if(rct.bussize_memreqs[busnum]) {
437 1.1.4.2 nathanw if(rbus_space_alloc(rct.membustags[busparent],
438 1.1.4.2 nathanw 0,
439 1.1.4.2 nathanw rct.bussize_memreqs[busnum] /* size */,
440 1.1.4.2 nathanw rct.bussize_memreqs[busnum]-1 /*mask */,
441 1.1.4.2 nathanw rct.bussize_memreqs[busnum] /* align */,
442 1.1.4.2 nathanw /* flags */ 0,
443 1.1.4.2 nathanw &start,
444 1.1.4.2 nathanw &handle) != 0) {
445 1.1.4.5 nathanw panic("rbus_ppb: can not allocate %ld bytes in MEM bus %d",
446 1.1.4.2 nathanw rct.bussize_memreqs[busnum], busnum);
447 1.1.4.2 nathanw }
448 1.1.4.2 nathanw rct.membustags[busnum]=rbus_new(rct.membustags[busparent],
449 1.1.4.2 nathanw start,
450 1.1.4.2 nathanw rct.bussize_memreqs[busnum],
451 1.1.4.2 nathanw 0 /* offset to add to physical
452 1.1.4.2 nathanw address to make processor
453 1.1.4.2 nathanw address */,
454 1.1.4.2 nathanw RBUS_SPACE_DEDICATE);
455 1.1.4.2 nathanw
456 1.1.4.2 nathanw /* program the bridge */
457 1.1.4.2 nathanw /* enable memory space */
458 1.1.4.2 nathanw reg = pci_conf_read(pc, pci_bus_tag[busnum],
459 1.1.4.2 nathanw PCI_COMMAND_STATUS_REG);
460 1.1.4.2 nathanw reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
461 1.1.4.2 nathanw pci_conf_write(pc, pci_bus_tag[busnum],
462 1.1.4.2 nathanw PCI_COMMAND_STATUS_REG, reg);
463 1.1.4.2 nathanw
464 1.1.4.2 nathanw /* now init the limit register for memory */
465 1.1.4.2 nathanw pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_MEM,
466 1.1.4.2 nathanw ((start & PPB_MEM_MASK)
467 1.1.4.2 nathanw >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT |
468 1.1.4.2 nathanw (((start +
469 1.1.4.2 nathanw rct.bussize_memreqs[busnum] +
470 1.1.4.2 nathanw PPB_MEM_MIN-1) >> PPB_MEM_SHIFT)
471 1.1.4.2 nathanw << PPB_MEMLIMIT_SHIFT));
472 1.1.4.2 nathanw
473 1.1.4.2 nathanw /* and set the prefetchable limits as well */
474 1.1.4.2 nathanw pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_PREFMEM,
475 1.1.4.2 nathanw ((start & PPB_MEM_MASK)
476 1.1.4.2 nathanw >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT |
477 1.1.4.2 nathanw (((start +
478 1.1.4.2 nathanw rct.bussize_memreqs[busnum] +
479 1.1.4.2 nathanw PPB_MEM_MIN-1) >> PPB_MEM_SHIFT)
480 1.1.4.2 nathanw << PPB_MEMLIMIT_SHIFT));
481 1.1.4.2 nathanw
482 1.1.4.2 nathanw /* pci_conf_print(pc, pci_bus_tag[busnum], NULL); */
483 1.1.4.2 nathanw }
484 1.1.4.2 nathanw }
485 1.1.4.2 nathanw
486 1.1.4.2 nathanw printf("%s: configuring buses %d-%d\n",
487 1.1.4.2 nathanw rct.csc->sc_dev.dv_xname,
488 1.1.4.2 nathanw minbus, maxbus);
489 1.1.4.2 nathanw pci_device_foreach_min(pc, minbus, maxbus,
490 1.1.4.2 nathanw rbus_pci_phys_allocate, &rct);
491 1.1.4.2 nathanw }
492 1.1.4.2 nathanw
493 1.1.4.2 nathanw static void
494 1.1.4.2 nathanw rbus_pci_phys_countspace(pc, tag, context)
495 1.1.4.2 nathanw pci_chipset_tag_t pc;
496 1.1.4.2 nathanw pcitag_t tag;
497 1.1.4.2 nathanw void *context;
498 1.1.4.2 nathanw {
499 1.1.4.2 nathanw int bus, device, function;
500 1.1.4.2 nathanw struct rbus_pci_addr_fixup_context *rct =
501 1.1.4.2 nathanw (struct rbus_pci_addr_fixup_context *)context;
502 1.1.4.2 nathanw
503 1.1.4.2 nathanw pci_decompose_tag(pc, tag, &bus, &device, &function);
504 1.1.4.2 nathanw
505 1.1.4.2 nathanw printf("%s: configuring device %02x:%02x:%02x\n",
506 1.1.4.2 nathanw rct->csc->sc_dev.dv_xname,
507 1.1.4.2 nathanw bus, device, function);
508 1.1.4.2 nathanw
509 1.1.4.2 nathanw pciaddr_resource_manage(pc, tag,
510 1.1.4.2 nathanw rbus_do_phys_countspace, context);
511 1.1.4.2 nathanw }
512 1.1.4.2 nathanw
513 1.1.4.2 nathanw
514 1.1.4.2 nathanw int
515 1.1.4.2 nathanw rbus_do_phys_countspace(pc, tag, mapreg, ctx, type, addr, size)
516 1.1.4.2 nathanw pci_chipset_tag_t pc;
517 1.1.4.2 nathanw pcitag_t tag;
518 1.1.4.2 nathanw void *ctx;
519 1.1.4.2 nathanw int mapreg, type;
520 1.1.4.2 nathanw bus_addr_t *addr;
521 1.1.4.2 nathanw bus_size_t size;
522 1.1.4.2 nathanw {
523 1.1.4.2 nathanw struct rbus_pci_addr_fixup_context *rct =
524 1.1.4.2 nathanw (struct rbus_pci_addr_fixup_context *)ctx;
525 1.1.4.2 nathanw int bus, device, function;
526 1.1.4.2 nathanw
527 1.1.4.2 nathanw pci_decompose_tag(pc, tag, &bus, &device, &function);
528 1.1.4.2 nathanw
529 1.1.4.2 nathanw if(size > (1<<24)) {
530 1.1.4.2 nathanw printf("%s: skipping huge space request of size=%08x\n",
531 1.1.4.2 nathanw rct->csc->sc_dev.dv_xname, (unsigned int)size);
532 1.1.4.2 nathanw return 0;
533 1.1.4.2 nathanw }
534 1.1.4.2 nathanw
535 1.1.4.2 nathanw if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) {
536 1.1.4.2 nathanw rct->bussize_ioreqs[bus] += size;
537 1.1.4.2 nathanw } else {
538 1.1.4.2 nathanw rct->bussize_memreqs[bus]+= size;
539 1.1.4.2 nathanw }
540 1.1.4.2 nathanw
541 1.1.4.2 nathanw return 0;
542 1.1.4.2 nathanw }
543 1.1.4.2 nathanw
544 1.1.4.2 nathanw static void
545 1.1.4.2 nathanw rbus_pci_phys_allocate(pc, tag, context)
546 1.1.4.2 nathanw pci_chipset_tag_t pc;
547 1.1.4.2 nathanw pcitag_t tag;
548 1.1.4.2 nathanw void *context;
549 1.1.4.2 nathanw {
550 1.1.4.2 nathanw int bus, device, function, command;
551 1.1.4.2 nathanw struct rbus_pci_addr_fixup_context *rct =
552 1.1.4.2 nathanw (struct rbus_pci_addr_fixup_context *)context;
553 1.1.4.2 nathanw //cardbus_chipset_tag_t ct = rct->ct;
554 1.1.4.2 nathanw // struct cardbus_softc *sc = rct->sc;
555 1.1.4.2 nathanw
556 1.1.4.2 nathanw pci_decompose_tag(pc, tag, &bus, &device, &function);
557 1.1.4.2 nathanw
558 1.1.4.2 nathanw printf("%s: configuring device %02x:%02x:%02x\n",
559 1.1.4.2 nathanw rct->csc->sc_dev.dv_xname,
560 1.1.4.2 nathanw bus, device, function);
561 1.1.4.2 nathanw
562 1.1.4.2 nathanw pciaddr_resource_manage(pc, tag,
563 1.1.4.2 nathanw rbus_do_phys_allocate, context);
564 1.1.4.2 nathanw
565 1.1.4.2 nathanw /* now turn the device's memory and I/O on */
566 1.1.4.2 nathanw command = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
567 1.1.4.2 nathanw command |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE;
568 1.1.4.2 nathanw pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command);
569 1.1.4.2 nathanw }
570 1.1.4.2 nathanw
571 1.1.4.2 nathanw int
572 1.1.4.2 nathanw rbus_do_phys_allocate(pc, tag, mapreg, ctx, type, addr, size)
573 1.1.4.2 nathanw pci_chipset_tag_t pc;
574 1.1.4.2 nathanw pcitag_t tag;
575 1.1.4.2 nathanw void *ctx;
576 1.1.4.2 nathanw int mapreg, type;
577 1.1.4.2 nathanw bus_addr_t *addr;
578 1.1.4.2 nathanw bus_size_t size;
579 1.1.4.2 nathanw {
580 1.1.4.2 nathanw struct rbus_pci_addr_fixup_context *rct =
581 1.1.4.2 nathanw (struct rbus_pci_addr_fixup_context *)ctx;
582 1.1.4.2 nathanw cardbus_chipset_tag_t ct = rct->ct;
583 1.1.4.2 nathanw struct cardbus_softc *sc = rct->sc;
584 1.1.4.2 nathanw cardbus_function_t *cf = sc->sc_cf;
585 1.1.4.2 nathanw rbus_tag_t rbustag;
586 1.1.4.2 nathanw bus_space_tag_t bustag;
587 1.1.4.2 nathanw bus_addr_t mask = size -1;
588 1.1.4.2 nathanw bus_addr_t base = 0;
589 1.1.4.2 nathanw bus_space_handle_t handle;
590 1.1.4.2 nathanw int busflags = 0;
591 1.1.4.2 nathanw int flags = 0;
592 1.1.4.2 nathanw char *bustype;
593 1.1.4.2 nathanw int bus, device, function;
594 1.1.4.2 nathanw
595 1.1.4.2 nathanw pci_decompose_tag(pc, tag, &bus, &device, &function);
596 1.1.4.2 nathanw
597 1.1.4.2 nathanw /*
598 1.1.4.2 nathanw * some devices come up with garbage in them (Tulip?)
599 1.1.4.2 nathanw * we are in charge here, so give them address
600 1.1.4.2 nathanw * space anyway.
601 1.1.4.2 nathanw *
602 1.1.4.2 nathanw * XXX this may be due to no secondary PCI reset!!!
603 1.1.4.2 nathanw */
604 1.1.4.2 nathanw #if 0
605 1.1.4.2 nathanw if (*addr) {
606 1.1.4.2 nathanw printf("Already allocated space at %08x\n",
607 1.1.4.2 nathanw (unsigned int)*addr);
608 1.1.4.2 nathanw return (0);
609 1.1.4.2 nathanw }
610 1.1.4.2 nathanw #endif
611 1.1.4.2 nathanw
612 1.1.4.2 nathanw if(size > (1<<24)) {
613 1.1.4.2 nathanw printf("%s: skipping huge space request of size=%08x\n",
614 1.1.4.2 nathanw rct->csc->sc_dev.dv_xname, (unsigned int)size);
615 1.1.4.2 nathanw return 0;
616 1.1.4.2 nathanw }
617 1.1.4.2 nathanw
618 1.1.4.2 nathanw if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) {
619 1.1.4.2 nathanw bustag = sc->sc_iot;
620 1.1.4.2 nathanw rbustag = rct->iobustags[bus];
621 1.1.4.2 nathanw bustype = "io";
622 1.1.4.2 nathanw } else {
623 1.1.4.2 nathanw bustag = sc->sc_memt;
624 1.1.4.2 nathanw rbustag = rct->membustags[bus];
625 1.1.4.2 nathanw bustype = "mem";
626 1.1.4.2 nathanw }
627 1.1.4.2 nathanw
628 1.1.4.2 nathanw if((*cf->cardbus_space_alloc)(ct, rbustag, base, size,
629 1.1.4.2 nathanw mask, size, busflags|flags,
630 1.1.4.2 nathanw addr, &handle)) {
631 1.1.4.2 nathanw printf("%s: no available resources (size=%08x) for bar %2d. fixup failed\n",
632 1.1.4.2 nathanw rct->csc->sc_dev.dv_xname, (unsigned int)size, mapreg);
633 1.1.4.2 nathanw
634 1.1.4.2 nathanw *addr = 0;
635 1.1.4.2 nathanw pci_conf_write(pc, tag, mapreg, *addr);
636 1.1.4.2 nathanw return (1);
637 1.1.4.2 nathanw }
638 1.1.4.2 nathanw
639 1.1.4.2 nathanw printf("%s: alloc %s space of size %08x for %02d:%02d:%02d -> %08x\n",
640 1.1.4.2 nathanw rct->csc->sc_dev.dv_xname,
641 1.1.4.2 nathanw bustype,
642 1.1.4.2 nathanw (unsigned int)size,
643 1.1.4.2 nathanw bus, device, function, (unsigned int)*addr);
644 1.1.4.2 nathanw
645 1.1.4.2 nathanw /* write new address to PCI device configuration header */
646 1.1.4.2 nathanw pci_conf_write(pc, tag, mapreg, *addr);
647 1.1.4.2 nathanw
648 1.1.4.2 nathanw /* check */
649 1.1.4.2 nathanw {
650 1.1.4.2 nathanw DPRINTF(("%s: pci_addr_fixup: ",
651 1.1.4.2 nathanw rct->csc->sc_dev.dv_xname));
652 1.1.4.2 nathanw #ifdef CBB_DEBUG
653 1.1.4.2 nathanw if(rbus_ppb_debug) { pciaddr_print_devid(pc, tag); }
654 1.1.4.2 nathanw #endif
655 1.1.4.2 nathanw }
656 1.1.4.2 nathanw
657 1.1.4.2 nathanw /* double check that the value got inserted correctly */
658 1.1.4.2 nathanw if (pciaddr_ioaddr(pci_conf_read(pc, tag, mapreg)) != *addr) {
659 1.1.4.2 nathanw pci_conf_write(pc, tag, mapreg, 0); /* clear */
660 1.1.4.2 nathanw printf("%s: fixup failed. (new address=%#x)\n",
661 1.1.4.2 nathanw rct->csc->sc_dev.dv_xname,
662 1.1.4.2 nathanw (unsigned)*addr);
663 1.1.4.2 nathanw return (1);
664 1.1.4.2 nathanw }
665 1.1.4.2 nathanw
666 1.1.4.2 nathanw DPRINTF(("new address 0x%08x\n",
667 1.1.4.2 nathanw (unsigned)*addr));
668 1.1.4.2 nathanw
669 1.1.4.2 nathanw return (0);
670 1.1.4.2 nathanw }
671 1.1.4.2 nathanw
672 1.1.4.2 nathanw static void
673 1.1.4.2 nathanw ppb_cardbus_attach(parent, self, aux)
674 1.1.4.2 nathanw struct device *parent, *self;
675 1.1.4.2 nathanw void *aux;
676 1.1.4.2 nathanw {
677 1.1.4.2 nathanw struct ppb_cardbus_softc *csc = (struct ppb_cardbus_softc *) self;
678 1.1.4.2 nathanw struct cardbus_softc *parent_sc =
679 1.1.4.2 nathanw (struct cardbus_softc *) csc->sc_dev.dv_parent;
680 1.1.4.2 nathanw struct cardbus_attach_args *ca = aux;
681 1.1.4.2 nathanw cardbus_devfunc_t ct = ca->ca_ct;
682 1.1.4.2 nathanw cardbus_chipset_tag_t cc = ct->ct_cc;
683 1.1.4.2 nathanw cardbus_function_tag_t cf = ct->ct_cf;
684 1.1.4.2 nathanw struct pccbb_softc *psc = (struct pccbb_softc *)cc;
685 1.1.4.2 nathanw struct pcibus_attach_args pba;
686 1.1.4.2 nathanw char devinfo[256];
687 1.1.4.2 nathanw pcireg_t busdata;
688 1.1.4.2 nathanw int mybus, rv;
689 1.1.4.2 nathanw u_int16_t pciirq;
690 1.1.4.2 nathanw int minbus, maxbus;
691 1.1.4.2 nathanw
692 1.1.4.2 nathanw mybus = ct->ct_bus;
693 1.1.4.2 nathanw pciirq = 0;
694 1.1.4.2 nathanw rv = 0;
695 1.1.4.2 nathanw
696 1.1.4.2 nathanw /* shut up compiler */
697 1.1.4.2 nathanw csc->foo=parent_sc->sc_intrline;
698 1.1.4.2 nathanw
699 1.1.4.2 nathanw
700 1.1.4.2 nathanw pci_devinfo(ca->ca_id, ca->ca_class, 0, devinfo);
701 1.1.4.2 nathanw printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(ca->ca_class));
702 1.1.4.2 nathanw
703 1.1.4.4 nathanw csc->sc_tag = ca->ca_tag; /* XXX cardbustag_t == pcitag_t */
704 1.1.4.4 nathanw
705 1.1.4.2 nathanw busdata = cardbus_conf_read(cc, cf, ca->ca_tag, PPB_REG_BUSINFO);
706 1.1.4.2 nathanw minbus = pcibios_max_bus;
707 1.1.4.2 nathanw
708 1.1.4.2 nathanw if (PPB_BUSINFO_SECONDARY(busdata) == 0) {
709 1.1.4.2 nathanw printf("%s: not configured by system firmware calling pci_bus_fixup(%d)\n",
710 1.1.4.2 nathanw self->dv_xname, 0);
711 1.1.4.2 nathanw
712 1.1.4.2 nathanw /*
713 1.1.4.2 nathanw * first, pull the reset wire on the secondary bridge
714 1.1.4.2 nathanw * to clear all devices
715 1.1.4.2 nathanw */
716 1.1.4.2 nathanw busdata = cardbus_conf_read(cc, cf, ca->ca_tag,
717 1.1.4.2 nathanw PPB_REG_BRIDGECONTROL);
718 1.1.4.2 nathanw cardbus_conf_write(cc, cf, ca->ca_tag, PPB_REG_BRIDGECONTROL,
719 1.1.4.2 nathanw busdata | PPB_BC_SECONDARY_RESET);
720 1.1.4.2 nathanw delay(1);
721 1.1.4.2 nathanw cardbus_conf_write(cc, cf, ca->ca_tag, PPB_REG_BRIDGECONTROL,
722 1.1.4.2 nathanw busdata);
723 1.1.4.2 nathanw
724 1.1.4.2 nathanw /* then go initialize the bridge control registers */
725 1.1.4.2 nathanw maxbus = pci_bus_fixup(psc->sc_pc, 0);
726 1.1.4.2 nathanw }
727 1.1.4.2 nathanw
728 1.1.4.2 nathanw busdata = cardbus_conf_read(cc, cf, ca->ca_tag, PPB_REG_BUSINFO);
729 1.1.4.2 nathanw if(PPB_BUSINFO_SECONDARY(busdata) == 0) {
730 1.1.4.2 nathanw printf("%s: still not configured, not fixable.\n",
731 1.1.4.2 nathanw self->dv_xname);
732 1.1.4.2 nathanw return;
733 1.1.4.2 nathanw }
734 1.1.4.2 nathanw
735 1.1.4.2 nathanw #if 0
736 1.1.4.2 nathanw minbus = PPB_BUSINFO_SECONDARY(busdata);
737 1.1.4.2 nathanw maxbus = PPB_BUSINFO_SUBORDINATE(busdata);
738 1.1.4.2 nathanw #endif
739 1.1.4.2 nathanw
740 1.1.4.2 nathanw /* now, go and assign addresses for the new devices */
741 1.1.4.2 nathanw rbus_pci_addr_fixup(csc, cc, parent_sc,
742 1.1.4.2 nathanw psc->sc_pc,
743 1.1.4.2 nathanw ca,
744 1.1.4.2 nathanw minbus, maxbus);
745 1.1.4.2 nathanw
746 1.1.4.2 nathanw /*
747 1.1.4.2 nathanw * now configure all connected devices to the IRQ which
748 1.1.4.2 nathanw * was assigned to this slot, as they will all arrive from
749 1.1.4.2 nathanw * that IRQ.
750 1.1.4.2 nathanw */
751 1.1.4.2 nathanw rbus_intr_fixup(psc->sc_pc, minbus, maxbus, ca->ca_intrline);
752 1.1.4.2 nathanw
753 1.1.4.2 nathanw /*
754 1.1.4.2 nathanw * enable direct routing of interrupts. We do this because
755 1.1.4.2 nathanw * we can not manage to get pccb_intr_establish() called until
756 1.1.4.2 nathanw * PCI subsystem is merged with rbus. The major thing that this
757 1.1.4.2 nathanw * routine does is avoid calling the driver's interrupt routine
758 1.1.4.2 nathanw * when the card has been removed.
759 1.1.4.2 nathanw *
760 1.1.4.2 nathanw * The rbus_ppb.c can not cope with card desertions until the merging
761 1.1.4.2 nathanw * anyway.
762 1.1.4.2 nathanw */
763 1.1.4.2 nathanw pccbb_intr_route(psc);
764 1.1.4.2 nathanw
765 1.1.4.2 nathanw /*
766 1.1.4.2 nathanw * Attach the PCI bus than hangs off of it.
767 1.1.4.2 nathanw *
768 1.1.4.2 nathanw * XXX Don't pass-through Memory Read Multiple. Should we?
769 1.1.4.2 nathanw * XXX Consult the spec...
770 1.1.4.2 nathanw */
771 1.1.4.2 nathanw pba.pba_busname = "pci";
772 1.1.4.2 nathanw pba.pba_iot = ca->ca_iot;
773 1.1.4.2 nathanw pba.pba_memt = ca->ca_memt;
774 1.1.4.2 nathanw pba.pba_dmat = ca->ca_dmat;
775 1.1.4.2 nathanw pba.pba_pc = psc->sc_pc;
776 1.1.4.2 nathanw pba.pba_flags = PCI_FLAGS_IO_ENABLED|PCI_FLAGS_MEM_ENABLED;
777 1.1.4.2 nathanw pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata);
778 1.1.4.4 nathanw pba.pba_bridgetag = &csc->sc_tag;
779 1.1.4.2 nathanw /*pba.pba_intrswiz = parent_sc->sc_intrswiz; */
780 1.1.4.2 nathanw pba.pba_intrtag = psc->sc_pa.pa_intrtag;
781 1.1.4.2 nathanw
782 1.1.4.2 nathanw config_found(self, &pba, rppbprint);
783 1.1.4.2 nathanw }
784 1.1.4.2 nathanw
785 1.1.4.2 nathanw void
786 1.1.4.2 nathanw ppb_cardbus_setup(struct ppb_softc * sc)
787 1.1.4.2 nathanw {
788 1.1.4.2 nathanw struct ppb_cardbus_softc *csc = (struct ppb_cardbus_softc *) sc;
789 1.1.4.2 nathanw #if 0
790 1.1.4.2 nathanw cardbus_chipset_tag_t cc = psc->sc_cc;
791 1.1.4.2 nathanw cardbus_function_tag_t cf = psc->sc_cf;
792 1.1.4.2 nathanw #endif
793 1.1.4.2 nathanw
794 1.1.4.2 nathanw /* shut up compiler */
795 1.1.4.2 nathanw csc->foo=2;
796 1.1.4.2 nathanw
797 1.1.4.2 nathanw printf("ppb_cardbus_setup called\n");
798 1.1.4.2 nathanw #if 0
799 1.1.4.2 nathanw /* not sure what to do here */
800 1.1.4.2 nathanw cardbustag_t tag = cardbus_make_tag(cc, cf, csc->ct->ct_bus,
801 1.1.4.2 nathanw csc->ct->ct_dev, csc->ct->ct_func);
802 1.1.4.2 nathanw
803 1.1.4.2 nathanw command = Cardbus_conf_read(csc->ct, tag, CARDBUS_COMMAND_STATUS_REG);
804 1.1.4.2 nathanw if (csc->base0_reg) {
805 1.1.4.2 nathanw Cardbus_conf_write(csc->ct, tag,
806 1.1.4.2 nathanw CARDBUS_BASE0_REG, csc->base0_reg);
807 1.1.4.2 nathanw (cf->cardbus_ctrl) (cc, CARDBUS_MEM_ENABLE);
808 1.1.4.2 nathanw command |= CARDBUS_COMMAND_MEM_ENABLE |
809 1.1.4.2 nathanw CARDBUS_COMMAND_MASTER_ENABLE;
810 1.1.4.2 nathanw } else if (csc->base1_reg) {
811 1.1.4.2 nathanw Cardbus_conf_write(csc->ct, tag,
812 1.1.4.2 nathanw CARDBUS_BASE1_REG, csc->base1_reg);
813 1.1.4.2 nathanw (cf->cardbus_ctrl) (cc, CARDBUS_IO_ENABLE);
814 1.1.4.2 nathanw command |= (CARDBUS_COMMAND_IO_ENABLE |
815 1.1.4.2 nathanw CARDBUS_COMMAND_MASTER_ENABLE);
816 1.1.4.2 nathanw }
817 1.1.4.2 nathanw
818 1.1.4.2 nathanw (cf->cardbus_ctrl) (cc, CARDBUS_BM_ENABLE);
819 1.1.4.2 nathanw
820 1.1.4.2 nathanw /* enable the card */
821 1.1.4.2 nathanw Cardbus_conf_write(csc->ct, tag, CARDBUS_COMMAND_STATUS_REG, command);
822 1.1.4.2 nathanw #endif
823 1.1.4.2 nathanw }
824 1.1.4.2 nathanw
825 1.1.4.2 nathanw int
826 1.1.4.2 nathanw ppb_cardbus_enable(struct ppb_softc * sc)
827 1.1.4.2 nathanw {
828 1.1.4.2 nathanw #if 0
829 1.1.4.2 nathanw struct ppb_cardbus_softc *csc = (struct fxp_cardbus_softc *) sc;
830 1.1.4.2 nathanw struct cardbus_softc *psc =
831 1.1.4.2 nathanw (struct cardbus_softc *) sc->sc_dev.dv_parent;
832 1.1.4.2 nathanw cardbus_chipset_tag_t cc = psc->sc_cc;
833 1.1.4.2 nathanw cardbus_function_tag_t cf = psc->sc_cf;
834 1.1.4.2 nathanw
835 1.1.4.2 nathanw Cardbus_function_enable(csc->ct);
836 1.1.4.2 nathanw
837 1.1.4.2 nathanw fxp_cardbus_setup(sc);
838 1.1.4.2 nathanw
839 1.1.4.2 nathanw /* Map and establish the interrupt. */
840 1.1.4.2 nathanw
841 1.1.4.2 nathanw sc->sc_ih = cardbus_intr_establish(cc, cf, psc->sc_intrline, IPL_NET,
842 1.1.4.2 nathanw fxp_intr, sc);
843 1.1.4.2 nathanw if (NULL == sc->sc_ih) {
844 1.1.4.2 nathanw printf("%s: couldn't establish interrupt\n",
845 1.1.4.2 nathanw sc->sc_dev.dv_xname);
846 1.1.4.2 nathanw return 1;
847 1.1.4.2 nathanw }
848 1.1.4.2 nathanw
849 1.1.4.2 nathanw printf("%s: interrupting at %d\n", sc->sc_dev.dv_xname,
850 1.1.4.2 nathanw psc->sc_intrline);
851 1.1.4.2 nathanw
852 1.1.4.2 nathanw #endif
853 1.1.4.2 nathanw return 0;
854 1.1.4.2 nathanw }
855 1.1.4.2 nathanw
856 1.1.4.2 nathanw void
857 1.1.4.2 nathanw ppb_cardbus_disable(struct ppb_softc * sc)
858 1.1.4.2 nathanw {
859 1.1.4.2 nathanw #if 0
860 1.1.4.2 nathanw struct cardbus_softc *psc =
861 1.1.4.2 nathanw (struct cardbus_softc *) sc->sc_dev.dv_parent;
862 1.1.4.2 nathanw cardbus_chipset_tag_t cc = psc->sc_cc;
863 1.1.4.2 nathanw cardbus_function_tag_t cf = psc->sc_cf;
864 1.1.4.2 nathanw
865 1.1.4.2 nathanw /* Remove interrupt handler. */
866 1.1.4.2 nathanw cardbus_intr_disestablish(cc, cf, sc->sc_ih);
867 1.1.4.2 nathanw
868 1.1.4.2 nathanw Cardbus_function_disable(((struct fxp_cardbus_softc *) sc)->ct);
869 1.1.4.2 nathanw #endif
870 1.1.4.2 nathanw }
871 1.1.4.2 nathanw
872 1.1.4.2 nathanw static int
873 1.1.4.2 nathanw ppb_cardbus_detach(self, flags)
874 1.1.4.2 nathanw struct device *self;
875 1.1.4.2 nathanw int flags;
876 1.1.4.2 nathanw {
877 1.1.4.2 nathanw /* struct ppb_softc *sc = (struct ppb_softc *) self;*/
878 1.1.4.2 nathanw struct ppb_cardbus_softc *csc = (struct ppb_cardbus_softc *) self;
879 1.1.4.2 nathanw
880 1.1.4.2 nathanw #if 0
881 1.1.4.2 nathanw struct cardbus_devfunc *ct = csc->ct;
882 1.1.4.2 nathanw int rv, reg;
883 1.1.4.2 nathanw
884 1.1.4.2 nathanw #ifdef DIAGNOSTIC
885 1.1.4.2 nathanw if (ct == NULL)
886 1.1.4.5 nathanw panic("%s: data structure lacks", sc->sc_dev.dv_xname);
887 1.1.4.2 nathanw #endif
888 1.1.4.2 nathanw
889 1.1.4.2 nathanw rv = fxp_detach(sc);
890 1.1.4.2 nathanw if (rv == 0) {
891 1.1.4.2 nathanw /*
892 1.1.4.2 nathanw * Unhook the interrupt handler.
893 1.1.4.2 nathanw */
894 1.1.4.2 nathanw cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, sc->sc_ih);
895 1.1.4.2 nathanw
896 1.1.4.2 nathanw /*
897 1.1.4.2 nathanw * release bus space and close window
898 1.1.4.2 nathanw */
899 1.1.4.2 nathanw if (csc->base0_reg)
900 1.1.4.2 nathanw reg = CARDBUS_BASE0_REG;
901 1.1.4.2 nathanw else
902 1.1.4.2 nathanw reg = CARDBUS_BASE1_REG;
903 1.1.4.2 nathanw Cardbus_mapreg_unmap(ct, reg, sc->sc_st, sc->sc_sh, csc->size);
904 1.1.4.2 nathanw }
905 1.1.4.2 nathanw return (rv);
906 1.1.4.2 nathanw
907 1.1.4.2 nathanw #endif
908 1.1.4.2 nathanw csc->foo=1;
909 1.1.4.2 nathanw return 0;
910 1.1.4.2 nathanw
911 1.1.4.2 nathanw }
912 1.1.4.2 nathanw
913 1.1.4.2 nathanw int
914 1.1.4.2 nathanw ppb_activate(self, act)
915 1.1.4.2 nathanw struct device *self;
916 1.1.4.2 nathanw enum devact act;
917 1.1.4.2 nathanw {
918 1.1.4.2 nathanw printf("ppb_activate called\n");
919 1.1.4.2 nathanw return 0;
920 1.1.4.2 nathanw }
921 1.1.4.2 nathanw
922