rbus_ppb.c revision 1.2 1 1.2 lukem /* $NetBSD: rbus_ppb.c,v 1.2 2001/11/13 12:51:13 lukem Exp $ */
2 1.1 mcr
3 1.1 mcr /*
4 1.1 mcr * Copyright (c) 1999 The NetBSD Foundation, Inc.
5 1.1 mcr * All rights reserved.
6 1.1 mcr *
7 1.1 mcr * This code is derived from software contributed to The NetBSD Foundation
8 1.1 mcr * by Michael Richardson <mcr (at) sandelman.ottawa.on.ca>
9 1.1 mcr *
10 1.1 mcr * Redistribution and use in source and binary forms, with or without
11 1.1 mcr * modification, are permitted provided that the following conditions
12 1.1 mcr * are met:
13 1.1 mcr * 1. Redistributions of source code must retain the above copyright
14 1.1 mcr * notice, this list of conditions and the following disclaimer.
15 1.1 mcr * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 mcr * notice, this list of conditions and the following disclaimer in the
17 1.1 mcr * documentation and/or other materials provided with the distribution.
18 1.1 mcr * 3. All advertising materials mentioning features or use of this software
19 1.1 mcr * must display the following acknowledgement:
20 1.1 mcr * This product includes software developed by the NetBSD
21 1.1 mcr * Foundation, Inc. and its contributors.
22 1.1 mcr * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.1 mcr * contributors may be used to endorse or promote products derived
24 1.1 mcr * from this software without specific prior written permission.
25 1.1 mcr *
26 1.1 mcr * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.1 mcr * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.1 mcr * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1 mcr * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.1 mcr * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.1 mcr * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.1 mcr * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.1 mcr * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.1 mcr * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.1 mcr * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.1 mcr * POSSIBILITY OF SUCH DAMAGE.
37 1.1 mcr */
38 1.1 mcr
39 1.1 mcr /*
40 1.1 mcr * CardBus front-end for the Intel/Digital DECchip 21152 PCI-PCI bridge
41 1.1 mcr */
42 1.2 lukem
43 1.2 lukem #include <sys/cdefs.h>
44 1.2 lukem __KERNEL_RCSID(0, "$NetBSD: rbus_ppb.c,v 1.2 2001/11/13 12:51:13 lukem Exp $");
45 1.1 mcr
46 1.1 mcr #include <sys/param.h>
47 1.1 mcr #include <sys/systm.h>
48 1.1 mcr #include <sys/mbuf.h>
49 1.1 mcr #include <sys/malloc.h>
50 1.1 mcr #include <sys/kernel.h>
51 1.1 mcr #include <sys/socket.h>
52 1.1 mcr #include <sys/ioctl.h>
53 1.1 mcr #include <sys/errno.h>
54 1.1 mcr #include <sys/device.h>
55 1.1 mcr
56 1.1 mcr #if NRND > 0
57 1.1 mcr #include <sys/rnd.h>
58 1.1 mcr #endif
59 1.1 mcr
60 1.1 mcr #include <machine/endian.h>
61 1.1 mcr
62 1.1 mcr #include <machine/bus.h>
63 1.1 mcr #include <machine/intr.h>
64 1.1 mcr
65 1.1 mcr #include <dev/pci/pcivar.h>
66 1.1 mcr #include <dev/pci/pcireg.h>
67 1.1 mcr #include <dev/pci/pcidevs.h>
68 1.1 mcr #include <dev/pci/ppbreg.h>
69 1.1 mcr
70 1.1 mcr #include <dev/ic/i82365reg.h>
71 1.1 mcr #include <dev/ic/i82365var.h>
72 1.1 mcr
73 1.1 mcr #include <dev/pci/pccbbreg.h>
74 1.1 mcr #include <dev/pci/pccbbvar.h>
75 1.1 mcr
76 1.1 mcr #include <dev/cardbus/cardbusvar.h>
77 1.1 mcr #include <dev/cardbus/cardbusdevs.h>
78 1.1 mcr
79 1.1 mcr #include <i386/pci/pci_addr_fixup.h>
80 1.1 mcr #include <i386/pci/pci_bus_fixup.h>
81 1.1 mcr #include <i386/pci/pci_intr_fixup.h>
82 1.1 mcr #include <i386/pci/pcibios.h>
83 1.1 mcr
84 1.1 mcr struct ppb_softc;
85 1.1 mcr
86 1.1 mcr static int ppb_cardbus_match __P((struct device *, struct cfdata *, void *));
87 1.1 mcr static void ppb_cardbus_attach __P((struct device *, struct device *, void *));
88 1.1 mcr static int ppb_cardbus_detach __P((struct device * self, int flags));
89 1.1 mcr /*static*/ void ppb_cardbus_setup __P((struct ppb_softc * sc));
90 1.1 mcr /*static*/ int ppb_cardbus_enable __P((struct ppb_softc * sc));
91 1.1 mcr /*static*/ void ppb_cardbus_disable __P((struct ppb_softc * sc));
92 1.1 mcr static int ppb_activate __P((struct device *self, enum devact act));
93 1.1 mcr int rppbprint __P((void *aux, const char *pnp));
94 1.1 mcr int rbus_intr_fixup __P((pci_chipset_tag_t pc, int minbus,
95 1.1 mcr int maxbus, int line));
96 1.1 mcr void rbus_do_header_fixup __P((pci_chipset_tag_t pc, pcitag_t tag,
97 1.1 mcr void *context));
98 1.1 mcr
99 1.1 mcr static void rbus_pci_phys_allocate __P((pci_chipset_tag_t pc,
100 1.1 mcr pcitag_t tag,
101 1.1 mcr void *context));
102 1.1 mcr
103 1.1 mcr static int rbus_do_phys_allocate __P((pci_chipset_tag_t pc,
104 1.1 mcr pcitag_t tag,
105 1.1 mcr int mapreg,
106 1.1 mcr void *ctx,
107 1.1 mcr int type,
108 1.1 mcr bus_addr_t *addr,
109 1.1 mcr bus_size_t size));
110 1.1 mcr
111 1.1 mcr static void rbus_pci_phys_countspace __P((pci_chipset_tag_t pc,
112 1.1 mcr pcitag_t tag,
113 1.1 mcr void *context));
114 1.1 mcr
115 1.1 mcr static int rbus_do_phys_countspace __P((pci_chipset_tag_t pc,
116 1.1 mcr pcitag_t tag,
117 1.1 mcr int mapreg,
118 1.1 mcr void *ctx,
119 1.1 mcr int type,
120 1.1 mcr bus_addr_t *addr,
121 1.1 mcr bus_size_t size));
122 1.1 mcr
123 1.1 mcr unsigned int rbus_round_up __P((unsigned int size, unsigned int min));
124 1.1 mcr
125 1.1 mcr
126 1.1 mcr struct ppb_cardbus_softc {
127 1.1 mcr struct device sc_dev;
128 1.1 mcr int foo;
129 1.1 mcr };
130 1.1 mcr
131 1.1 mcr struct cfattach rbus_ppb_ca = {
132 1.1 mcr sizeof(struct ppb_cardbus_softc),
133 1.1 mcr ppb_cardbus_match,
134 1.1 mcr ppb_cardbus_attach,
135 1.1 mcr ppb_cardbus_detach,
136 1.1 mcr ppb_activate
137 1.1 mcr };
138 1.1 mcr
139 1.1 mcr #ifdef CBB_DEBUG
140 1.1 mcr int rbus_ppb_debug = 0; /* hack with kdb */
141 1.1 mcr #define DPRINTF(X) if(rbus_ppb_debug) printf X
142 1.1 mcr #else
143 1.1 mcr #define DPRINTF(X)
144 1.1 mcr #endif
145 1.1 mcr
146 1.1 mcr static int
147 1.1 mcr ppb_cardbus_match(parent, match, aux)
148 1.1 mcr struct device *parent;
149 1.1 mcr struct cfdata *match;
150 1.1 mcr void *aux;
151 1.1 mcr {
152 1.1 mcr struct cardbus_attach_args *ca = aux;
153 1.1 mcr
154 1.1 mcr if (CARDBUS_VENDOR(ca->ca_id) == PCI_VENDOR_DEC &&
155 1.1 mcr CARDBUS_PRODUCT(ca->ca_id) == PCI_PRODUCT_DEC_21152)
156 1.1 mcr return (1);
157 1.1 mcr
158 1.1 mcr if(PCI_CLASS(ca->ca_class) == PCI_CLASS_BRIDGE &&
159 1.1 mcr PCI_SUBCLASS(ca->ca_class) == PCI_SUBCLASS_BRIDGE_PCI) {
160 1.1 mcr /* XXX */
161 1.1 mcr printf("recognizing generic bridge chip\n");
162 1.1 mcr }
163 1.1 mcr
164 1.1 mcr return (0);
165 1.1 mcr }
166 1.1 mcr
167 1.1 mcr
168 1.1 mcr int
169 1.1 mcr rppbprint(aux, pnp)
170 1.1 mcr void *aux;
171 1.1 mcr const char *pnp;
172 1.1 mcr {
173 1.1 mcr struct pcibus_attach_args *pba = aux;
174 1.1 mcr
175 1.1 mcr /* only PCIs can attach to PPBs; easy. */
176 1.1 mcr if (pnp)
177 1.1 mcr printf("pci at %s", pnp);
178 1.1 mcr printf(" bus %d (rbus)", pba->pba_bus);
179 1.1 mcr return (UNCONF);
180 1.1 mcr }
181 1.1 mcr
182 1.1 mcr int
183 1.1 mcr rbus_intr_fixup(pci_chipset_tag_t pc,
184 1.1 mcr int minbus,
185 1.1 mcr int maxbus,
186 1.1 mcr int line)
187 1.1 mcr {
188 1.1 mcr pci_device_foreach_min(pc, minbus,
189 1.1 mcr maxbus, rbus_do_header_fixup, (void *)&line);
190 1.1 mcr return 0;
191 1.1 mcr }
192 1.1 mcr
193 1.1 mcr void
194 1.1 mcr rbus_do_header_fixup(pc, tag, context)
195 1.1 mcr pci_chipset_tag_t pc;
196 1.1 mcr pcitag_t tag;
197 1.1 mcr void *context;
198 1.1 mcr {
199 1.1 mcr int pin, irq;
200 1.1 mcr int bus, device, function;
201 1.1 mcr pcireg_t intr, id;
202 1.1 mcr int *pline = (int *)context;
203 1.1 mcr int line = *pline;
204 1.1 mcr
205 1.1 mcr pci_decompose_tag(pc, tag, &bus, &device, &function);
206 1.1 mcr id = pci_conf_read(pc, tag, PCI_ID_REG);
207 1.1 mcr
208 1.1 mcr intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
209 1.1 mcr pin = PCI_INTERRUPT_PIN(intr);
210 1.1 mcr irq = PCI_INTERRUPT_LINE(intr);
211 1.1 mcr
212 1.1 mcr #if 0
213 1.1 mcr printf("do_header %02x:%02x:%02x pin=%d => line %d\n",
214 1.1 mcr bus, device, function, pin, line);
215 1.1 mcr #endif
216 1.1 mcr
217 1.1 mcr intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);
218 1.1 mcr intr |= (line << PCI_INTERRUPT_LINE_SHIFT);
219 1.1 mcr pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr);
220 1.1 mcr
221 1.1 mcr }
222 1.1 mcr
223 1.1 mcr /*
224 1.1 mcr * This function takes a range of PCI bus numbers and
225 1.1 mcr * allocates space for all devices found in this space (the BARs) from
226 1.1 mcr * the rbus space maps (I/O and memory).
227 1.1 mcr *
228 1.1 mcr * It assumes that "rbus" is defined. The whole concept does.
229 1.1 mcr *
230 1.1 mcr * It uses pci_device_foreach_min() to call rbus_pci_phys_allocate.
231 1.1 mcr * This function is mostly stolen from
232 1.1 mcr * pci_addr_fixup.c:pciaddr_resource_reserve.
233 1.1 mcr *
234 1.1 mcr */
235 1.1 mcr struct rbus_pci_addr_fixup_context {
236 1.1 mcr struct ppb_cardbus_softc *csc;
237 1.1 mcr cardbus_chipset_tag_t ct;
238 1.1 mcr struct cardbus_softc *sc;
239 1.1 mcr struct cardbus_attach_args *caa;
240 1.1 mcr int minbus;
241 1.1 mcr int maxbus;
242 1.1 mcr bus_size_t *bussize_ioreqs;
243 1.1 mcr bus_size_t *bussize_memreqs;
244 1.1 mcr rbus_tag_t *iobustags;
245 1.1 mcr rbus_tag_t *membustags;
246 1.1 mcr };
247 1.1 mcr
248 1.1 mcr unsigned int
249 1.1 mcr rbus_round_up(unsigned int size, unsigned int min)
250 1.1 mcr {
251 1.1 mcr unsigned int power2;
252 1.1 mcr
253 1.1 mcr if(size == 0) {
254 1.1 mcr return 0;
255 1.1 mcr }
256 1.1 mcr
257 1.1 mcr power2=min;
258 1.1 mcr
259 1.1 mcr while(power2 < (1 << 31) &&
260 1.1 mcr power2 < size) {
261 1.1 mcr power2 = power2 << 1;
262 1.1 mcr }
263 1.1 mcr
264 1.1 mcr return power2;
265 1.1 mcr }
266 1.1 mcr
267 1.1 mcr static void
268 1.1 mcr rbus_pci_addr_fixup(struct ppb_cardbus_softc *csc,
269 1.1 mcr cardbus_chipset_tag_t ct,
270 1.1 mcr struct cardbus_softc *sc,
271 1.1 mcr pci_chipset_tag_t pc,
272 1.1 mcr struct cardbus_attach_args *caa,
273 1.1 mcr int minbus, int maxbus)
274 1.1 mcr {
275 1.1 mcr struct rbus_pci_addr_fixup_context rct;
276 1.1 mcr int size, busnum;
277 1.1 mcr bus_addr_t start;
278 1.1 mcr bus_space_handle_t handle;
279 1.1 mcr u_int32_t reg;
280 1.1 mcr
281 1.1 mcr rct.csc=csc;
282 1.1 mcr rct.ct=ct;
283 1.1 mcr rct.sc=sc;
284 1.1 mcr rct.caa=caa;
285 1.1 mcr rct.minbus = minbus;
286 1.1 mcr rct.maxbus = maxbus;
287 1.1 mcr size = sizeof(bus_size_t)*(maxbus+1);
288 1.1 mcr rct.bussize_ioreqs = alloca(size);
289 1.1 mcr rct.bussize_memreqs = alloca(size);
290 1.1 mcr rct.iobustags = alloca(maxbus * sizeof(rbus_tag_t));
291 1.1 mcr rct.membustags = alloca(maxbus * sizeof(rbus_tag_t));
292 1.1 mcr
293 1.1 mcr bzero(rct.bussize_ioreqs, size);
294 1.1 mcr bzero(rct.bussize_memreqs, size);
295 1.1 mcr
296 1.1 mcr printf("%s: sizing buses %d-%d\n",
297 1.1 mcr rct.csc->sc_dev.dv_xname,
298 1.1 mcr minbus, maxbus);
299 1.1 mcr
300 1.1 mcr pci_device_foreach_min(pc, minbus, maxbus,
301 1.1 mcr rbus_pci_phys_countspace, &rct);
302 1.1 mcr
303 1.1 mcr /*
304 1.1 mcr * we need to determine amount of address space for each
305 1.1 mcr * bus. To do this, we have to roll up amounts and then
306 1.1 mcr * we need to divide up the cardbus's extent to allocate
307 1.1 mcr * some space to each bus.
308 1.1 mcr */
309 1.1 mcr
310 1.1 mcr for(busnum=maxbus; busnum > minbus; busnum--) {
311 1.1 mcr if(pci_bus_parent[busnum] != 0) {
312 1.1 mcr if(pci_bus_parent[busnum] < minbus ||
313 1.1 mcr pci_bus_parent[busnum] >= maxbus) {
314 1.1 mcr printf("%s: bus %d has illegal parent %d\n",
315 1.1 mcr rct.csc->sc_dev.dv_xname,
316 1.1 mcr busnum, pci_bus_parent[busnum]);
317 1.1 mcr continue;
318 1.1 mcr }
319 1.1 mcr
320 1.1 mcr /* first round amount of space up */
321 1.1 mcr rct.bussize_ioreqs[busnum] =
322 1.1 mcr rbus_round_up(rct.bussize_ioreqs[busnum], PPB_IO_MIN);
323 1.1 mcr rct.bussize_ioreqs[pci_bus_parent[busnum]] +=
324 1.1 mcr rct.bussize_ioreqs[busnum];
325 1.1 mcr
326 1.1 mcr rct.bussize_memreqs[busnum] =
327 1.1 mcr rbus_round_up(rct.bussize_memreqs[busnum], PPB_MEM_MIN);
328 1.1 mcr rct.bussize_memreqs[pci_bus_parent[busnum]] +=
329 1.1 mcr rct.bussize_memreqs[busnum];
330 1.1 mcr
331 1.1 mcr }
332 1.1 mcr }
333 1.1 mcr
334 1.1 mcr rct.bussize_ioreqs[minbus] =
335 1.1 mcr rbus_round_up(rct.bussize_ioreqs[minbus], 4096);
336 1.1 mcr rct.bussize_memreqs[minbus] =
337 1.1 mcr rbus_round_up(rct.bussize_memreqs[minbus], 8);
338 1.1 mcr
339 1.1 mcr printf("%s: total needs IO %08lx and MEM %08lx\n",
340 1.1 mcr rct.csc->sc_dev.dv_xname,
341 1.1 mcr rct.bussize_ioreqs[minbus], rct.bussize_memreqs[minbus]);
342 1.1 mcr
343 1.1 mcr if(!caa->ca_rbus_iot) {
344 1.1 mcr panic("no iot bus");
345 1.1 mcr }
346 1.1 mcr
347 1.1 mcr if(rct.bussize_ioreqs[minbus]) {
348 1.1 mcr if(rbus_space_alloc(caa->ca_rbus_iot, 0,
349 1.1 mcr rct.bussize_ioreqs[minbus],
350 1.1 mcr rct.bussize_ioreqs[minbus]-1 /* mask */,
351 1.1 mcr rct.bussize_ioreqs[minbus] /* align */,
352 1.1 mcr /* flags */ 0,
353 1.1 mcr &start,
354 1.1 mcr &handle) != 0) {
355 1.1 mcr panic("rbus_ppb: can not allocate %ld bytes in IO bus %d\n",
356 1.1 mcr rct.bussize_ioreqs[minbus], minbus);
357 1.1 mcr }
358 1.1 mcr rct.iobustags[minbus]=rbus_new(caa->ca_rbus_iot,
359 1.1 mcr start,
360 1.1 mcr rct.bussize_ioreqs[minbus],
361 1.1 mcr 0 /* offset to add to physical address
362 1.1 mcr to make processor address */,
363 1.1 mcr RBUS_SPACE_DEDICATE);
364 1.1 mcr }
365 1.1 mcr
366 1.1 mcr if(rct.bussize_memreqs[minbus]) {
367 1.1 mcr if(rbus_space_alloc(caa->ca_rbus_memt, 0,
368 1.1 mcr rct.bussize_memreqs[minbus],
369 1.1 mcr rct.bussize_memreqs[minbus]-1 /* mask */,
370 1.1 mcr rct.bussize_memreqs[minbus] /* align */,
371 1.1 mcr /* flags */ 0,
372 1.1 mcr &start,
373 1.1 mcr &handle) != 0) {
374 1.1 mcr panic("%s: can not allocate %ld bytes in MEM bus %d\n",
375 1.1 mcr rct.csc->sc_dev.dv_xname,
376 1.1 mcr rct.bussize_memreqs[minbus], minbus);
377 1.1 mcr }
378 1.1 mcr rct.membustags[minbus]=rbus_new(caa->ca_rbus_memt,
379 1.1 mcr start,
380 1.1 mcr rct.bussize_memreqs[minbus],
381 1.1 mcr 0 /* offset to add to physical
382 1.1 mcr address to make processor
383 1.1 mcr address */,
384 1.1 mcr RBUS_SPACE_DEDICATE);
385 1.1 mcr }
386 1.1 mcr
387 1.1 mcr for(busnum=minbus+1; busnum <= maxbus; busnum++) {
388 1.1 mcr int busparent;
389 1.1 mcr
390 1.1 mcr busparent = pci_bus_parent[busnum];
391 1.1 mcr
392 1.1 mcr printf("%s: bus %d (parent=%d) needs IO %08lx and MEM %08lx\n",
393 1.1 mcr rct.csc->sc_dev.dv_xname,
394 1.1 mcr busnum,
395 1.1 mcr busparent,
396 1.1 mcr rct.bussize_ioreqs[busnum],
397 1.1 mcr rct.bussize_memreqs[busnum]);
398 1.1 mcr
399 1.1 mcr if(busparent > maxbus) {
400 1.1 mcr panic("rbus_ppb: illegal parent");
401 1.1 mcr }
402 1.1 mcr
403 1.1 mcr if(rct.bussize_ioreqs[busnum]) {
404 1.1 mcr if(rbus_space_alloc(rct.iobustags[busparent],
405 1.1 mcr 0,
406 1.1 mcr rct.bussize_ioreqs[busnum],
407 1.1 mcr rct.bussize_ioreqs[busnum]-1 /*mask */,
408 1.1 mcr rct.bussize_ioreqs[busnum] /* align */,
409 1.1 mcr /* flags */ 0,
410 1.1 mcr &start,
411 1.1 mcr &handle) != 0) {
412 1.1 mcr panic("rbus_ppb: can not allocate %ld bytes in IO bus %d\n",
413 1.1 mcr rct.bussize_ioreqs[busnum], busnum);
414 1.1 mcr }
415 1.1 mcr rct.iobustags[busnum]=rbus_new(rct.iobustags[busparent],
416 1.1 mcr start,
417 1.1 mcr rct.bussize_ioreqs[busnum],
418 1.1 mcr 0 /* offset to add to physical
419 1.1 mcr address
420 1.1 mcr to make processor address */,
421 1.1 mcr RBUS_SPACE_DEDICATE);
422 1.1 mcr
423 1.1 mcr /* program the bridge */
424 1.1 mcr
425 1.1 mcr /* enable I/O space */
426 1.1 mcr reg = pci_conf_read(pc, pci_bus_tag[busnum],
427 1.1 mcr PCI_COMMAND_STATUS_REG);
428 1.1 mcr reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE;
429 1.1 mcr pci_conf_write(pc, pci_bus_tag[busnum],
430 1.1 mcr PCI_COMMAND_STATUS_REG, reg);
431 1.1 mcr
432 1.1 mcr /* now init the limit register for I/O */
433 1.1 mcr pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_IOSTATUS,
434 1.1 mcr (((start & 0xf000) >> 8) << PPB_IOBASE_SHIFT) |
435 1.1 mcr ((((start +
436 1.1 mcr rct.bussize_ioreqs[busnum] +
437 1.1 mcr 4095) & 0xf000) >> 8) << PPB_IOLIMIT_SHIFT));
438 1.1 mcr }
439 1.1 mcr
440 1.1 mcr if(rct.bussize_memreqs[busnum]) {
441 1.1 mcr if(rbus_space_alloc(rct.membustags[busparent],
442 1.1 mcr 0,
443 1.1 mcr rct.bussize_memreqs[busnum] /* size */,
444 1.1 mcr rct.bussize_memreqs[busnum]-1 /*mask */,
445 1.1 mcr rct.bussize_memreqs[busnum] /* align */,
446 1.1 mcr /* flags */ 0,
447 1.1 mcr &start,
448 1.1 mcr &handle) != 0) {
449 1.1 mcr panic("rbus_ppb: can not allocate %ld bytes in MEM bus %d\n",
450 1.1 mcr rct.bussize_memreqs[busnum], busnum);
451 1.1 mcr }
452 1.1 mcr rct.membustags[busnum]=rbus_new(rct.membustags[busparent],
453 1.1 mcr start,
454 1.1 mcr rct.bussize_memreqs[busnum],
455 1.1 mcr 0 /* offset to add to physical
456 1.1 mcr address to make processor
457 1.1 mcr address */,
458 1.1 mcr RBUS_SPACE_DEDICATE);
459 1.1 mcr
460 1.1 mcr /* program the bridge */
461 1.1 mcr /* enable memory space */
462 1.1 mcr reg = pci_conf_read(pc, pci_bus_tag[busnum],
463 1.1 mcr PCI_COMMAND_STATUS_REG);
464 1.1 mcr reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
465 1.1 mcr pci_conf_write(pc, pci_bus_tag[busnum],
466 1.1 mcr PCI_COMMAND_STATUS_REG, reg);
467 1.1 mcr
468 1.1 mcr /* now init the limit register for memory */
469 1.1 mcr pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_MEM,
470 1.1 mcr ((start & PPB_MEM_MASK)
471 1.1 mcr >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT |
472 1.1 mcr (((start +
473 1.1 mcr rct.bussize_memreqs[busnum] +
474 1.1 mcr PPB_MEM_MIN-1) >> PPB_MEM_SHIFT)
475 1.1 mcr << PPB_MEMLIMIT_SHIFT));
476 1.1 mcr
477 1.1 mcr /* and set the prefetchable limits as well */
478 1.1 mcr pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_PREFMEM,
479 1.1 mcr ((start & PPB_MEM_MASK)
480 1.1 mcr >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT |
481 1.1 mcr (((start +
482 1.1 mcr rct.bussize_memreqs[busnum] +
483 1.1 mcr PPB_MEM_MIN-1) >> PPB_MEM_SHIFT)
484 1.1 mcr << PPB_MEMLIMIT_SHIFT));
485 1.1 mcr
486 1.1 mcr /* pci_conf_print(pc, pci_bus_tag[busnum], NULL); */
487 1.1 mcr }
488 1.1 mcr }
489 1.1 mcr
490 1.1 mcr printf("%s: configuring buses %d-%d\n",
491 1.1 mcr rct.csc->sc_dev.dv_xname,
492 1.1 mcr minbus, maxbus);
493 1.1 mcr pci_device_foreach_min(pc, minbus, maxbus,
494 1.1 mcr rbus_pci_phys_allocate, &rct);
495 1.1 mcr }
496 1.1 mcr
497 1.1 mcr static void
498 1.1 mcr rbus_pci_phys_countspace(pc, tag, context)
499 1.1 mcr pci_chipset_tag_t pc;
500 1.1 mcr pcitag_t tag;
501 1.1 mcr void *context;
502 1.1 mcr {
503 1.1 mcr int bus, device, function;
504 1.1 mcr struct rbus_pci_addr_fixup_context *rct =
505 1.1 mcr (struct rbus_pci_addr_fixup_context *)context;
506 1.1 mcr
507 1.1 mcr pci_decompose_tag(pc, tag, &bus, &device, &function);
508 1.1 mcr
509 1.1 mcr printf("%s: configuring device %02x:%02x:%02x\n",
510 1.1 mcr rct->csc->sc_dev.dv_xname,
511 1.1 mcr bus, device, function);
512 1.1 mcr
513 1.1 mcr pciaddr_resource_manage(pc, tag,
514 1.1 mcr rbus_do_phys_countspace, context);
515 1.1 mcr }
516 1.1 mcr
517 1.1 mcr
518 1.1 mcr int
519 1.1 mcr rbus_do_phys_countspace(pc, tag, mapreg, ctx, type, addr, size)
520 1.1 mcr pci_chipset_tag_t pc;
521 1.1 mcr pcitag_t tag;
522 1.1 mcr void *ctx;
523 1.1 mcr int mapreg, type;
524 1.1 mcr bus_addr_t *addr;
525 1.1 mcr bus_size_t size;
526 1.1 mcr {
527 1.1 mcr struct rbus_pci_addr_fixup_context *rct =
528 1.1 mcr (struct rbus_pci_addr_fixup_context *)ctx;
529 1.1 mcr int bus, device, function;
530 1.1 mcr
531 1.1 mcr pci_decompose_tag(pc, tag, &bus, &device, &function);
532 1.1 mcr
533 1.1 mcr if(size > (1<<24)) {
534 1.1 mcr printf("%s: skipping huge space request of size=%08x\n",
535 1.1 mcr rct->csc->sc_dev.dv_xname, (unsigned int)size);
536 1.1 mcr return 0;
537 1.1 mcr }
538 1.1 mcr
539 1.1 mcr if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) {
540 1.1 mcr rct->bussize_ioreqs[bus] += size;
541 1.1 mcr } else {
542 1.1 mcr rct->bussize_memreqs[bus]+= size;
543 1.1 mcr }
544 1.1 mcr
545 1.1 mcr return 0;
546 1.1 mcr }
547 1.1 mcr
548 1.1 mcr static void
549 1.1 mcr rbus_pci_phys_allocate(pc, tag, context)
550 1.1 mcr pci_chipset_tag_t pc;
551 1.1 mcr pcitag_t tag;
552 1.1 mcr void *context;
553 1.1 mcr {
554 1.1 mcr int bus, device, function, command;
555 1.1 mcr struct rbus_pci_addr_fixup_context *rct =
556 1.1 mcr (struct rbus_pci_addr_fixup_context *)context;
557 1.1 mcr //cardbus_chipset_tag_t ct = rct->ct;
558 1.1 mcr // struct cardbus_softc *sc = rct->sc;
559 1.1 mcr
560 1.1 mcr pci_decompose_tag(pc, tag, &bus, &device, &function);
561 1.1 mcr
562 1.1 mcr printf("%s: configuring device %02x:%02x:%02x\n",
563 1.1 mcr rct->csc->sc_dev.dv_xname,
564 1.1 mcr bus, device, function);
565 1.1 mcr
566 1.1 mcr pciaddr_resource_manage(pc, tag,
567 1.1 mcr rbus_do_phys_allocate, context);
568 1.1 mcr
569 1.1 mcr /* now turn the device's memory and I/O on */
570 1.1 mcr command = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
571 1.1 mcr command |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE;
572 1.1 mcr pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, command);
573 1.1 mcr }
574 1.1 mcr
575 1.1 mcr int
576 1.1 mcr rbus_do_phys_allocate(pc, tag, mapreg, ctx, type, addr, size)
577 1.1 mcr pci_chipset_tag_t pc;
578 1.1 mcr pcitag_t tag;
579 1.1 mcr void *ctx;
580 1.1 mcr int mapreg, type;
581 1.1 mcr bus_addr_t *addr;
582 1.1 mcr bus_size_t size;
583 1.1 mcr {
584 1.1 mcr struct rbus_pci_addr_fixup_context *rct =
585 1.1 mcr (struct rbus_pci_addr_fixup_context *)ctx;
586 1.1 mcr cardbus_chipset_tag_t ct = rct->ct;
587 1.1 mcr struct cardbus_softc *sc = rct->sc;
588 1.1 mcr cardbus_function_t *cf = sc->sc_cf;
589 1.1 mcr rbus_tag_t rbustag;
590 1.1 mcr bus_space_tag_t bustag;
591 1.1 mcr bus_addr_t mask = size -1;
592 1.1 mcr bus_addr_t base = 0;
593 1.1 mcr bus_space_handle_t handle;
594 1.1 mcr int busflags = 0;
595 1.1 mcr int flags = 0;
596 1.1 mcr char *bustype;
597 1.1 mcr int bus, device, function;
598 1.1 mcr
599 1.1 mcr pci_decompose_tag(pc, tag, &bus, &device, &function);
600 1.1 mcr
601 1.1 mcr /*
602 1.1 mcr * some devices come up with garbage in them (Tulip?)
603 1.1 mcr * we are in charge here, so give them address
604 1.1 mcr * space anyway.
605 1.1 mcr *
606 1.1 mcr * XXX this may be due to no secondary PCI reset!!!
607 1.1 mcr */
608 1.1 mcr #if 0
609 1.1 mcr if (*addr) {
610 1.1 mcr printf("Already allocated space at %08x\n",
611 1.1 mcr (unsigned int)*addr);
612 1.1 mcr return (0);
613 1.1 mcr }
614 1.1 mcr #endif
615 1.1 mcr
616 1.1 mcr if(size > (1<<24)) {
617 1.1 mcr printf("%s: skipping huge space request of size=%08x\n",
618 1.1 mcr rct->csc->sc_dev.dv_xname, (unsigned int)size);
619 1.1 mcr return 0;
620 1.1 mcr }
621 1.1 mcr
622 1.1 mcr if(PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) {
623 1.1 mcr bustag = sc->sc_iot;
624 1.1 mcr rbustag = rct->iobustags[bus];
625 1.1 mcr bustype = "io";
626 1.1 mcr } else {
627 1.1 mcr bustag = sc->sc_memt;
628 1.1 mcr rbustag = rct->membustags[bus];
629 1.1 mcr bustype = "mem";
630 1.1 mcr }
631 1.1 mcr
632 1.1 mcr if((*cf->cardbus_space_alloc)(ct, rbustag, base, size,
633 1.1 mcr mask, size, busflags|flags,
634 1.1 mcr addr, &handle)) {
635 1.1 mcr printf("%s: no available resources (size=%08x) for bar %2d. fixup failed\n",
636 1.1 mcr rct->csc->sc_dev.dv_xname, (unsigned int)size, mapreg);
637 1.1 mcr
638 1.1 mcr *addr = 0;
639 1.1 mcr pci_conf_write(pc, tag, mapreg, *addr);
640 1.1 mcr return (1);
641 1.1 mcr }
642 1.1 mcr
643 1.1 mcr printf("%s: alloc %s space of size %08x for %02d:%02d:%02d -> %08x\n",
644 1.1 mcr rct->csc->sc_dev.dv_xname,
645 1.1 mcr bustype,
646 1.1 mcr (unsigned int)size,
647 1.1 mcr bus, device, function, (unsigned int)*addr);
648 1.1 mcr
649 1.1 mcr /* write new address to PCI device configuration header */
650 1.1 mcr pci_conf_write(pc, tag, mapreg, *addr);
651 1.1 mcr
652 1.1 mcr /* check */
653 1.1 mcr {
654 1.1 mcr DPRINTF(("%s: pci_addr_fixup: ",
655 1.1 mcr rct->csc->sc_dev.dv_xname));
656 1.1 mcr #ifdef CBB_DEBUG
657 1.1 mcr if(rbus_ppb_debug) { pciaddr_print_devid(pc, tag); }
658 1.1 mcr #endif
659 1.1 mcr }
660 1.1 mcr
661 1.1 mcr /* double check that the value got inserted correctly */
662 1.1 mcr if (pciaddr_ioaddr(pci_conf_read(pc, tag, mapreg)) != *addr) {
663 1.1 mcr pci_conf_write(pc, tag, mapreg, 0); /* clear */
664 1.1 mcr printf("%s: fixup failed. (new address=%#x)\n",
665 1.1 mcr rct->csc->sc_dev.dv_xname,
666 1.1 mcr (unsigned)*addr);
667 1.1 mcr return (1);
668 1.1 mcr }
669 1.1 mcr
670 1.1 mcr DPRINTF(("new address 0x%08x\n",
671 1.1 mcr (unsigned)*addr));
672 1.1 mcr
673 1.1 mcr return (0);
674 1.1 mcr }
675 1.1 mcr
676 1.1 mcr static void
677 1.1 mcr ppb_cardbus_attach(parent, self, aux)
678 1.1 mcr struct device *parent, *self;
679 1.1 mcr void *aux;
680 1.1 mcr {
681 1.1 mcr struct ppb_cardbus_softc *csc = (struct ppb_cardbus_softc *) self;
682 1.1 mcr struct cardbus_softc *parent_sc =
683 1.1 mcr (struct cardbus_softc *) csc->sc_dev.dv_parent;
684 1.1 mcr struct cardbus_attach_args *ca = aux;
685 1.1 mcr cardbus_devfunc_t ct = ca->ca_ct;
686 1.1 mcr cardbus_chipset_tag_t cc = ct->ct_cc;
687 1.1 mcr cardbus_function_tag_t cf = ct->ct_cf;
688 1.1 mcr struct pccbb_softc *psc = (struct pccbb_softc *)cc;
689 1.1 mcr struct pcibus_attach_args pba;
690 1.1 mcr char devinfo[256];
691 1.1 mcr pcireg_t busdata;
692 1.1 mcr int mybus, rv;
693 1.1 mcr u_int16_t pciirq;
694 1.1 mcr int minbus, maxbus;
695 1.1 mcr
696 1.1 mcr mybus = ct->ct_bus;
697 1.1 mcr pciirq = 0;
698 1.1 mcr rv = 0;
699 1.1 mcr
700 1.1 mcr /* shut up compiler */
701 1.1 mcr csc->foo=parent_sc->sc_intrline;
702 1.1 mcr
703 1.1 mcr
704 1.1 mcr pci_devinfo(ca->ca_id, ca->ca_class, 0, devinfo);
705 1.1 mcr printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(ca->ca_class));
706 1.1 mcr
707 1.1 mcr busdata = cardbus_conf_read(cc, cf, ca->ca_tag, PPB_REG_BUSINFO);
708 1.1 mcr minbus = pcibios_max_bus;
709 1.1 mcr
710 1.1 mcr if (PPB_BUSINFO_SECONDARY(busdata) == 0) {
711 1.1 mcr printf("%s: not configured by system firmware calling pci_bus_fixup(%d)\n",
712 1.1 mcr self->dv_xname, 0);
713 1.1 mcr
714 1.1 mcr /*
715 1.1 mcr * first, pull the reset wire on the secondary bridge
716 1.1 mcr * to clear all devices
717 1.1 mcr */
718 1.1 mcr busdata = cardbus_conf_read(cc, cf, ca->ca_tag,
719 1.1 mcr PPB_REG_BRIDGECONTROL);
720 1.1 mcr cardbus_conf_write(cc, cf, ca->ca_tag, PPB_REG_BRIDGECONTROL,
721 1.1 mcr busdata | PPB_BC_SECONDARY_RESET);
722 1.1 mcr delay(1);
723 1.1 mcr cardbus_conf_write(cc, cf, ca->ca_tag, PPB_REG_BRIDGECONTROL,
724 1.1 mcr busdata);
725 1.1 mcr
726 1.1 mcr /* then go initialize the bridge control registers */
727 1.1 mcr maxbus = pci_bus_fixup(psc->sc_pc, 0);
728 1.1 mcr }
729 1.1 mcr
730 1.1 mcr busdata = cardbus_conf_read(cc, cf, ca->ca_tag, PPB_REG_BUSINFO);
731 1.1 mcr if(PPB_BUSINFO_SECONDARY(busdata) == 0) {
732 1.1 mcr printf("%s: still not configured, not fixable.\n",
733 1.1 mcr self->dv_xname);
734 1.1 mcr return;
735 1.1 mcr }
736 1.1 mcr
737 1.1 mcr #if 0
738 1.1 mcr minbus = PPB_BUSINFO_SECONDARY(busdata);
739 1.1 mcr maxbus = PPB_BUSINFO_SUBORDINATE(busdata);
740 1.1 mcr #endif
741 1.1 mcr
742 1.1 mcr /* now, go and assign addresses for the new devices */
743 1.1 mcr rbus_pci_addr_fixup(csc, cc, parent_sc,
744 1.1 mcr psc->sc_pc,
745 1.1 mcr ca,
746 1.1 mcr minbus, maxbus);
747 1.1 mcr
748 1.1 mcr /*
749 1.1 mcr * now configure all connected devices to the IRQ which
750 1.1 mcr * was assigned to this slot, as they will all arrive from
751 1.1 mcr * that IRQ.
752 1.1 mcr */
753 1.1 mcr rbus_intr_fixup(psc->sc_pc, minbus, maxbus, ca->ca_intrline);
754 1.1 mcr
755 1.1 mcr /*
756 1.1 mcr * enable direct routing of interrupts. We do this because
757 1.1 mcr * we can not manage to get pccb_intr_establish() called until
758 1.1 mcr * PCI subsystem is merged with rbus. The major thing that this
759 1.1 mcr * routine does is avoid calling the driver's interrupt routine
760 1.1 mcr * when the card has been removed.
761 1.1 mcr *
762 1.1 mcr * The rbus_ppb.c can not cope with card desertions until the merging
763 1.1 mcr * anyway.
764 1.1 mcr */
765 1.1 mcr pccbb_intr_route(psc);
766 1.1 mcr
767 1.1 mcr /*
768 1.1 mcr * Attach the PCI bus than hangs off of it.
769 1.1 mcr *
770 1.1 mcr * XXX Don't pass-through Memory Read Multiple. Should we?
771 1.1 mcr * XXX Consult the spec...
772 1.1 mcr */
773 1.1 mcr pba.pba_busname = "pci";
774 1.1 mcr pba.pba_iot = ca->ca_iot;
775 1.1 mcr pba.pba_memt = ca->ca_memt;
776 1.1 mcr pba.pba_dmat = ca->ca_dmat;
777 1.1 mcr pba.pba_pc = psc->sc_pc;
778 1.1 mcr pba.pba_flags = PCI_FLAGS_IO_ENABLED|PCI_FLAGS_MEM_ENABLED;
779 1.1 mcr pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata);
780 1.1 mcr /*pba.pba_intrswiz = parent_sc->sc_intrswiz; */
781 1.1 mcr pba.pba_intrtag = psc->sc_pa.pa_intrtag;
782 1.1 mcr
783 1.1 mcr config_found(self, &pba, rppbprint);
784 1.1 mcr }
785 1.1 mcr
786 1.1 mcr void
787 1.1 mcr ppb_cardbus_setup(struct ppb_softc * sc)
788 1.1 mcr {
789 1.1 mcr struct ppb_cardbus_softc *csc = (struct ppb_cardbus_softc *) sc;
790 1.1 mcr #if 0
791 1.1 mcr cardbus_chipset_tag_t cc = psc->sc_cc;
792 1.1 mcr cardbus_function_tag_t cf = psc->sc_cf;
793 1.1 mcr #endif
794 1.1 mcr
795 1.1 mcr /* shut up compiler */
796 1.1 mcr csc->foo=2;
797 1.1 mcr
798 1.1 mcr printf("ppb_cardbus_setup called\n");
799 1.1 mcr #if 0
800 1.1 mcr /* not sure what to do here */
801 1.1 mcr cardbustag_t tag = cardbus_make_tag(cc, cf, csc->ct->ct_bus,
802 1.1 mcr csc->ct->ct_dev, csc->ct->ct_func);
803 1.1 mcr
804 1.1 mcr command = Cardbus_conf_read(csc->ct, tag, CARDBUS_COMMAND_STATUS_REG);
805 1.1 mcr if (csc->base0_reg) {
806 1.1 mcr Cardbus_conf_write(csc->ct, tag,
807 1.1 mcr CARDBUS_BASE0_REG, csc->base0_reg);
808 1.1 mcr (cf->cardbus_ctrl) (cc, CARDBUS_MEM_ENABLE);
809 1.1 mcr command |= CARDBUS_COMMAND_MEM_ENABLE |
810 1.1 mcr CARDBUS_COMMAND_MASTER_ENABLE;
811 1.1 mcr } else if (csc->base1_reg) {
812 1.1 mcr Cardbus_conf_write(csc->ct, tag,
813 1.1 mcr CARDBUS_BASE1_REG, csc->base1_reg);
814 1.1 mcr (cf->cardbus_ctrl) (cc, CARDBUS_IO_ENABLE);
815 1.1 mcr command |= (CARDBUS_COMMAND_IO_ENABLE |
816 1.1 mcr CARDBUS_COMMAND_MASTER_ENABLE);
817 1.1 mcr }
818 1.1 mcr
819 1.1 mcr (cf->cardbus_ctrl) (cc, CARDBUS_BM_ENABLE);
820 1.1 mcr
821 1.1 mcr /* enable the card */
822 1.1 mcr Cardbus_conf_write(csc->ct, tag, CARDBUS_COMMAND_STATUS_REG, command);
823 1.1 mcr #endif
824 1.1 mcr }
825 1.1 mcr
826 1.1 mcr int
827 1.1 mcr ppb_cardbus_enable(struct ppb_softc * sc)
828 1.1 mcr {
829 1.1 mcr #if 0
830 1.1 mcr struct ppb_cardbus_softc *csc = (struct fxp_cardbus_softc *) sc;
831 1.1 mcr struct cardbus_softc *psc =
832 1.1 mcr (struct cardbus_softc *) sc->sc_dev.dv_parent;
833 1.1 mcr cardbus_chipset_tag_t cc = psc->sc_cc;
834 1.1 mcr cardbus_function_tag_t cf = psc->sc_cf;
835 1.1 mcr
836 1.1 mcr Cardbus_function_enable(csc->ct);
837 1.1 mcr
838 1.1 mcr fxp_cardbus_setup(sc);
839 1.1 mcr
840 1.1 mcr /* Map and establish the interrupt. */
841 1.1 mcr
842 1.1 mcr sc->sc_ih = cardbus_intr_establish(cc, cf, psc->sc_intrline, IPL_NET,
843 1.1 mcr fxp_intr, sc);
844 1.1 mcr if (NULL == sc->sc_ih) {
845 1.1 mcr printf("%s: couldn't establish interrupt\n",
846 1.1 mcr sc->sc_dev.dv_xname);
847 1.1 mcr return 1;
848 1.1 mcr }
849 1.1 mcr
850 1.1 mcr printf("%s: interrupting at %d\n", sc->sc_dev.dv_xname,
851 1.1 mcr psc->sc_intrline);
852 1.1 mcr
853 1.1 mcr #endif
854 1.1 mcr return 0;
855 1.1 mcr }
856 1.1 mcr
857 1.1 mcr void
858 1.1 mcr ppb_cardbus_disable(struct ppb_softc * sc)
859 1.1 mcr {
860 1.1 mcr #if 0
861 1.1 mcr struct cardbus_softc *psc =
862 1.1 mcr (struct cardbus_softc *) sc->sc_dev.dv_parent;
863 1.1 mcr cardbus_chipset_tag_t cc = psc->sc_cc;
864 1.1 mcr cardbus_function_tag_t cf = psc->sc_cf;
865 1.1 mcr
866 1.1 mcr /* Remove interrupt handler. */
867 1.1 mcr cardbus_intr_disestablish(cc, cf, sc->sc_ih);
868 1.1 mcr
869 1.1 mcr Cardbus_function_disable(((struct fxp_cardbus_softc *) sc)->ct);
870 1.1 mcr #endif
871 1.1 mcr }
872 1.1 mcr
873 1.1 mcr static int
874 1.1 mcr ppb_cardbus_detach(self, flags)
875 1.1 mcr struct device *self;
876 1.1 mcr int flags;
877 1.1 mcr {
878 1.1 mcr /* struct ppb_softc *sc = (struct ppb_softc *) self;*/
879 1.1 mcr struct ppb_cardbus_softc *csc = (struct ppb_cardbus_softc *) self;
880 1.1 mcr
881 1.1 mcr #if 0
882 1.1 mcr struct cardbus_devfunc *ct = csc->ct;
883 1.1 mcr int rv, reg;
884 1.1 mcr
885 1.1 mcr #ifdef DIAGNOSTIC
886 1.1 mcr if (ct == NULL)
887 1.1 mcr panic("%s: data structure lacks\n", sc->sc_dev.dv_xname);
888 1.1 mcr #endif
889 1.1 mcr
890 1.1 mcr rv = fxp_detach(sc);
891 1.1 mcr if (rv == 0) {
892 1.1 mcr /*
893 1.1 mcr * Unhook the interrupt handler.
894 1.1 mcr */
895 1.1 mcr cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, sc->sc_ih);
896 1.1 mcr
897 1.1 mcr /*
898 1.1 mcr * release bus space and close window
899 1.1 mcr */
900 1.1 mcr if (csc->base0_reg)
901 1.1 mcr reg = CARDBUS_BASE0_REG;
902 1.1 mcr else
903 1.1 mcr reg = CARDBUS_BASE1_REG;
904 1.1 mcr Cardbus_mapreg_unmap(ct, reg, sc->sc_st, sc->sc_sh, csc->size);
905 1.1 mcr }
906 1.1 mcr return (rv);
907 1.1 mcr
908 1.1 mcr #endif
909 1.1 mcr csc->foo=1;
910 1.1 mcr return 0;
911 1.1 mcr
912 1.1 mcr }
913 1.1 mcr
914 1.1 mcr int
915 1.1 mcr ppb_activate(self, act)
916 1.1 mcr struct device *self;
917 1.1 mcr enum devact act;
918 1.1 mcr {
919 1.1 mcr printf("ppb_activate called\n");
920 1.1 mcr return 0;
921 1.1 mcr }
922 1.1 mcr
923